1

DMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

EC6411 CIRCUITS AND SIMULATION INTEGRATED

LABORATORY MANUAL

IV SEMESTER

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I .Sylabus

EC6411 CIRCUITS AND SIMULATION INTEGRATED LABORATORY L T P C

0 0 3 2

OBJECTIVES:

To gain hands on experience in designing electronic circuits. To learn simulation software used in circuit design. To learn the fundamental principles of amplifier circuits To understand Bias in Amplifier circuits To differentiate feedback amplifiers and oscillators. To study the characteristic of source follower To understand the concepts of multivibrators

DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS 1. Series and Shunt feedback amplifiers-Frequency response, Input and output impedance calculation 2. RC Phase shift oscillator and Wien Bridge Oscillator 3. Hartley Oscillator and Colpitts Oscillator 4. Single Tuned Amplifier 5. RC Integrator and Differentiator circuits 6. Astable and Monostable multivibrators 7. Clippers and Clampers 8. Free running Blocking Oscillators SIMULATION USING SPICE (Using Transistor): 1. Tuned Collector Oscillator 2. Twin -T Oscillator / Wein Bridge Oscillator 3. Double and Stagger tuned Amplifiers 4. Bistable Multivibrator 5. Schmitt Trigger circuit with Predictable hysteresis 6. Monostable multivibrator with emitter timing and base timing 7. Voltage and Current Time base circuits TOTAL: 45 PERIODS

OUTCOMES: On completion of this lab course, the students will be able to

Analyze various types of feedback amplifiers Design oscillators, tuned amplifiers, wave-shaping circuits and multivibrators Design and simulate feedback amplifiers, oscillators, tuned amplifiers, wave-shaping

circuits and multivibrators using SPICE Tool.

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S.No Date List Of Experiments Page No Faculty

Signature

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EXPERIMENT :1

CLIPPER AND CLAMPER CIRCUITS 1.1 AIM: To construct and design the clipper and clamper circuits using diodes. 1.2 REQUIREMENTS:

S.No

Equipment

List

Name Range Quantity

1.

Equipments

Function generator (0-30)MHz 1

CRO (0-20)V 1

Regulated Power Supply

(0-30)V 1

2.

Components

Diode IN4007 1

Resistor 1k 1

Capacitor 1uf 2

3.

Other accessories

Bread board - 1

Connecting Wires Single strand As required

1.3. DESIGN PROCEDURE:

Given f=1 kHz, T=t=1/f=1x10-3 sec=RC Assume, C=1uF Then, R=1KΩ

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1.4 POSITIVE CLIPPER

1.4.1 CIRCUIT DIAGRAM:

FIG.1.1 1.4.2 MODEL TABULATION:

Positive

Cycle (V)

Negative

Cycle( V)

Time (ms)

Input Output

TAB 1.1

1.4.3 MODEL GRAPH:

FIG.1.2

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1.5 NEGATIVE CLIPPER:

1.5.1 CIRCUIT DIAGRAM:

FIG.1.3

1.5.2 MODEL TABULATION:

Positive

Cycle (V)

Negative

Cycle( V)

Time (ms)

Input

Output

TAB 1.2

1.5.3 MODEL GRAPH:

FIG.1.4

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1.6 CLAMPER CIRCUIT:

1.6.1 POSITIVE CLAMPER CIRCUIT DIAGRAM:

FIG.1.5

1.6.2 MODEL TABULATION:

Positive

Cycle (V)

Negative

Cycle( V)

Time (ms)

Input

Output

TAB 1.3

1.6.3 MODEL GRAPH:

FIG.1.6

Vin=5V

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1.7.1 NEGATIVE CLAMPER CIRCUIT DIAGRAM:

FIG.1.7 1.7.2 MODEL TABULATION:

Positive

Cycle (V)

Negative

Cycle( V)

Time (ms)

Input

Output

TAB 1.5

1.7.3 MODEL GRAPH

FIG:1.8

Vin=5V

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1.8 THEORY

CLIPPER: A Clipper is a circuit that removes either the positive or negative part of a waveform. For a positive clipper only the negative half cycle will appear as output. CLAMPER: A Clamper circuit is a circuit that adds a dc voltage to the signal. A positive clamper shifts the ac reference level upto a dc level.

WORKING: During the positive half cycle, the diode turns on and looks like a short circuit across the output terminals. Ideally, the output voltage is zero. But practically, the diode voltage is 0.7 V while conducting. On the negative half cycle, the diode is open and hence the negative half cycle appear across the output. APPLICATION:

Used for wave shaping To protect sensitive circuits

1.9 PROCEDURE:

1. Connect as per the circuit diagram. 2. Set the signal voltage (say 5V, 1 KHz) using signal generator. 3. Observe the output waveform using CRO. 4. Sketch the output waveform.

1.10 INFERENCE:

Thus the output waveform for Clipper and clamper was observed and its readings

are tabulated. 1.11 CONCLUSON:

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1.12 VIVA QUESTIONS:

1. What are the other names of clipper circuits?

2. What is combinational clipper?

3. Why clippers are used in TV receivers.

4. Give one application of clamper.

5. What are biased clipper and clamper?

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WORK SHEET

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EXPERIMENT :2

INTEGRATOR AND DIFFERENTIATOR 2.1 AIM: To design and construct a differentiator and integrator circuit. 2.2 REQUIREMENTS:

S.No

Equipment

List

Name Range Quantity

1.

Equipments

Function generator (0-30)MHz 1

CRO (0-20)V 1

Regulated Power Supply

(0-30)V 1

2.

Components

Resistor 1 k 1

Capacitor 1 uf 1

3.

Other accessories

Bread board - 1

Connecting Wires Single strand As required

2.3 THEORY:

Differentiator: Differentiator is a circuit which differentiates the input signal, it allows high order frequency and blocks low order frequency. If time constant is very low it acts as a differentiator. In this circuit input is continuous pulse with high and low value. Integrator: In a low pass filter when the time constant is very large it acts as an integrator. In this the voltage drop across C will be very small in comparison with the drop across resistor R. So total input appears across the R.

2.4 PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Set the signal voltage. 3. Observe the output waveform. 4. Sketch the output waveform.

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2.5. INTEGRATOR:

2.5.1 CIRCUIT DIAGRAM:

FIG.2.1 2.5.2 MODEL TABULATION:

Amplitude(V) Time(ms) Frequency(KHz)

TAB 2.2

2.5.3 MODEL GRAPH:

FIG.2.2

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2.6 DIFFERENTIATOR 2.6.1 CIRCUIT DIAGRAM:

FIG.2.3

2.5.2 MODEL TABULATION:

Amplitude(V) Time(ms) Frequency(KHz)

TAB 2.2

2.5.3 MODEL GRAPH:

FIG.2.4

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2.6 INFERENCE: Thus the integrator and differentiator is constructed and output waveform is observed and readings were tabulated.

2.7 CONCLUSON:

2.8 VIVA QUESTIONS:

1. What is wave shaping circuit?

2. What are the components used in wave shaping circuits.

3. When HPF acts as a differentiator

4. When LPF acts as an integrator.

5. How triangular waveform is obtained using integrator.

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WORK SHEET

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EXPERIMENT :3

VOLTAGE SHUNT FEEDBACK AMPLIFIER

3.1 AIM: To design and study frequency response of voltage shunt feedback amplifier. 3.2 REQUIREMENTS:

S.No

Equipment

List

Name Range Quantity

1.

Equipments

Signal generator (0-30)MHz 1

CRO (0-20)V 1

Regulated Power Supply

(0-30)V 1

2.

Components

Resistor 3k, 1.1 k,5k 2.5 k,1k,

1

Capacitor 66F, 30F,58 µf

1

Transistors BC 107 1

3.

Other accessories

Bread board - 1

Connecting Wires Single strand As required

TAB 3.1

3.3 DESIGN PROCEDURE:

Given specifications: VCC= 10V, IC=1.2mA, AV= 30, fI = 1 kHz, S=2, hFE= 150, β=0.4 The feedback factor, β= - 1/RF= +1/0.4=2.5KΏ (i) To calculate RC: The voltage gain is given by, AV= -hfe (RC|| RF) / hie h ie = β re re = 26mV / IE = 26mV / 1.2mA = 21.6 hie = 150 x 21.6 =3.2K Apply KVL to output loop, VCC= IC RC + VCE+ IE RE ----- (1) Where VE = IE RE (IC= IE) VE= VCC / 10= 1V Therefore RE= 1/1.2x10-3=0.8K= 1KΏ

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VCE= VCC/2= 5V From equation (1), RC= 3 KΏ (ii) To calculate R1&R2: S=1+ (RB/RE) RB= (S-1) RE= R1 || R2 =1KΏ RB= R 1R2 / R1+ R2------- (2) VB= VBE + VE = 0.7+ 1= 1.7V VB= VCC R2 / R1+ R2 ------- (3) Solving equation (2) & (3), R1= 5 KΏ & R2= 1.1KΏ

(iii) To calculate Resistance: Output resistance is given by, RO= RC || RF

RO= 1.3KΏ input impedance is given by, Ri = (RB|| RF) || hie = 0.6KΏ Trans-resistance is given by, Rm= -hfe (RB|| RF)( RC || RF) / (RB|| RF)+ hie Rm= 0.06KΏ AC parameter with feedback network: (i) Input Impedance: Rif = Ri /D (where D= 1+β Rm) Therefore D = 25 Rif= 24 Input coupling capacitor is given by, Xci= Rif / 10= 2.4 (since XCi << Rif) Ci = 1/ 2пfXCi =66µf (ii) Output impedance: ROf= RO/ D = 52 Output coupling capacitor: XCO= Rof /10= 5.2 CO = 1/ 2пfXCO= 30µf (iii) Emitter capacitor: XCE << R’E = R’/10 R’E= RE|| ( hie +RB) / (1+hfe) XCE= 2.7 Therefore CE= 58µf

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3.4 WITHOUT FEED BACK 3.4.1 CIRCUIT DIAGRAM:

C1

1n

RC 3K

R5

1k

+10V

Rs

1k

VCC

CE

58uf

Vi5V

Q1

Ci

66uf

R1

5K

R2

1.1K

FIG.3.1

3.5 WITH FEED BACK 3.5.1 CIRCUIT DIAGRAM

FIG.3.2

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3.6 MODEL TABULATION: 3.6 .1 Without feedback:

Vi=

Sl. No Frequency Output Voltage Gain = V0/Vi Gain = 20 log(V0/Vi)

(Hz) (V0) (volts) (dB)

TAB 3.3

3.6.2 With feedback: Vi=

Sl. No Frequency Output Voltage Gain = V0/Vi Gain = 20 log(V0/Vi)

(Hz) (V0) (volts) (dB)

TAB 3.4 3.7 MODEL GRAPH:

FIG.3.3

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3.8 THEORY: Negative feedback in general increases the bandwidth of the transfer

function stabilized by the specific type of feedback used in a circuit. In Voltage

shunt feedback amplifier, consider a common emitter stage with a resistance R’

connected from collector to base. This is a case of voltage shunt feedback and

we expect the bandwidth of the Trans resistance to be improved due to the

feedback through R’. The voltage source is represented by its Norton’s

equivalent current source Is=Vs/Rs.

3.9 PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 10V; set input voltage using audio frequency oscillator.

3. By varying audio frequency oscillator take down output frequency oscillator voltage for difference in frequency.

4. Calculate the gain in dB

5. Plot gain Vs frequency curve in semi-log sheet.

6. Repeat the steps 1 to 6 with feedback

7. Compare this response with respect to the amplifier without feedback.

3.10 INFERENCE:

Thus voltage shunt feedback amplifier is designed and studied its performance.

Parameters Theoretical Practical With Feed Back Without Feed Back With Feed Back Without Feed Back

Input Impedance Output Impedance

Gain(midband) Bandwidth

TAB 3.5

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3.11 VIVA QUESTIONS:

1. Compare the bandwidth of feedback amplifier.

2. Give the stability of gain with feedback.

3. Which sampling and mixing network is used in Voltage shunt feed back amplifier,

4. Calculate the input impedance for with feed back.

5. What type of feedback is used in amplifier?

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WORK SHEET

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EXPERIMENT :4

CURRENT SERIES FEEDBACK AMPLIFER

4.1 AIM: To design a negative feedback amplifier, and to draw its frequency response.

4.2 REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 AFO (0-1)MHz 1 2 CRO (0-20)MHz 1 3 Resistors 1.5 K,6KΏ,2K,

14k,2.3K,10K

Each one

4 Power supply (0-30V) 1 5 Transistors BC 107 1 6 Capacitors 28F, 10F,720F 1

TAB 4.1

4.3 Design examples: VCC= 15V, IC=1mA, AV= 30, fL= 50Hz, S=3, hFE= 100, hie= 1.1KΏ Gain formula is, AV= - hFE RLeff / hie Assume, VCE = VCC / 2 (transistor in active region) VCE = 15 /2=7.5V VE = VCC / 10= 15/10=1.5V Emitter resistance is given by, re =26mV/ IE

Therefore re =26 Ώ hie= hfe re hie =2.6KΏ (i) To calculate RC: Applying KVL to output loop, VCC= IC RC + VCE+ IE RE ----- (1) Where RE = VE / IE (IC= IE) RE = 1.5 / 1x10-3= 1.5KΏ From equation (1), RC= 6KΏ (ii) To calculate RB1&RB2: Since IB is small when compared with IC, IC ~ IE

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VB= VBE + VE= 0.7 + 1.5=2.2V VB= VCC (RB2 / RB1+ RB2) ----- (2) S=1+ (RB / RE) RB= 2KΏ We know that RB= RB1|| RB2

RB= R B1RB2/ RB1+RB2--------- (3) Solving equation (2) & (3), Therefore, RB1 = 14KΏ From equation (3), RB2= 2.3KΏ (iii) To find input coupling capacitor (Ci): XCi = (hie|| RB) / 10 XCi = 113 XCi= 1/ 2пf Ci

Ci = 1 / 2пf XCi

Ci = 1/ 2X3.14X 50 X 113=28µf (iv)To find output coupling capacitor (CO): XCO= (RC || RL) / 10, (Assume RL= 10KΏ) XCO= 375 XCO= 1/ 2пf CO CO = 1/ 2x 3.14x 50 x 375=8µf =10 µf (v) To find Bypass capacitor (CE): (Without feedback) XCE = (RB+hie / 1+ hfe) || RE/ 10 XCE = 4.416 CE= 1 / 2пf XCE CE = 720 µf Design with feedback: To design with feedback remove the bypass capacitor (CE). Assume RE = 10KΏ

4.4 CIRCUIT DIAGRAM: 4.4.1 WITHOUT FEED BACK:

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Fig 4.1

4.4.2 WITH FEEDBACK:

Fig.4.2

4.5 MODEL TABULATION: 4.5.1 Without feedback:

Vi=

Sl. No Frequency Output Voltage Gain = V0/Vi Gain = 20 log(V0/Vi)

(Hz) (V0) (volts) (dB)

TAB 4.2

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4.5.2 With feedback: Vi=

Sl. No Frequency Output Voltage Gain = V0/Vi Gain = 20 log(V0/Vi)

(Hz) (V0) (volts) (dB)

TAB 4.3 4.6 MODEL GRAPH:

FIG.4.3

4.7 THEORY Negative feedback in general increases the bandwidth of the transfer function

stabilized by the specific type of feedback used in a circuit. In Voltage series feedback amplifier,

consider a common emitter stage with a resistance R’ connected from emitter to ground. This is a

case of voltage series feedback and we expect the bandwidth of the transresistance to be improved

due to the feedback through R’.The voltage source is represented by its Norton’s equivalent current

source Is=Vs/Rs.

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4.8 PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 10V; set input voltage using audio frequency oscillator.

3. By varying audio frequency oscillator take down output frequency oscillator voltage for

difference in frequency.

4. Calculate the gain in dB

5. Plot gain Vs frequency curve in semi-log sheet.

6. Repeat the steps 1 to 6 with feedback

7. Compare this response with respect to the amplifier without feedback.

4.9.INFERENCE: Thus current series feedback amplifier is designed and studied its performance.

Parameters Theoretical Practical With Feed Back Without Feed Back With Feed Back Without Feed Back

Input Impedance Output Impedance

Gain(midband) Bandwidth

4.10 VIVA QUESTIONS:

1. What is feedback?

2. what are the parameters used to design the amplifier.

3. Compare the input impedance for with and without feedback?

4. Compare the theortical and practical bandwidth for with feedback. 5. Calculate the value of output impedance with and without feed back.

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WORK SHEET

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EXPERIMENT :5

SINGLE TUNED AMPLIFIER

5.1 AIM: To design a single tuned amplifier and to draw its frequency response. 5.2 REQUIREMENTS:

TAB 5.1

5.3 DESIGN EXAMPLE:

Given specifications Vcc = 12V, β = 100, Ic = 1mA, L=1mH, f=2 KHz, S= [2-10] Assume, VCE = VCC / 2=6V VE = VCC / 10 =1.2V To calculate C:

F = 1/ 2∏ LC

Therefore C=0 .6μf To calculate RE: VE= IE RE (IC= IE) RE = VE / IE= 1.2 / 1x10-3 = 1.2K Assume S= 10, S= 1+ (RB / RE) Therefore RB= 10K To find R1 & R2: RB = R1 || R2 RB= R1 R2 / R1+ R2 ------------- (1) VB= VCC x (R2 / R1+ R2) ------ (2)

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors 2 RPS (0-30)V 1 3 Transistor BC107 1 4 Capacitors 5 CRO (0-30)MHz 1

6 Function generator (0-10)MHz 1 7 Bread board - 1

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5.4 CIRCUIT DIAGRAM:

FIG 5.1

5.5 MODAL GRAPH:

FIG 5.2

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5.6 TABULATION:

TAB 5.2

5.7 THEORY: The single tuned amplifier selecting the range of frequency the resistance load replaced by the tank circuit. Tank circuit is nothing but inductors and capacitor in parallel with each other. The tuned amplifier gives the response only at particular frequency at which the output is almost zero. The resistor R1 and R2 provide potential diving biasing, Re and Ce provide the thermal stabilization. This it fixes up the operating point. 5.8 PROCEDURE:

1. Connections are given as per the circuit diagram

2. By varying frequency, amplitude is noted down

3. Gain is calculated in dB

4. Frequency response curve is drawn.

5.9 INFERENCE: Thus the class – c single tuned amplifier is designed and frequency response is plotted.

FREQUENCY OUTPUT

VO(V)

Vin (V) Gain

20log(Vo/Vin) dB

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5.10 VIVA QUESTIONS:

1. Define Q-factor? 2. What is tuned circuit? 3. What is coil loss? 4. Give the application of Single tuned Class-C amplifier 5. What is tank circuit?

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WORK SHEET

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EXPERIMENT :6

RC PHASE SHIFT OSCILLATOR

6.1 AIM:

To design a RC phase shift oscillator and to find the frequency of oscillation

6.2 REQUIREMENTS:

S.

No

REQUIREMENTS RANGE QUANTI

TY

1 Resistors

7.5k,1.4 k 4.8K,1.2K,19K,6.5K

1each,3

2 Power supply (0-30)V 1 3 Transistor BC107 1 4 Capacitors 1.3f ,2.1f,1.3f

0.01F

1,1,3

5 CRO (0-30)MHz 1

6 Bread board - 1 TAB 6.1

6.3 Design Example: Specifications:

VCC = 12V, ICq =1mA, =100, Vceq = 5V, f=1 KHz, S=10, C=0.01 µf, hfe= 330, AV= 29

Design: (i)To find R:

Assume f=1 KHz, C=0.01µf

f=1/2∏ RC 6

R=1/2x3.14 6 x1x103x0.01x10-6=6.5KΩ Therefore R=6.5KΩ

(ii)To find RE & RC:

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VCE = VCC /2 = 6V

re= 26mV / IE= 26

hie = hfe re= 330 x 26= 8580 On applying KVL to output loop, VCC=ICRC + VCE + IERE ----- (1) VE = IE RE

RE = VE / IE =1.2/ 10-3 =1.2K From equation (1), 12= 10-3(RC+ 1200) +6= RC= 4800=4.8K (iii)To calculate R1 & R2:

VBB= VCC R2 / R1+ R2 ------ (2) VB= VBE +VE = 0.7+12 =1.9V From equation (2), 1.9= 12 R2 / R1+ R2 R2 / R1+ R2= 0.158 -------- (3) S = 1+ RB / RE= RB = 1.2K RB =R1 || R2 0.15R1= 1.2x10-3=7.5K R2 =0.158 R1 + 0.158 R2, R2= 1.425K (iv)To calculate Coupling capacitors:

(i) XCi= [hie + (1+hfe) RE] || RB / 10 = 0.12K XCi= 1 / 2∏ f Ci == 1.3f (ii) XCO= RLeff / 10 [ AV = - hfe RLeff / hie]

RLeff = 0.74K, XCO=0.075 K XCO= 1 / 2∏ f CO , CO = 2.1f (iii) XCE= RE / 10 = 1.326 f XCE = 1 / 2∏ f CE=49.27f (iv) Feed back capacitor, XCF = Rf / 10 Cf = 0.636f = 0.01f

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6.4 CIRCUIT DIAGRAM:

FIG 6.1

6.5 MODEL GRAPH:

FIG.6.2

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6.6 TABULATION:

Time Period (ms) Frequency(Hz) Amplitude

Tab 6.2 6.7 THEORY:

The low frequencies RC oscillators are more suitable. Tuned circuit is not an essential requirement for oscillation. The essential requirement is that there must be a 180o phase shift around the feedback network and loop gain should be greater than unity. The 180o phase shift in feedback signal can be achieved by suitable RC network. 6.8 PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 15V.

3. For the given supply the amplitude and time period is measured from

CRO.

4. Frequency of oscillation is calculated by the formula f=1/T

5. Amplitude Vs time graph is drawn.

6.9 INFERENCE:

Thus the RC-phase shift oscillator is designed and constructed for the given

frequency. Theoretical frequency : Practical frequency :

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6.10 VIVA QUESTIONS: 1. What is an oscillator? 2. What is barkhausen criterion for oscillation? 3. Which feedback is used in oscillators? 4. Give the frequency of oscillation for RC-phase shift oscillator? 5. Give the disadvantages of phase shift oscillator.

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WORK SHEET

41

EXPERIMENT :7

HARTLEY OSCILLATOR 7.1 AIM: To design and construct a Hartley oscillator at the given operating frequency

7.2 REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors 2 RPS (0-30)V 1

3 Transistor BC107 1 4 Capacitors 5 Inductor 10mH 2 6 CRO 30MHz 1 7 Bread board - 1

TAB 7.1

7.3Design Example:

Design of feed back Network: Given L1= L2=10mH, f=20 KHz, VCC=12V, IC=3mA, S=12

f = 1/2∏ CLL )21(

C= 3.2nf Amplifier design:

(i) Selection of RC: Gain formula is,

AV= - hfe RLeff / hie Assume VCE=VCC/2 (Transistor active)

VCE= 12/2= 6V VE=IERE= VCC/10=1.2V VCC=ICRC + VCE + IERE

RC= (VCC- VCE -IERE) / IC

Therefore RC = 1.6K=2 K (ii) Selection of RE:

IC= IE=3mA RE= VE/IE

RE= 1.2 / 3x10-3=400 =1K (iii) Selection of R1 & R2:

Stability factor S=12 S=1+ (RB/ RE) 12=1+ (RB/1x103) RB=11K Using potential divider rule,

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RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC RB /R1= R2/ R1+R2

Therefore RB/R1= VB/VCC VB=VBE+ VE= 0.7+1.2=1.9V=2V R1= (VCC/ VB )RB R1= (12/2)x 11x103=66K=100K VB/VCC =R2 / R1+R2 2/ 12=R2 / 100x103+R2 (100x103)+R2=R2/0.16=19K R2=19K=22 K (iv)Output capacitance (CO): XCO=RC/10=2x103/10=200

1/2∏fCO=200 CO=1/2x3.14x20x103x200 CO=0.039=0.01µf (v) Input capacitance (Ci): XCin= RB/10=11x103/10=1.1x103

1/2∏fCin=1.1x103 Cin=1/2x3.14x20x103x1.1x103 Cin= 0.007=0.01µf (vi) By pass Capacitance (CE): XCE=RE/10=1x103/10=100

1/2∏fCE=100 CE= 1/2x3.14x20x103x100

CE = 0.079µf = 0.1µf

7.4 THEORY: Hartley oscillator is very popular and is commonly used as local oscillator in radio receivers. The collector voltage is applied to the collector through inductor L whose reactance is high compared with X2 and may therefore be omitted from equivalent circuit, at zero frequency, however capacitor Cb acts as an open circuit. 7.5 PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 12V.

3. For the given supply the amplitude and time period is measured from CRO.

4. Frequency of oscillation is calculated by the formula f=1/T

5. Verify it with theoretical frequency, f= 1/2∏ ( CLL )21( ) Amplitude Vs time graph is

drawn.

43

7.6 CIRCUIT DIAGRAM:

FIG 7.1 7.7 MODEL GRAPH:

FIG 7.2

7.8 MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

1.5 40 25

TAB.7.2 7.9 INFERENCE: Thus the Hartley oscillator is designed and constructed for the given frequency. Theoretical frequency : Practical frequency :

44

7.10 VIVA QUESTIONS: 1. How does an oscillator differ from an amplifier?

2. What is the approximate value of hfe in a Hartley oscillator using BJT?

3. Mention the expression for frequency of oscillation?

4. Mention the reasons why LC oscillator is preferred over RC oscillator at radio frequency?

5. How the Hartley oscillator satisfy the barkhausen criterion

45

WORK SHEET

46

EXPERIMENT :8

COLPITT’S OSCILLTOR 8.1 AIM:

To design and construct a Colpitt’s oscillator at the given operating frequency.

8.2 REQUIREMENTS:

S.No EQUIPMEN

TS

RANGE QUANTITY

1 Resistors 2 RPS (0-30)V 1

3 Transistor BC107 1

4 Capacitors

5 Inductor 10mH 1

6 CRO 30MHz 1

7 Bread board - 1

TAB 8.1 8.3 Design of feed back Network:

Given C1= 0.1 F, L=10mH, f=20 KHz, VCC=12V,IC=3mA, S=12

f = 1/2∏21

21

CLC

CC , C2= 0.01F

Amplifier design:

(i)Selection of RC: Gain formula is,

AV= - hfe RLeff / hie Assume VCE=VCC/2 (Transistor active)

VCE= 12/2= 6V VE=IERE= VCC/10=1.2V VCC=ICRC + VCE + IERE

RC= (VCC- VCE -IERE) / IC

Therefore RC= 1.6K=2 K (ii) Selection of RE:

IC= IE=3mA RE= VE/IE= 1K

(iii) Selection of R1 & R2: Stability factor S=12 S=1+(RB/ RE) 12=1+ (RB/1x103)=11k Using potential divider rule, RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC

47

RB /R1= R2/ R1+R2

Therefore RB/R1= VB/VCC VB=VBE+ VE= 0.7+1.2=1.9V=2V R1= (VCC/ VB ) RB=66K=100K VB/VCC =R2 / R1+R2 2/ 12=R2 / 100x103+R2 R2=19K=22 K (iv) Output capacitance (CO): XCO=RC/10=2x103/10=200

1/2∏fCO=200 CO=1/2x3.14x20x103x200=0.039=0.01µf (v) Input capacitance (Ci): XCin= RB/10=11x103/10=1.1x103

1/2∏fCin=1.1x103 Cin=1/2x3.14x20x103x1.1x103=0.0101µf (vi) By pass Capacitance (CE): XCE=RE/10=1x103/10=100

1/2∏fCE=100 CE= 1/2x3.14x20x103x100=0.079µf = 0.1µf 8.4 THEORY: Colpitt’s oscillator is very popular and is commonly used as local oscillator in radio receivers. The collector voltage is applied to the collector through inductor L whose reactance is high compared with X2 and may therefore be omitted from equivalent circuit, at zero frequency; The circuit operates as Class C. the tuned circuit determines basically the frequency of oscillation. 8.5 PROCEDURE:

1. Connect the circuit as per the circuit diagram. 2. Set VCC = 12V. 3. For the given supply the amplitude and time period is measured from CRO. 4. Frequency of oscillation is calculated by the formula f=1/T

5 .Amplitude Vs time graph is drawn.

48

8.6 CIRCUIT DIAGRAM:

FIG 8.1

8.7 MODEL GRAPH:

FIG 8.2

8.8 MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

TAB.8.2 8.9 INFERENCE: Thus the Collipit’s oscillator is designed and constructed for the given frequency. Theoretical frequency : Practical frequency :

49

8.10 VIVA QUESTIONS:

1. What is the approximate value of hfe in a colpitt’s oscillator using BJT for

sustained oscillation?

2. What is Tank circuit?

3. Mention the expression for frequency of oscillation?

4. What are the essential parts of an oscillator?

5. Name two high frequency oscillators?

50

WORK SHEET

51

EXPERIMENT :9

WEIN- BRIDGE OSCILLATOR

9.1 AIM:

To design a Wein-bridge oscillator using transistors and to find the frequency of oscillation. 9.2 REQUIREMENTS:

S.No REQUIREMENTS RANGE QUANTITY

1 Resistors

2 Power supply 5V 1 3 Transistor BC107 1 4 Capacitors 5 CRO 1

6 Bread board 1 TAB 9.1

9.3 DESIGN EXAMPLE: Assume f=1 KHz, C=0.1µf f = 1/ 2∏RC

R= 1/2∏fC R =1/2x3.14x1x103x0.1x103

R= 1.59KΩ To calculate R1: R1= 10R R1 =10x1.5K R1 =15.9KΩ

To calculate Rf (Feed back resistor):

Rf = 2R1

Rf = 2(15.9x103)=31.8KΩ ≈ 33KΩ 9.4 THEORY:

Generally in an oscillator, amplifier stage introduces 180o phase shift and feedback

network introduces additional 180o phase shift, to obtain a phase shift of 360o around a loop. This is a condition for any oscillator. But Wein bridge oscillator uses a non-inverting amplifier and hence does not provide any phase shift during amplifier stage. As total phase shift requires is 0o or 2n radians, in Wein bridge type no phase shift is necessary through feedback. Thus the total phase shift around a loop is 0o. The output of the amplifier is applied between the terminals 1 and 3, which are the input to the feedback network. While the amplifier input is supplied from the diagonal terminals 2 and 4, which is the output from the feedback network. Thus amplifier supplied its own output through the Wein bridge as a feed back network.

52

The two arms of the bridge, namely R1, C1 in series and R2, C2 in parallel are called frequency sensitive arms. This is because the components of these two arms decide the frequency of the oscillator. Advantage of Wein bridge oscillator is that by varying the two-capacitor values simultaneously, by mounting them on the common shaft, different frequency ranges can be provided. 9.5 PROCEDURE:

1. Connect the circuit as per the circuit diagram. 2. Set VCC = 5V. 3. For the given supply the amplitude and time period is measured from CRO. 4. Frequency of oscillation is calculated by the formula f=1/T 5. Amplitude Vs time graph is drawn.

9.6 CIRCUIT DIAGRAM

FIG 9.1

53

9.7 MODEL GRAPH:

FIG 9.2

9.8 MODEL TABULATION:

Amplitude (V) Time(μs) Frequency (Hz)

TAB.9.2

9.9 INFERENCE:

Thus the Wein – bridge oscillator is designed for the given frequency of oscillation. Theoretical frequency : Practical frequency :

9.10 VIVA QUESTIONS:

1. Give the condition for maximum oscillation.

2. What is the frequency of oscillation under balanced condition?

3. In which way high gain is obtained in wein bridge oscillator.

4. How to improve the amplitude stability of output waveform.

5. What is the frequency of oscillation?

54

WORK SHEET

55

EXPERIMENT :10

EMITTER COUPLED ASTABLE MULTIVIBRATOR

10.1 AIM: To design an Emitter coupled Astable multivibrator and study the output waveform.

10.2 REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors

2 RPS (0-30)V 1 3 Transistor BC107 2 4 Capacitors

5 CRO (0-30)MHz 1

6 Bread board - 1

TAB 10.1 10.3 DESIGN EXAMPLE: Given specifications: VCC= 10V; hfe = 100; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v; To design RC:

R ≤ hFE RC

RC= VCC- VC2 (Sat) / IC= 4.9 k

Since R ≤ hFE RC

Therefore R≤ 100 x 4.7 x103=490 k 470 k To Design C: Since T= 1.38RC 1x10-3=1.38x 490x103x C Therefore C=0.01F 10.4. THEORY: The astable multivibrator generates square wave without any external triggering pulse. It has no stable state, i.e., it has two quasi- Stable states. It switches back and forth from one stable state to other,remaining in each state for a time depending upon the discharging of a capacitive circuit.When supply voltage + Vcc is applied, one transistor will Conduct more than the other due to some circuit imbalance.

56

10.5 PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Set VCC = 5V. 3. For the given supply the amplitude and time period is measured from CRO. 4. Frequency of oscillation is calculated by the formula f=1/T 5. Amplitude Vs time graph is drawn.

10.6 CIRCUIT DIAGRAM

FIG 10.1

57

10.7 MODEL GRAPH:

FIG.8.2 10.8 TABULATION:

TAB 10.2

10.9 INFERENCE: Thus the astable multivibrator is designed and output waveform is plotted

Amplitude(V) Time

period(msec)

58

10.10 VIVA QUESTIONS:

1. What is meant by multivibrator?

2. What is the frequency of oscillation of astable multivibrator?

3. Distinguish oscillator and multivibrator?

4. List the applications of astable multivibrator.

5. Why it is called as free running multivibrator. .

59

EXPERIMENT :11

MONOSTABLE MULTIVIBRATOR

11.1 AIM: To design and test the performance of Monostable multivibrator for the given frequency 11.2 REQUIREMENTS:

S.No

EQUIPMENTS

RANGE QUANTITY

1 Resistors

2 RPS (0-30)V 1

3 Transistor BC107 1

4 CRO (0-30)MHz 1

5 Capacitor 3.2nf 25pf

1 1

6 Bread board - 1

TAB 11.1 11.3 DESIGN EXAMPLE: Given specifications: VCC= 12V; hfe = 200; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v; VBB= - 2V, (i)To calculate RC: RC = VCC - Vce (sat) / IC RC = 12 – 0.2 / 2x10-3=5.9KΩ (ii) To calculate R:

IB2(min)=IC2 / hfe= 2x10-3 / 200 = 10µ A Select IB2 > IB1(min) (say 25µ A) Then R = VCC – V BE (sat) / IB2 Therefore R= 12-0.7/25x10-6=452KΩ (iii) To calculate C:

T=0.69RC 1x10-3= 0.69x452x103xC C=3.2nf To calculate R1 & R2: VB1= (VBB R1/ R1 +R2) + (VCE (sat) R2 / R1+R2) Since Q1 is in off state ,VB1 ≤ 0 Then (VBB R1/ R1 +R2) = (VCE (sat) R2 / R1+R2) VBB R1 = VCE (sat) R2 2 R1 = 0.2 R2 Assume R1=10KΩ, then R2=100 KΩ Consider, C1= 25pf (commutative capacitor)

60

11.4 THEORY: The monostable multivibrator has one stable state when an external trigger input is applied the circuit changes its state from stable quasi stable state. And then automatically after some time interval the circuit returns back to the original normal stable state. The time T is dependent on circuit components. The capacitor C1 is a speed-up capacitor coupled to base of Q2 through C.Thus DC coupling in bistable multivibrator is replaced by a capacitor coupling. The resistor R at input of Q2 is returned to VCC. The value of R2 , V BB are chosen such that transistor Q1 is off by reverse biasing it. Q2 is on. This is possible by forward biasing Q2 with the help of VCC and resistance R. Thus Q2-ON and Q1-OFF is normal stable state of circuit. 11.5 PROCEDURE:

1. Connect the circuit as per the circuit diagram. 2. Give a negative trigger input to Q2.

3. Note the output of transistor Q2 and Q1. 4. Find the value of Ton and Toff.

11.6 CIRCUIT DIAGRAM:

FIG 11.1

61

11.7 MODEL GRAPH:

FIG.11.2

11.8 TABULATION:

TAB 11.2 11.9 INFERENCE: Thus the monostable multivibrator is designed and the performance is tested. Theoretical period : Practical period :

Amplitude(V) Time period(msec)

TON TOFF

62

11.10 VIVA QUESTIONS:

1. Give the other names of monostable multivibrator? 2. What is the use of commutating capacitor? 3. What is the frequency of oscillation of monostable multivibrator? 4. Why it is called as one-shot multivibrator? 5. List the applications of mono stable multivibrator.

63

WORK SHEET

64

EXPERIMENT :12

BISTABLE MULTIVIBRATOR 12.1 AIM: To design a bi-stable multivibrator and study the output waveform. 12.2 REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors

2 RPS (0-30)V 1

3 Transistor BC107 1

4 CRO (0-30)MHz 1

5 Capacitor 50pf 2 6 Bread board - 1

TAB 12. 12.3 Design Example: Given specifications: VCC =12V,VBB = - 12V, IC= 2mA , VC(Sat) = 0.2V, VBE(Sat)= 0.7V, hfe=200 Assume Q1 is cut off, i.e. VC1= VCC (+12V) Q2 is saturation (ON), i.e.VC2= VC (Sat) (0.2V) Using superposition principle, VB1 = [VBB ( R1/ R1+R2) + VC2(R2 / R1+R2)] << 0.7 Consider VB1= -1V -1= (-12R1 / R1+ R2) + (0.2 R2 / R1+R2) -------- (1) To calculate RC: IC = VCC – VC2 / RC RC = VCC – VC2 / IC = 12-0.2 / 2x10-3 = 5.9K To calculate R1 & R2:

Assume, R1 = 10K By using inequality, R1 < hfe RC R2= 91.67k= 100k [Using equation (1)] Since IB2 > IB2(min) , Q2 is ON Choose Capacitor C1= 25pf (commutative capacitor) 12.4 THEORY

The bistable multivibrator has two stable states. The multivibrator can exist indefinitely in either of the twostable states. It requires an external trigger pulse to change from one stable state to another. The circuit remains in one stable state until an external trigger pulse is applied. The bistable multivibrator is used for the performance of many digital operations such as counting and storing of binary information. The multivibrator also finds an applications in generation and pulse type waveform.

65

12.5 PROCEDURE: 1. Connect the circuit as per the circuit diagram 2. Switch on the regulated power supply and observe the output waveform at the collector of Q1 and Q2. 3. Sketch the waveform. 4. Apply a threshold voltage of VT (pulse voltage) and observe the changes of states of Q1 and Q2 5. Sketch the waveform

12.6 CIRCUIT DIAGRAM:

FIG 12.1 12.7 TABULATION:

TAB 12.2

Amplitude(V) Time period(msec)

TON TOFF

66

12.8 MODEL GRAPH:

FIG.10.2 12.9 INFERENCE:

Thus the bistable multivibrator is designed and the performance is tested.

67

12.10 VIVA QUESTIONS:

1. Define storage time of bistable multivibrator?

2. What are the different types of triggering of bistable multivibrator?

3. List the application of bistable multivibrator.

4. What is the use of triggering in bistable multivibrators?

5. Give the differences between three multivibrators.

68

WORK SHEET

69

EXPERIMENT :13

ASTABLE BLOCKING OSCILLATOR WITH BASE TIMING(DIODE CONTROLLED)

12.1 AIM:

To design an astable blocking oscillator with base timing(diode controlled) . 12.2 REQUIREMENTS:

S.No EQUIPMENTS RANGE QUANTITY

1 Resistors

2 RPS (0-30)V 1

3 Transistor BC107 1

4 CRO (0-30)MHz 1

5 Capacitor 50pf 2 6 Bread board - 1

TAB 12. 12.3 Design Example: Given specifications: L=5.2mH,C=90pF,Vcc=10V,R=500Ω,Vγ=6v,VBB=0.5,n=1 Since VBB<<VCC

sR

nLt p 4.10

500

105.2 -3

To calculate tf:

stV

Vcc

R

L

n

nt pf

7.86

10

2

1

1

2

157.1 CLta 1.1µs

To Calculate Period T: T=tf + ta +tp

To Duty Cycle :

70

12.4 THEORY The bistable multivibrator has two stable states. The multivibrator can exist indefinitely in

either of the twostable states. It requires an external trigger pulse to change from one stable state to another. The circuit remains in one stable state until an external trigger pulse is applied. The bistable multivibrator is used for the performance of many digital operations such as counting and storing of binary information. The multivibrator also finds an applications in generation and pulse type waveform. 12.5 PROCEDURE: 1. Connect the circuit as per the circuit diagram 2. Switch on the regulated power supply and observe the output waveform at the collector of Q1 and Q2. 3. Sketch the waveform. 4. Apply a threshold voltage of VT (pulse voltage) and observe the changes of states of Q1 and Q2 5. Sketch the waveform

12.6 CIRCUIT DIAGRAM:

FIG 12.1

12.7 TABULATION:

TAB 12.2

Amplitude(V) Time period(msec)

TON TOFF

71

12.8 MODEL GRAPH:

FIG.10.2 12.9 INFERENCE:

Thus the bistable multivibrator is designed and the performance is tested.

72

12.10 VIVA QUESTIONS:

1. Define storage time of bistable multivibrator?

2. What are the different types of triggering of bistable multivibrator?

3. List the application of bistable multivibrator.

4. What is the use of triggering in bistable multivibrators?

5. Give the differences between three multivibrators.

73

SIMULATION USING PSPICE

74

EXPERIMENT :1 TUNED COLLECTOR OSCILLATOR

1.1 AIM: To simulate a tuned collector oscillator using PSPICE 1.2REQUIREMENTS: 1. PC 2. PSPICE software 1.3 THEORY: Tuned collector oscillation is a type of transistor LC oscillator where the tuned circuit (tank) consists of a transformer and a capacitor is connected in the collector circuit of the transistor. Tuned collector oscillator is of course the simplest and the basic type of LC oscillators. The tuned circuit connected at the collector circuit behaves like a purely resistive load at resonance and determines the oscillator frequency. The common applications of tuned collector oscillator are RF oscillator circuits, mixers, frequency demodulators, signal generators etc

1.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms 1.5 CIRCUIT DIAGRAM:

FIG.1.1

`

75

1.6 MODEL GRAPH:

FIG.1.2

1.7 INFERENCE:

Thus the tuned collector oscillator is simulated using PSpice.

76

1.8 VIVA QUESTIONS:

1. What is PSpice? 2. What is the use of Pspice? 3. What are the different types of analysis done using Spice? 4. List the limitation of Pspice 5. What are the different output commands?

77

EXPERIMENT :2

MONO STABLE MULTIVIBRATOR

2.1 AIM: To simulate an monostable multivibrator using PSPICE

2.2 REQUIREMENTS:

1. PC 2. PSPICE software 2.3 THEORY: Monostable multivibrator is an electronic circuit which has one stable state and one quasi stable state. It needs external pulse to change their stable state to quasi state and return back to its stable state after completing the time constant RC. Thus the RC time constant determines the duration of quasi state. Also called as one-shot, single shot and one swing multivibrator.Used as triggering circuit for some circuits like timer circuit, delay circuits etc.

2.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms

78

2.5 CIRCUIT DIAGRAM:

FIG.2.1 2.6 MODEL GRAPH:

FIG.2.2

79

2.5 INFERENCE:

Thus the monostable multivibrator is simulated using PSpice .

2.6 VIVA QUESTIONS:

1. Give the other names of monostable multivibrator? 2. What is the use of commutating capacitor? 3. What is the frequency of oscillation of monostable multivibrator? 4. Why it is called as one-shot multivibrator? 5. List the applications of mono stable multivibrator.

80

EXPERIMENT :3

BI-STABLE MULTIVIBRATOR

3.1 AIM: To simulate an Bi-stable multivibrator using PSPICE

3.2 REQUIREMENTS:

1. PC 2. PSPICE software 3.3 THEORY: Bi- stable multivibrator contains two stable states and no quasi states. It requires two clock or trigger pulses to change the states. It is also called as flip flop, scale of two toggle circuit, trigger circuit. It is used in digital operations like counting, storing data’s in flip flops and production of square waveforms. 3.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms 3.5 CIRCUIT DIAGRAM:

FIG 3.1

81

3.6 MODEL GRAPH:

FIG.3.2

3.5 INFERENCE:

Thus the Bi-stable multivibrator is simulated using PSpice.

82

3.6 VIVA QUESTIONS:

1. Define storage time of bistable multivibrator? 2. What are the different types of triggering of bistable multivibrator? 3. List the application of bistable multivibrator. 4. What is the use of triggering in bistable multivibrators? 5. Give the differences between three multivibrators.

83

EXPERIMENT :4

DOUBLE AND STAGGERED TUNED AMPLIFIER 4.1 AIM: To simulate double and staggered tuned amplifiers

4.2 REQUIREMENTS:

1. PC 2. PSPICE software 4.3 THEORY:

A double-tuned amplifier is a tuned amplifier with transformer coupling between the amplifier

stages in which the inductances of both the primary and secondary windings are tuned separately

with a capacitor across each. The scheme results in a wider bandwidth than a single tuned

circuit would achieve. There is a critical value of transformer coupling coefficient at which

the frequency response of the amplifier is maximally flat in the pass band and the gain is maximum

at the resonant frequency. Designs frequently use a coupling greater than this (over-coupling) in

order to achieve an even wider bandwidth at the expense of a small loss of gain in the centre of the

pass band. Staggered tuning is a technique used in the design of multi-stage tuned

amplifiers whereby each stage is tuned to a slightly different frequency. In comparison

to synchronous tuning (where each stage is tuned identically) it produces a wider bandwidth at the

expense of reduced gain. It also produces a sharper transition from the passband to the stopband.

Both staggered tuning and synchronous tuning circuits are easier to tune and manufacture than

many other filter types.The function of stagger-tuned circuits can be expressed as a rational

function and hence they can be designed to any of the major filter responses such

as Butterworth and Chebyshev. The poles of the circuit are easy to manipulate to achieve the

desired response because of the amplifier buffering between stages.

4.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms 4.5 CIRCUIT DIAGRAM:

DOUBLE TUNNED AMPLIFIER

84

FIG 3.1

4.6 MODEL GRAPH:

DOUBLE TUNNED AMPLIFIER

FIG.3.2

4.7 INFERENCE:

Thus the double and staggered tuned amplifier is simulated using PSpice.

85

EXPERIMENT :5

Schmitt Trigger circuit with Predictable hysteresis

5.1 AIM: To simulate Schmitt Trigger circuit with Predictable hysteresis

5.2 REQUIREMENTS:

1. PC 2. PSPICE software 5.3 THEORY:

A Schmitt trigger is a comparator circuit with hysteresis, implemented by applying positive

feedback to the input of an amplifier. It is an active circuit which converts an analog input signal to

a digital output signal. The circuit is named a "trigger" because the output retains its value until the

input changes sufficiently to trigger a change. In the non-inverting configuration, when the input is

higher than a certain chosen threshold, the output is high. When the input is below a different

(lower) chosen threshold, the output is low, and when the input is between the two levels, the output

retains its value. This dual threshold action is called hysteresis and implies that the Schmitt trigger

possesses memory and can act as a bistable circuit (latch or flip-flop). There is a close relation

between the two kinds of circuits: a Schmitt trigger can be converted into a latch and a latch can be

converted into a Schmitt trigger.

Schmitt trigger devices are typically used in signal conditioning applications to remove noise from

signals used in digital circuits, particularly mechanical switch bounce. They are also used in closed

loop negative feedback configurations to implement relaxation oscillators, used in function

generators and switching power supplies.

5.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms

86

5.5 CIRCUIT DIAGRAM:

5.6 MODEL GRAPH:

5.7 INFERENCE:

Thus the Schmitt trigger is simulated using PSpice

87

EXPERIMENT :6

VOLTAGE AND CURRENT TIME BASE CIRCUITS

6.1 AIM: To simulate voltage and current time base circuits by using PSPICE

6.2 REQUIREMENTS:

1. PC 2. PSPICE software 6.3 THEORY:

A time base generator, or timebase, is a special type of function generator, an electronic circuit

that generates a varying voltage to produce a particular waveform. Time base generators produce

very high frequency sawtooth waves specifically designed to deflect the beam in cathode ray

tube (CRT) smoothly across the face of the tube and then return it to its starting position.

Time bases are used by radar systems to determine range to a target, by comparing the current

location along the time base to the time of arrival of radio echoes. Analog television systems using

CRTs had two time bases, one for deflecting the beam horizontally in a rapid movement, and

another pulling it down the screen 60 times per second.Oscilloscopes often have several time bases,

but these may be more flexible function generators able to produce many waveforms as well as a

simple time base.

6.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms 6.5 CIRCUIT DIAGRAM:

VOLTAGE TIME BASE CIRCUIT

88

CURRENT TIME BASE CIRCUIT

6.6 MODEL GRAPH:

CURRENT TIME BASE CRCUIT

6.7 INFERENCE:

Thus the Voltage and Current time base circuits are simulated using PSpice

89

EXPERIMENT :7

WEIN BRIGE OSCILLATOR

7.1 AIM: To simulate voltage and current time base circuits by using PSPICE

7.2 REQUIREMENTS:

1. PC 2. PSPICE software 7.3 THEORY:

Generally in an oscillator, amplifier stage introduces 180o phase shift and feedback

network introduces additional 180o phase shift, to obtain a phase shift of 360o around a loop. This is a condition for any oscillator. But Wein bridge oscillator uses a non-inverting amplifier and hence does not provide any phase shift during amplifier stage. As total phase shift requires is 0o or 2n radians, in Wein bridge type no phase shift is necessary through feedback. Thus the total phase shift around a loop is 0o. The output of the amplifier is applied between the terminals 1 and 3, which are the input to the feedback network. While the amplifier input is supplied from the diagonal terminals 2 and 4, which is the output from the feedback network. Thus amplifier supplied its own output through the Wein bridge as a feed back network.

7.4 PROCEDURE: 1. Click on the start menu and select the pspice simulation software 2. Select the parts required for the circuit from the parts menu and place them in the work space 3. Connect the parts using wires 4. Save the file and select the appropriate analysis 5. Simulate the circuit and observe the corresponding output waveforms 7.5 CIRCUIT DIAGRAM:

90

7.6 MODEL GRAPH:

5.7 INFERENCE:

Thus the Wein Bridge Oscillator is simulated using PSpice

91

ADDITIONAL EXPERIMENTS

92

EXPERIMENT: 1

CRYSTAL TESTER

1.1AIM : To design a Crystal tester circuit using BC107

1.2REQUIREMENTS:

S.No EQUIPMENTS Quantity 1 BC107 B Transistor 2 2 Diodes 1N4148 75V 150mA 2 3 Resistors:27K Ω,1K Ω,560Ω 1 4 Capacitor :0.1uF,330pF ,0.0047uF 2

5 LED1 1 TAB 1.1

1.3 CIRCUIT DIAGRAM:

FIG 1.2 1.4 WORKING PRINCIPLE:

The transistor Q1 (BC107) is the key to the oscillated circuit. By will create frequency,

when the crystal put on socket to the base pin (B) of Q1.When the switch S1 is pressed to the

circuit, the current from the battery (B1-9 volt) to flow into circuit, the oscillated signal from

emitter pin (E) of Q1 pass through to C4.The oscillator signal will be changing all the time, need to

smooth with D1 and D2. Then, the signal is passed to the C5, which helps smooth up. At C5 has

voltage across it, is a positive voltage to trigger a bias current to the Q2 works, as a INFERENCE

the LED1 lights. The R3 limits the current through the LED1 to a value not exceeding 20 mA. If

93

more than this, LED lights too, and short lived to LED1.The above principle see that LED1 is

illuminated when the transistor Q1 works.

1.5 INFERENCE:

Thus a crystal tester is implemented using operational amplifier.

94

EXPERIMENT: 2

SIMPLE BURGLAR ALARM CIRCUIT

2.1 AIM :

To design a Simple Burglar Alarm Circuit using BC107

2.2 REQUIREMENTS:

S.No EQUIPMENTS Quantity 1 BC107 B Transistor 2 2 SCR TYN612 1 3 Resistors: 1K Ω 1 POT 250K Ω 1 4 SPST Switch 1

5 Window Foil 1 6 12 V car Horn 1

TAB 2.1

2.3 CIRCUIT DIAGRAM:

FIG 2.1

95

2.4 WORKING PRINCIPLE:

The circuit uses a fine wire element fixed as a network through the window glass for

sensing the break through . Normally the base of Q1 is held to ground potential by the wire

element.So Q1 will be off and SCR H1 will not be conducting, and horn will be off. When the wire

element is broken the base of Q1 will be raised to positive potential, Q1 will be on and so SCR H1

(TYN 612) will be ON making the horn to blow and this condition will be latched by the SCR. The

circuit remains ON until the normal condition is restored or the power supply is switched OFF.

To make the window foil make a loop of very fine wire through the window glass ( two or

three lines running in both direction is enough).See figure. Connect the two free ends of the

wires to point A & B as shown in circuit diagram.

To setup the circuit , make S1 open and adjust R2 to get a 1V between base of Q1 and

ground.(0.7 V is enough to ON Q1).Now transistor will be ON and horn will be blowing.

Now ,close S1 and reset the power supply .The transistor Q1 will be off and horn will not

be blowing. The circuit is ready.

FIG 2.2

2.5 INFERENCE:

Thus a simple burglar alarm circuit is implemented using operational amplifier.

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EXPERIMENT: 3 ONE TRANSISTOR CODE LOCK

3.1 AIM : To design a One transistor code lock Circuit using BC107

3.2REQUIREMENTS:

S.No EQUIPMENTS Quantity 1 BC107 B Transistor 1 2 IN4007 5 3 Resistors: 2.2K Ω,100K Ω 1 POT 250K Ω 1 4 SPST Switch 1

5 Window Foil 1 6 12 V car Horn 1 7 Auto Transformer 1 8. Capacitor 100µF,15V 1 9. SPDT Relay 6V,200 Ω 1 10 Switchs 10

TAB 3.1

3.3 CIRCUIT DIAGRAM:

FIG 3.1

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3.4 WORKING PRINCIPLE:

The circuit is nothing but a simple transistor switch with a relay at its collector as load. Five

switches (S0 to S4) arranged in series with the current limiting resistor R2 is connected across the

base of the transistor and positive supply rail. Another five switches (S5 to S9) arranged in parallel

is connected across the base of the transistor and ground. The transistor Q1 will be ON and relay

will be activated only if all the switches S0 to S4 are ON and S5 to S9 are OFF. Arrange these

switches in a shuffled manner on the panel and that it. The relay will be ON only if the switches S0

to S9 are either OFF or ON in the correct combination. The device to be controlled using the lock

circuit can be connected through the relay terminals. Transformer T1, bridge D1, capacitor C1

forms the power supply section of the circuit. Diode D2 is a freewheeling diode. Resistor R1

ensures that the transistor Q1 is OFF when there is no connection between its base and positive

supply rail.

Notes.

This circuit can be assembled on a Vero board.

Switch S1 is the lock’s power switch.

The no of switches can be increased to make it hard to guess the combination.

Transistor 2N2222 is not very critical here. Any low or medium power NPN transistor

will do the job.

3.5 INFERENCE:

Thus a one transistor code lock circuit is implemented using operational amplifier

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APPENDIX

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NPN general purpose transistors BC107; BC108; BC109

FEATURES Low current (max. 100 mA) Low voltage (max. 45 V).

APPLICATIONS General purpose switching and amplification.

DESCRIPTION NPN transistor in a TO-18; SOT18 metal package. PNP complement: BC177.

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QUICK REFERENCE DATA

101