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Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Principles OfPrinciples Of
Digital DesignDigital DesignDiscussion 5: Combinatorial RTL Discussion 5: Combinatorial RTL
ComponentsComponents
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 2
Problem 1: delay in adder/Problem 1: delay in adder/subtractorsubtractor
� For a 8-bit carry-ripple Adder/Subtractor, what is the delay to add or subtract two numbers ?
� Determine the shortest possible time considering different implementation of the Adder/Subtractor with the libraries given in Logic Gates lecture.
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 3
TwoTwo’’s Complement Adder/s Complement Adder/SubtractorSubtractor
Truth Table
8-bit Adder/Subtractor Unit Schematic
� Two’s complement subtraction
A – B = A + B′ + 1
� Subtraction Procedure� Complement B
� Set input carry to 1
� Add to A
S Function Comment
0 A + B Addition
1 A + B′ + 1 Subtraction
A B
F
Graphic Symbol
cout
S
cout
S
a0 b0a1 b1a2 b2a3 b3a4 b4a5 b5a6 b6a7 b7
f0f1f2f3f4f5f6f7
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 4
TwoTwo’’s Complement Adder/s Complement Adder/SubtractorSubtractor
8-bit Adder/Subtractor Unit Schematic
cout
S
a0 b0a1 b1a2 b2a3 b3a4 b4a5 b5a6 b6a7 b7
f0f1f2f3f4f5f6f7
� To calculate delay, find the critical path ! (longest path from input to output)
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 5
TwoTwo’’s Complement Adder/s Complement Adder/SubtractorSubtractor
8-bit Adder/Subtractor Unit Schematic
cout
S
a0 b0a1 b1a2 b2a3 b3a4 b4a5 b5a6 b6a7 b7
f0f1f2f3f4f5f6f7
xxii yyii
ccii
si
ccii + 1+ 1
4.2
2.42.4
2.4 4.2
Input/OutputPath
Delay(ns)
ci to ci + 1 4.8 ns
ci to si 4.2 ns
xi, yi to ci + 1 9.0 ns
xi, yi to si 8.4 ns
Full–adder delays
Consider the implementation of FA
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 6
TwoTwo’’s Complement Adder/s Complement Adder/SubtractorSubtractor
8-bit Adder/Subtractor Unit Schematic
cout
S
a0 b0a1 b1a2 b2a3 b3a4 b4a5 b5a6 b6a7 b7
f0f1f2f3f4f5f6f7
� Red: 8 * (delay of ci to ci + 1)
� Green: 7 * (delay of ci to ci + 1) + (delay of xi, yi
to ci + 1)+(delay of XOR)
� Yellow: 6 * (delay of ci to ci + 1) + (delay of xi, yi
to ci + 1)+(delay of XOR) + (delay of ci to si)
Input/OutputPath
Delay(ns)
ci to ci + 1 4.8 ns
ci to si 4.2 ns
xi, yi to ci + 1 9.0 ns
xi, yi to si 8.4 ns
Full–adder delays
xxii yyii
ccii
si
ccii + 1+ 1
4.2
2.42.4
2.4 4.2
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 7
FullFull--adder Design Using XOR Gatesadder Design Using XOR Gates
xi yi ci ci + 1 si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Truth table
si = xi′yi′ci + xi′yici′ + xiyi′ci′ + xiyici
= (xi′yi + xiyi′)ci′ + (xi′yi′ + xiyi)ci
= (xi ⊕⊕⊕⊕ yi)ci′ + (xi ���� yi)ci
= (xi ⊕⊕⊕⊕ yi)ci′ + (xi ⊕⊕⊕⊕ yi)′ci
= (xi ⊕⊕⊕⊕ yi) ⊕⊕⊕⊕ ci
ci + 1 = xiyici′ + xiyici + xi′yici + xiyi′ci
= xiyi(ci′ + ci) + ci(xi′yi + xiyi′)
= xi yi + ci(xi ⊕⊕⊕⊕ yi)
Full–adder equation
xxii yyii
ccii
si
ccii + 1+ 1
2.4 4.2
4.2
2.42.4
Logic Schematic (46 Transistors)
Input/OutputPath
Delay(ns)
ci to ci + 1 4.8 ns
ci to si 4.2 ns
xi, yi to ci + 1 9.0 ns
xi, yi to si 8.4 ns
Full–adder delays
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 8
FullFull--adder Design Using Fast Gatesadder Design Using Fast Gates
xi ���� yi = xi yi + xi′yi′
= ((xi yi)′ (xi′yi′)′ )′
= ((xi yi)′ (xi + yi))′
si = (xi ⊕ ⊕ ⊕ ⊕ yi)ci′ + (xi ���� yi)ci
= (xi ���� yi)′ci′ + (xi ���� yi)ci
= (xi ���� yi) ���� ci
ci + 1 = xi yi + ci(xi + yi)
= ((xi yi)′ (ci(xi + yi))′)′
Full–adder equation
xi yi ci ci + 1 si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Truth table
Logic Schematic
(36 Transistors)
Input/OutputPath
Delay(ns)
ci to ci + 1 2.8 ns
ci to si 3.8 ns
xi, yi to ci + 1 5.2 ns
xi, yi to si 7.6 ns
Full–adder delays
xxii
yyii
ccii
ssii ccii + 1+ 1
2.4
1.41.41.4
1.4
1.4
2.4
1.4
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 9
FullFull--adder with Multipleadder with Multiple--Input GatesInput Gates
xi yi ci ci + 1 si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Truth table
Full–adder equations
Logic Schematic
(56 Transistors)
xxii
yyii
ccii
ssiiccii + 1+ 1
2.21.8
1.4 1.4 1.4 1.8 1.8 1.8 1.8
Input/OutputPath
Delay(ns)
ci to ci + 1 3.2 ns
ci to si 5.0 ns
xi, yi to ci + 1 4.2 ns
xi, yi to si 5.0 ns
Full–adder delays
si = xi′yi′ci + xi′yici′ + xiyi′ci′ + xiyici
= ((xi′yi′ci)′ (xi′yici′)′ (xiyi′ci′)′ (xiyici))′
ci + 1 = xiyi + cixi + ciyi
= ((xiyi)′ (cixi)′ (ciyi)′)′
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 10
FullFull--adder Design with Complex Gatesadder Design with Complex Gates
Full–adder equation
xi yi ci ci + 1 si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Truth table
Input/OutputPath
Delay(ns)
ci to ci + 1 3.4 ns
ci to si 4.4 ns
xi, yi to ci + 1 3.4 ns
xi, yi to si 4.4 ns
Full–adder delays
Logic Schematic
(46 Transistors)
ssiiccii + 1+ 1
xxii
yyii
ccii
1.4
2.42.0 2.0
si = xi′yi′ci + xi′yici′ + xiyi′ci′ + xiyici
= ((xi′yi′ci+ xi′yici′)′ (xiyi′ci′ + xiyici)′)′
ci + 1 = xiyi + cixi + ciyi
= ((xiyi)′ (cixi)′ (ciyi)′)′
= ((xi′+ yi′)(ci′+ xi′)(ci′+ yi′))′
= (xi′ yi′ + ci′ xi′ + ci′ yi′ )′
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 11
Using Fast GatesUsing Fast Gates
8-bit Adder/Subtractor Unit Schematic
cout
S
a0 b0a1 b1a2 b2a3 b3a4 b4a5 b5a6 b6a7 b7
f0f1f2f3f4f5f6f7
� Green : 7 * (delay of ci to ci + 1) + (delay of xi, yi to ci + 1)+(delay of XOR)
� Yellow: 6 * (delay of ci to ci + 1) + (delay of xi, yi to ci + 1)+(delay of XOR) +
(delay of ci to si) -longest path
� =6*2.8+5.2+4.2+3.8=30 ns
Input/OutputPath
Delay(ns)
ci to ci + 1 2.8 ns
ci to si 3.8 ns
xi, yi to ci + 1 5.2 ns
xi, yi to si 7.6 ns
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 2
� Design a system that determines if three 2-bit numbers are equal, by connecting 2-bit magnitude comparators together and using additional components if necessary.
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 13
22--bit Magnitude Comparatorbit Magnitude Comparator
x1 x0 y1 y0 G L
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 0
Truth Table
G= x1y′1 + x0y′1y′0 + x1x0y′0
L = x′1 y1 + x′1x′0y0 + x′0y1y0
Logic Schematic
� G = 1 when X > Y,
L = 1 when X < Y,G = L = 0 when X = Y.
y1
G
L
x1
x0
y0
Boolean Equations
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 2 solution
� Comparing 3 2-bit numbers x1x0, y1y0 , z1z0
� Using 4-input NOR
2-bit Magnitude Comparator
x1 x0y1 y0
LG
2-bit Magnitude Comparator
z1 z0
LG
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 3
� Design a 6-to-1 selector.
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 16
88--toto--1 Selector1 Selector S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
Implementation with 2-to-1 Selectors
Truth Table
Implementation with 3-to-8 Decoder
Y
S0S1S2
D0D3 D1
D2D4D7 D5
D6
7 6
5 4
3 2
1 0
Y
D0D3
S0
S1
S2
D1D2D4
D7 D5D6
01
01 01
01 0101 01
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 3 solution
Truth Table
S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 X 0 D4
1 X 1 D5
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 4
� Design a 2-to-4 decoder using 1-to-2 decoders.
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 19
22--toto--4 Decoder4 Decoder
Boolean Expression Logic Schematic
E A1 A0 C3 C2 C1 C0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0
C0 = E0 A′1 A′0C1 = E0 A′1 A0
C2 = E0 A1 A′0C2 = E0 A1 A0
Truth Table
Graphic Symbol E
C3 C0
A0
C2 C1
A1
03 12
A1E
C1C2 C0C3
A0
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 4 solution
� Using 1-to-2 decoder E A1 A0 C3 C2 C1 C0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0
E A0 C1 C0
1 0 0 1
1 1 1 0
0 X 0 0
Truth Table of 1-
to-2 decoder
Graphic Symbol
C1 C0
A0
E01
Truth Table of 2-
to-4 decoder
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 5
� Design an 8-bit shifter that shifts its inputs two bits to the right (shifting in 0s) when the shifter's shift control input is 1. (Hint: use selector)
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine 22
88--bit Shifterbit Shifter Function Table
S2 S1 S0 Y Comment
0 0 X D No Shift
0 1 X Not Used
1 0 0 shl(D) Shift Left
1 0 1 rtl(D) Rotate Left
1 1 0 shr(D) Shift Right
1 1 1 rtr(D) Rotate Right
� 1-bit left or right shift or rotation
Shifter Implemented with 4-to-1 Selectors
d0d3 d1d2d4d7 d5d6
S0
S1
S2
y0y3 y1y2y4y7 y5y6
Right Input
Left Input
0101
03 1203 1203 1203 1203 1203 1203 1203 12
Copyright © 2010-2011 by Daniel D. Gajski EECS 31/CSE31, University of California, Irvine
Problem 5 Solution