direct conversion pulsed uwb transceiver architecture · 2020. 6. 17. · low probability of...
TRANSCRIPT
-
Direct Conversion Pulsed UWB Transceiver Architecture
Raul Blazquez, Fred Lee, David Wentzloff, Brian Ginsburg, Johnna Powell, Anantha P. Chandrakasan
Massachusetts Institute of Technology
-
Outline
IntroductionBaseband TransceiverDirect Conversion TransceiverConclussions
-
Initial Interpretation of UWB
High data rate.Low probability of interception.Excellent multipath resolutionLow interference to preexisting services.Simplicity of implementation (low power, largely digital).
Narrowband
Narrowband
UWB
UWB
1896 1950s 1960s 1980s 1990s 2002 2004
Marconi’sSpark Gap
RadarApplications
First UWBPatents
First UWBPapers
First UWBSystems
FCCReport
First Commercial
Chips
freq
time
-
Regulation Issues
0 2 4 6 8 10 12-80
-75
-70
-65
-60
-55
-50
-45
-40
Frequency (GHz)
UWB
EIR
P Em
issi
on le
vel in
dB
m/M
Hz
Distance1m 10m 100m
500Mb
50Mb
5Mb
500Kb
WLAN
Wireless USB &
Multimedia
Locationing/Tagging
USA7.5GHz of free unlicensed spectrum
EuropeUnregulated
-
Future UWB Standards
480Mbps1m
200Mbps4m
110Mbps10m
Bit RateDistance
IEEE 802.15.3aQoSHigh Data-Rate4 PicoNet in close proximityCost
IEEE 802.15.4aHigh Precision Location CapabilityLarger RangeRobust multipath performanceScalable Data Rate
ApplicationsSafety (Public/Military)Smart BuildingsItem Locating/TrackingNetworking
-
UWB Baseband Transceiver
ADCADC 0
RECEIVER
TRANSMITTERBits to TX
S/P
Correlator 1Correlator 2
Correlator 10
Coarse Acq.Fine Track.Control
Digital Back-end
4 Samples
40 samplesPLL
ADC 1
ADC 2
ADC 3
Pulse Amplifier
Pulse Generator
Frontend
RetimingBlock
BW = 300MHz, Duty cycle = 2%, 31 pulses per bit
-
Front-end
Vin+Vin-
Vout-Vout+
Vb2
Vb1
Vin Vb3
VADC+ VADC-
VDCVb2+ - + - + - + -
+ - + - + - + -
-
Specification of the ADC
4 bits sufficient for reliable UWB detection
Noise Limited Case Interference Limited Case
-30 -25 -20 -15 -1010-4
10-3
10-2
10-1
100
SIR (dB)P
roba
bilit
y of
erro
r
1 bit2 bits4 bits∞ bits
-30 -25 -20 -15 -1010-4
10-3
10-2
10-1
100
SNR (dB)
Pro
babi
lity
of e
rror
1 bit2 bits4 bits∞ bits
-
ADC Architecture
T/H
Preamp Comp 1 Comp 2
Single FLASH ADC channel
Vinp
Vinm
PCC 15
PCC 0
Preamp Comp 1 Comp 2
T15
T15
T0
T0
B0B1B2B3
Switch + CapacitorBetter dynamic performanceLow resolution
Fully Differential Preamplifier and Comparators
Pipelined Decoder
-
ADC (Measurements)
ADC Channel 1
0.620.31250
0.620.31384
INLave / LSBDNLave / LSBfCLK / MHz
Dornberg, J., Lee, H.S. and Hodges, D.A., “Full-Speed Testing of A/D Converters”, IEEE JSSC, Dec 1984.
-
Clock Generation Subsystem
x4 x4 x4 x4
PhaseFreq Det
ChargePump
BiasGen
ChargePump
Xtal
Div by 64
++-
-+
+-
-+
+-
-+
+-
-
Φ1
Φ3
Φ2
Φ4
Delay Cells
ClockBuffers
-
Digital Backend Specification
Correlator 1
Coarse Acq.Fine Track.Control
RetimingBlock S/P
Correlator 2
Correlator 10FromADCs4x
300MHzCustom Layout
30MHzSynthesis
Whole synchronization in digital domain.Coarse Acquisition < 70µs, Fine Tracking Precision = 1sample
-
Coarse Acquisition
Time
Wider integration window?2 samples per pulseNc pulses per bit
Case 1: 1window ⇒ Width N2NcN multiplications2NcN-1 additions
Case 2: N windows ⇒ Width 12NcN multiplications2NcN-N additions
PARALLELIZATION
Time to Coarse Acq. 70 µs
50 correlations in parallel
Loss = 1.7dB
-
Correlators
R1 R2 R3 R4 R5Shift RegistersSample 1
Sample 2Sample 3Sample 4
Correlation 1
R1 R2 R3 R4 R5Shift RegistersSample 37
Sample 38Sample 39Sample 40
Correlation 10
Gold CodeGenerator
Code Reset30MHzClock
1 Correlation:
200 samp/frame31 frames
= 6200 FIR coeffs
50 Correlationsin parallel
-
UWB System on a Chip
1.8 V - 0.18µm non-epiDemonstrated 193kbps wireless link
4.3mm
2.9mm
Correlators
ADC
RF Front EndS/P
S/P
ClockGen.
FineTracking
CoarseAcquisition
Transmitter
Correlators
86mWADC
5mWTransmitter
71mWRF Front-end
347mWTotal
75mWBackend
65mWCLK Buffers
45mWPLL
Power Consumption
-
0 50 100 150 200-1
-0.5
0
0.5
1
ns
The UWB Channel
BWmin = 500 MHz Limitations:
In band interferers. (802.11a)Multipath. 580 ps/div
150 mV
-150 mV
Extreme NLOS
NLOS 4-10m
NLOS 0-4m
LOS 0-4m
Description
14.3nsCM3
25nsCM4
8.0nsCM2
5.3nsCM1
RMS Delay
-
Two Proposals for 802.15.3a
Time Frequency
Pulsed UWB MB-OFDM
Prefix removal
FFT
Slicers
S/P
P/S
Samples
BitsIntegrate & Dump SlicerSamples
Template
Bits
Simple TransmitterGood behaviour with non-linearities
ISI ⇒ Viterbi-like MLSE Equalizer
Elegant EqualizationSimilar to 802.11a
Linearity required
FCC to rule on this dispute next week
-
ADC Impact in UWB Signals
Pulsed UWB MB-OFDM
-10 -5 0 5 10 15
10-4
10-3
10-2
10-1
100
SNR (dB)
Pe
1 bit2 bits3 bits4 bitsno quantization
-10 -5 0 5 10 15
10-4
10-3
10-2
10-1
100
SNR (dB)
Pe
1 bit2 bits3 bits4 bitsno quantization
Solution: Coding
R. Blazquez, F. S. Lee, D. D. Wentzloff, P. P. Newaskar, J. D. Powell, A. P. Chandrakasan, "Digital architecture for an ultra-wideband radio receiver", VTC Fall 2003, Orlando FA, October 2003.
-
Direct Conversion ReceiverB
ASE
BA
ND
PRO
CES
SIN
G
PulseGeneration
ADCI
ADCQ
TRASMITTER
RECEIVER
Spectral Compliance, Jitter
Impulse ResponseForm Factor, Wideband
Matching
Impulse ResponseForm Factor
Dynamic Range, NF,Linearity,
Impulse ResponseNumber of bitsSample Rate
Narrowband Interferer
802.11a (30dBm)
-
Power Budget for a UWB Transceiver
MB-OFDM : Front-end: 117.5 mW (Bergervoet et al. ISSCC’05) (SiGe BiCMOS 0.25)Clock and carrier generation: 73.44 mW (Leenaerts et al. ISSCC’05) (SiGe BiCMOS 0.25)Digital Back-end: 523 mW (Liu et al. ISSCC’05) (CMOS 0.18)Estimated for 90nm CMOS (MBOA White paper): 93mW in transmission, 169mW in reception
Pulse UWB (DSSS)Total: 280mW (Iida et al. ISSCC’05) (CMOS 0.18)
-
Discrete Prototype
Splitter
5.335GHz PLL
Splitter
Tuned TX lineFor Quadrature
PGM board
X 1GSPSADC
1GSPSADCX
X5.335GHz
PLL
PGM board
PulseGenerator
100MHz TektronixPattern Generator
Mat
lab/
FPG
A
6GHzLNA
6GHzLNA
DigitallyControlledVGA
DigitallyControlledVGA
LPF250MHz
LPF250MHz
Demonstrated 100Mbps wireless link
-
-40 -30 -20 -10 0 10
0
30
60
90
120
150
180
-150
-120
-90
-60
-30 30
60
90
120
150180
-150
-120
90
-60
-30
0
Max Gain 2.11 dB
Lincoln Laboratory Measured Azimuth Pattern
4 GHz
Antenna
5cm
2.5cm
VSWR < 2 for 3.1- 10.6 GHzNear Omnidirectional PatternHigh Radiation EfficiencyPhysically Small SizeShort impulse response
Johnna Powell, Anantha P. Chandrakasan, "Differential and Single Ended Elliptical Antennas for 3.1-10.6 GHz UWB Communication", IEEE Antennas and Propagation Society International Symposium, June 2004.
-
RF Front-end
802.11aNotch Control
UWB S2D
UWB LNA
Freq ControlUWBFilter
Gain & Switch
LO I IN
Out Q
I
Q
VCO/EXT LO switch
VCO/EXT LO switch
RFIN
Out I BasebandGain
BasebandGain
Adjustable
500Msps5-Bit ADC
500Msps5-Bit ADC
Digital Back-end
Adjustable
DataOut
LPF
LPF
Gain & Switch
LO Q IN
Divider OutputUWB TunableQ-VCO PLL
-
Programmable Baseband
Ret
imin
g B
lock
Freq
. Cor
rect
ion
Correlators/RAKES
erie
s to
par
alle
l
Correlator 1
Coarse Acquisition
Initialization
Threshold
Sam
ples
from
AD
C Correlator 2
Correlator P
Channel Estimator Impulse response
Interference Detection
Interference PowerSamples from ADC
Bits
ProgrammableFeatures
TI/TS ↓MLSE Viterbi
Equalizer
Automatic Gain Control
To RF Front-end
PLL/DLL
Length of impulse response
Tracking
-
0 5 10 15 20 25 300
10
20
30
40
50
60
70
Number of pulses integrated
Tim
e to
pac
ket s
ynch
roni
zatio
n ( µ
s)
0 5 10 15 20 25 300
5
10
15
Pro
cess
ing
gain
(dB
)
Parallellization
Faster acquisition.Slower clock. Lower Vdd.
Correlators ArchitectureCoarse Acquisition Trade-off
R1 R2 RqShift Registers
x1[n]
Correlation 1
Serie
s to
Par
alle
l
R1 R2 RqShift Registers
xP[n]
Correlation P
GoldCode(-1/+1) Reset(0/1) Clock
x[m]
xi[n]=x[Pn+i]
-
0 5 10 15 20-0.5
0
0.5
1
1.5
Impu
lse
resp
onse
Rake Receiver
Channel Impulse Response (with multipath effects)
6 finger RAKE Method implementedVariable number of fingers based on relative amplitude of response.
Number of fingers fixed
0 5 10 15 20-0.5
0
0.5
1
1.5
Impu
lse
resp
onse
0 5 10 15 20-0.5
0
0.5
1
1.5
Impu
lse
resp
onse
-
Adapting to the Channel
1 1.5 2 2.5 3 3.5 40
0.5
1
1.5
2
2.5
3
3.5
4
L
Loss
(dB)
CM1CM2CM3CM4
NUMBER OF STATES OF MLSE EQ.
KNOBS AVAILABLE TO ADAPT THE COMPLEXITY TO THE CHANNEL QUALITY
Digital baseband estimates channel properties:
Interference (ISR)Multipath (Impulse Response)Signal power
Controls over signal processing:
Number of states of equalizer.Number of bits of ADC.Threshold of the channel.
-
Conclusions
SoC implementation is difficult.
Higher data rate implies complexity.
Parallellization allows power reduction.
Adapt the complexity of the transceiver to channel quality.