Digital Voltmeter (DVM)

Introduction:•DVM can measure ac or dc Voltage and currents•DVM can measure digitally instead of analog reading•DVM reduce the human mistakes in reading and eliminate parallax error•Smaller size & low cost•High stability•Input resistance ≈ 10MΩ and input capacitance Cin ≈ 40pF•High resolution (1μv can be read on 1 v range)•Bigger range from 1v → 106v with automatic range selection and overload protection.

Types of digital voltmeters:

a)Ramp – type DVM:

The operating principle of the ramp-type DVM is based on the measurement of the time it takes for a linear ramp voltage to rise from 0v to the level of the input voltage, or to decrease from the level of the input voltage to zero. This time interval is measured with an electronic time interval counter, and the count is displaced as a number of digits on electronic indicating tubes. Conversion from a voltage to a time interval is illustrated by the wave from diagram as follow.

Start of measurement

coincidencevoltage being measured

0

12 v

Ramp

Time

Time

-12 v

t

clock pulse to counter

gating time interval

•At the start of the measurement cycle, a ramp voltage is initiated, this voltage may be positive decreasing to –ve or –ve increasing to +ve.

• The ramp voltage is compared by the input unknown voltage. At the instance that the ramp voltage equals the unknown voltage, the coincidence or comparator generates a pulse, which opens a gate.

•The ramp voltage continuous to decrease with time until it finally reaches 0v and the 2 nd comparator (Ground Comparator) generates an output pulse, which closes the gate.

•An oscillator generates clock pulses which are allowed to pass through the gate to a counter, the no. of counted pulses is proportional to the input unknown voltage where the output of the counter is displayed by the indicator.

Block diagram of ramp –type digital voltmeter

Rangingand attenuator

Osc. Gate

Readout

Counter

SampleRate MV

RampGenerator

Dc inputInput Comparator

Start pulse

Stop pulse

Ground Comparator

Successive-approximation conversion

The block diagram of DVM using successive approximation conversion is as Follow.

D/ A Converter

Succesive approximation Register

DecisionLogic

inputComparator

cable

clock

clear

clock

Data output

•To understand this types DVM technique, we assume the following example:Assume the input voltage that is required to be determined is 499. The successive approximation register generates a binary pattern with the indicated weight

8

7 6 5 4 3 2 1 0

2 2 2 2 2 2 2 2 2

256 128 64 32 16 8 4 2 1•The required number that is required to be determined is between 0 and 511. The first guess would be some number midway between the extremes and ideally 256 [100000000] which will be the output of SAR. The D/A will convert it to 256 which will be applied to the input of comparator with also the input voltage (499).

•The input is still greater than the estimate (output of D/A converter). Thus the output of the comparator is low indicating that the estimate is lower than the input signal, the first output remains in logic one state and the second output assumes the logic one state i.e. the output of the SAR in the second clock will be 110000000. The estimate will be 256+128=384

•Again the output of the comparator is low and again the decision logic make the SAR output in the 3rd guess will be 111000000. The estimate will be 384+64=448

•Again the output of the comparator is low and the decision logic make the output of the SAR in the 4th guess to be 111100000.The estimate will be 448+32=480

•Again the output of the comparator is low and the decision logic make the output of SAR in the 5th guess to be 111110000. The estimate will be 480+16=496

•Again the output of the comparator is low and by the same manner the output of the SAR in the 6th guess will be111111000. The estimate will be 496+8=504.

•In this case the output of the compatator is high because the estimate is greater than the input and the decision logic clear the last bit or you can say reverse the state and the 2nd output changes to logic one i.e. the output of the SAR will be in the 7th guess 111110100. The estimate will be 496+4=500.

•Again the output of the comparator is high and the decision logic will clear the last state and again the output of SAR will be in the 8th guess 111110010. The estimate output will be 496+2=498. In this case the output of the comparator is low and the decision logic make the output of SAR in 9th guess to be 111110011The estimate output will be 499(convert). In this case the SAR will appear or supplied to the data output.

Advantages of the successive_approximation conversion•less expensive.•More effective type.