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Digital Systems TestingDesign for Test by Means of Scan

Moslem Amiri, Vaclav Prenosil

Embedded Systems LaboratoryFaculty of Informatics, Masaryk University

Brno, Czech Republic

[email protected]

[email protected]

December, 2012

Introduction

Most test generation schemes look at a CUT as a black box

The only available nodes for testers to control are CUT’s primary inputs,and to observe are its primary outputsThis limited controllability and observability of CUT means complex testgeneration algorithms for circuitsTo overcome this difficulty in testing, digital circuits must become moretestable by incorporation of design for test (DFT) techniques

DFT techniques offer ways of making internal structure of a design morecontrollable and easier to observeBecause such tasks are handled by designers, HDLs play an importantrole in facilitating insertion and evaluation of hardware structures thatare put in a circuit for making it more testable

Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 2 / 84

Making Circuits Testable

A circuit is testable if tests can be generated for it efficiently, it can betested with a high fault coverage, and the time it takes to test themanufactured part is reasonable

Testability is a combination of controllability and observability

A circuit becomes more testable by making it more controllable andmore observable


Making Circuits Testable: Tradeoffs

DFT techniques that make circuits more testable always introduceadditional hardware that results in more pins, more delays, more powerconsumption, and a hardware overhead

What we get instead is a better coverage and reduced test timeIn some cases, DFT techniques gain access to internal structures of acircuit that would otherwise be impossible to testReducing the extra test hardware, its power consumption during test,the delay it introduces in design, and extra pins that are needed, areparameters a design engineer must optimize


Making Circuits Testable: Testing Sequential Circuits

Generating a complete test for a sequential circuit is very complex

Even if tests are generated, application of test requires many clockcycles to move a circuit into states that activate faults

One of the most important contributions of DFT is making sequentialcircuits testable

DFT techniques alter a sequential circuit model in such a way thatcombinational test techniques can be used for itDFT techniques define ways in which tests generated for a combinationalmodel of a sequential circuit can be applied to actual sequential circuit



Huffman model is a useful model for sequential circuit testingA sequential circuit is modeled by a combinational circuit havingfeedback through delay elementsIn synchronous sequential circuits, delay elements are clocked flip-flops,and each feedback is a state variableCircuit primary inputs and outputs only apply to combinational partSynchronous or asynchronous set, reset, and other control inputs onlyapply to feedback flip-flopsThis model separates a CUT’s registers from its combinational part

Figure 1: Huffman model for test.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 6 / 84


Usefulness of Huffman model is in separation of registers andcombinational part of a digital system

This separation enables application of test methodologies tocombinational part, and treating registers separatelySince majority of a circuit’s logic gates are contained in combinationalpart, testing this part, while considering register part inputs andoutputs, covers majority of a circuit’s faultsSince flip-flops are treated as primitive building blocks in mosttechnologies, testing a circuit for internal flip-flop faults is a secondaryissue in most logic test systems



A circuit model that separates combinational and register parts, andputs focus of testing on combinational part is obtained by unfoldingcircuit model of Fig. 1

This is shown in Fig. 2By unfolding a sequential circuit, its registers are separated and ignoredRegister outputs become pseudo primary inputs (PPI) for unfoldedcircuit, and register inputs become pseudo primary outputs (PPO) ofthis circuitTest results obtained from unfolded model are used by test equipmentfor testing actual circuit

Figure 2: Unfolded circuit model.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 8 / 84

Making Circuits Testable: Combinational Circuits

Combinational circuits can also benefit from DFT techniques

With an additional hardware inserted into a combinational circuit, it canbe made to give a better coverage, reduce the number of test vectorsrequired to test it, or achieve both at the same timeDFT techniques alter a combinational circuit for better controllabilityand observability


Testability Insertion: Improving Observability

Adding output pins improves observability

Enables fault effects (that would otherwise not propagate to a primaryoutput) to have a chance to show themselves through newly addedoutput pinsResults in fewer test vectors to test for faults, thus less test applicationtimeLines with observability values below a certain threshold can beconsidered as candidates for becoming extra output pins

State flip-flops outputs can also be made observable by pulling themout as primary outputs

In Fig. 3, flip-flop outputs are pulled as primary outputsStarting in state V1V0 = 10, while a = 1, SA0 fault shown can bedetected in one clock cycle on new Out V1 outputProvisions for forcing this circuit into a certain state (e.g., V1V0 = 10)are made in Fig. 3

0 or 1 insertion



clk

a w

1D

1D

C1

C1

V1V0

Out V1

Out V0

0 or 1 Insertion

0 or 1 Insertion

SA0

0 Insertion1 Insertion

Figure 3: Basic testability techniques (observability, controllability).Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 11 / 84


In an RT-level design, appropriate places where extra output pins canbe added are

Control signals for flow of data through buses and logic unitsLogic and ALU control inputsBus and multiplexer select inputsMultiplexer and decoder enable inputsTri-state controlsRegister load inputCount up and count down signalsShift-register mode control inputsFeedback lines


Testability Insertion: Improving Controllability

Controllability parameters identify hard-to-reach places (lowcontrollability lines) in a combinational circuit and add controllabilitythere

In sequential circuits

Flip-flop inputs are good candidates for being directly controlled bycircuit inputsIn addition, controlling flip-flop reset and other control inputs helpdriving a sequential circuit into a given state

In RT-level designs, direct control of control signals coming from acircuit’s controller to its datapath enables testing of individual dataoperations independently

Other places to add controllability

Multiplexer and bus control inputsTri-state control inputsALU select inputsCounter and shift-register mode control signals



Insert 0

LogicA

Insert 1

LogicA

Insert 0

LogicA

Insert 1

0

1

td

0 Inserting

a b

c d

1 Inserting

0 and 1 Inserting Normal and Test Data

LogicB

LogicB

LogicB

LogicA

LogicB

NbarT

Figure 4: Several methods to add controllability.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 14 / 84


Fig. 4

In (a), to drive a 0 into input of Logic B, Insert 0 must be set to 1In combinational circuit testing, 0-insertion and 1-insertion structuresare useful in places with low 0- and 1-controllability, respectivelyIf hardware structures shown do not share pins with other teststructures, 0- and 1-insertions require one primary input pin, while othertwo structures require two pinsIn all cases, timing delays are added between two logic parts

Multiplexer has the largest delay

Fig. 3

To force state V1V0 = 10 into flip-flops, 1-insertion and 0-insertionstructures should be used at inputs of flip-flop 1 and flip-flop 0,respectivelyTesting this circuit becomes easier by use of multiplexers at its flip-flopinputs

Shown in Fig. 5



Figure 5: Put circuit into any desired state.


Testability Insertion: Sharing Observability Pins

When using observability points, to reduce cost of external pins, amultiplexer can be used

An n-to-1 multiplexer can be used to multiplex n test points into oneoutput pinRequires log2 n input pins for multiplexer select inputsMultiplexing observation points prevents simultaneous observation ofmultiple observation points, thus increases test timeIn addition, multiplexer adds extra hardware and delay overhead

n Points To

Observe

logn2

Figure 6: Multiplexing observability points.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 17 / 84

Testability Insertion: Sharing Observability Pins

Hardware shown in Fig. 6 can be repeated if multiple activation ofseveral observation points are required

For observing parallel buses, same bit positions of several buses can begrouped, and the hardware shown in Fig. 6 can be used for each groupIn this case, select inputs can still be shared, but actual output data pinmust be repeated for each group


Testability Insertion: Sharing Control Pins

To reduce pins required for controlling n internal lines of a circuit, a1-to-n demultiplexer is used

A demultiplexer is a decoder with an enable input

Logic structure in Fig. 7 is for a 1-to-4 demultiplexer (2-to-4 decoder)

S1 S0

y0

y3

y2

y1

En or Data

Decoder / Demultiplexer

n Points To

Control

S2

S1

S0

Figure 7: Demultiplexer/decoder, reduce pins for control.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 19 / 84


Figure 8: Sharing 0-insertion hardware.



Figure 9: Sharing test data insertion hardware.



Demultiplexing control points prevents simultaneous assignment ofvalues to control points that share pins

Therefore, simultaneous assignment of test data to bits of parallel busesis not possible unless hardware of Fig. 9 is repeated for each bus bitthat needs to be controlled

Figure 10: Simultaneous control of bits of buses.


Testability Insertion: Reducing Select Inputs

Although multiplexing observation points (Fig. 6) and demultiplexingcontrol points (Fig. 7) significantly reduce test pin counts, for a largenumber of test points, we still have many pins for select inputs

We can resolve this problem by adding a counter to CUTCounter is used for selection inputsFor controlling or observing a line, counter counts up, and when itreaches the number of the test point, other test signals are issuedTest time will be longer

Figure 11: Selection input counter.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 23 / 84

Testability Insertion: Simultaneous Control of Test Points

None of techniques discussed above allowed simultaneous activation ofcontrol or observe points

Unless separate test pins were used and hardware structures wererepeated (e.g., Fig. 10)

To allow simultaneous control for several test points and still keepingthe number of pins low, a shift-register can be used

To take test data serially, and apply all bits in parallel in test mode

Fig. 12In normal mode, NbarT = 0While in normal mode, test data can be shifted into shift-registerwithout affecting normal operation

Because test data shifting takes several clock cycles, we overlap normaloperation with shifting test data into shift-register

When test data are completely shifted in, CUT is put in test mode(NbarT = 1), which allows test data from shift-register to be used forinput of logic blocksSerial shifting of test data is a time-consuming process

One way to improve this is by use of a faster clock for test clock


Testability Insertion: Simultaneous Control of Test Points

Figure 12: Shift-register for simultaneous control.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 25 / 84

Testability Insertion: Simultaneous Test Points Observation

A shift-register can be used for simultaneous collection of values fromseveral test points and shifting them out seriallyFig. 13

In test mode, when response of CUT is ready at shift-register input, loadinput is enabled and shift-register is clockedThen load is deasserted, which puts shift-register in serial modeBy applying n clocks in this mode, line values are shifted out

Figure 13: Using a shift-register for simultaneous collection of line values.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 26 / 84

Testability Insertion: Isolated Serial Scan

Isolated serial scanThe two concepts of using a shift-register for controlling test points andone for observing them can be combined and the same shift-register canbe used for both purposes

Fig. 14

In normal mode, NbarT = 0While in this mode, shift-register is put in serial mode and new test dataare shifted in, while collected data from last testing to be observed(from YO3,YO2,YO1,YO0) are being shifted outAt the end of shifting, CUT is put in test mode by asserting NbarTThis applies test data in shift-register to inputs of CUTWhile CUT is propagating this test data, shift-register mode is changedto parallel loadingEnough time is given for test data to propagate and show its effect onYO internal output linesAt this time, shift-register is clocked just once to collect outputThis is followed by serial mode that shifts in a new test data whileshifting out data that were just collected



Figure 14: Isolated serial scan.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 28 / 84


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Figure 15: Isolated serial scan shift-register.

Fig. 15Shows Verilog code of shift-register used in Fig. 14TestMode = 0: does nothingTestMode = 1: right shiftingTestMode = 2: parallel loadTestMode = 3: resets shift-register



Figure 16: Isolated serial scan virtual tester.

Fig. 16Shows pseudo code for equipment that connects to pins of CUT in Fig.14 and tests itSince this code plays role of an ATE, it is referred to as a virtual tester


Full Scan

The most common DFT technique is full scan

Very similar in concept to isolated scan

Problems with isolated scan

Has an overhead of a shift-registerInclusion of this register still does not solve problem of test generationfor sequential circuits

We still have to treat CUT as a sequential circuit with a few extra testpoints for adding controllability and observability

Full scan takes care of hardware overhead and sequentiality of CUT byincorporating required shift-register in CUT’s state flip-flops

Reduces hardware overheadCUT becomes virtually a combinational circuit


Full Scan: Full Scan Insertion

Starting with Huffman model of a sequential circuit (Fig. 1) andunfolding it (Fig. 2), and applying testing to combinational part,covers all logic and register interconnection faults

Full scan testing takes Huffman model of Fig. 1, and by inserting ashift-register in its register structures, makes a virtual model of theunfolded circuit of Fig. 2



Figure 17: Scan insertion.



Test procedure for testable Huffman model of Fig. 17Only involves testing combinational part, and modified register is usedas a mechanism for providing controllability of ps and observability of ns

ps becomes pseudo primary inputs (PPI), and ns becomes pseudoprimary outputs (PPO) of combinational part

In normal mode (NbarT = 0), register loads ns to psIn test mode (NbarT = 1), test data (PPI) that is to be applied to ps isshifted into registerWhen all data bits are shifted, first part of test data is ready at ps input(PPI)At this time, second part of test data is applied to circuit’s primaryinputs through external pins (PI)Combinational circuit takes the two-part test data (PI and PPI) andpropagates it to its outputsPrimary outputs (PO) are collected and storedWe then put circuit in normal mode (NbarT = 0), and clocking circuitonly onceThis causes ns part of output (PPO) to get clocked into registerPPO is shifted out, so that together with PO forms complete outputWhile this shifting is happening, we also shift in a new test data



module FBRegister #(parameter size = 4)(input [size-1:0] ns, input

always @ (posedge Clock) beginif (Reset == 1'b0) begin if (NbarT == 1'b0) ps <= ns; else ps <= {STDI, ps[size-1:1] }; //shift mode

endelse

ps <= 0; endassign STDO = ps[0];

endmodule

STDI, Clock, NbarT, Reset, output STDO,output reg [size-1:0] ps);

Figure 18: Testable Huffman model feedback register; ns = next state, ps =present state, STDI = serial test data in.


Full Scan: Flip-flop Structures

Verilog code of Fig. 18 assumes a simple flip-flop structure and amultiplexer for selection of normal and shift modes

In addition to this structure, there are other structures that are moreefficient in terms of timing and gate structures

Latches cannot be used in feedback paths in sequential circuits unlesscomplemented by other logic structures or other latches

When clock is active, inputs of latches directly affect Q output

Flip-flops can be used in sequential circuit feedback paths



Figure 19: Basic latch.

Figure 20: D latch.

D 1D

Q

C1

1D

Q

C1

Q

1D

Q

C1

Q

D

C

Figure 21: D-type flip-flop.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 37 / 84


Figure 22: Multiplexed scan element.

module MuxedFF (input NbarT, Reset, DataIn, SerialIn, Clock, output reg OutFF);always @ (negedge Clock) begin

if (Reset) OutFF <= 1'b0;else OutFF <= ~NbarT ? DataIn : SerialIn;

end endmodule

Figure 23: Multiplexed scan element Verilog code.

Flip-flop of Fig. 22Provides a close correspondence with Verilog description of Fig. 18Can be used as a scan element for feedback register in Fig. 17



Figure 24: Scan register with multiplexed flip-flops.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 39 / 84


Modeling multi-bit feedback registersWe can use a Verilog code similar to scan code in Fig. 18

Appropriate for a behavioral description of a scan-inserted circuit

Or, we can individually cascade flip-flops of Fig. 23 to form the rightsize register

Useful in a netlist where low-level detailed simulations may be needed

Flip-flop of Fig. 22

Is simpleHas problem of multiplexer delay that adds to logic delay

This structure increases the worst-case delay of circuit for which scan isinsertedThis reduces speed of normal system clock, and thus, a slower overalloperation



Dual clockingIn Fig. 17, with each normal mode clock, ps output of feedback registermust travel through entire combinational part to affect this part’s nsoutputThis involves a delay, only after which the register can be clocked againThis delay is the worst-case delay of CUT, and its normal clock speedhas to be slow enough to allow complete propagation of ps into nsthrough combinational partSuch a delay does not apply when running circuit in test mode

In this mode, we are only shifting data into shift-register, and the onlylogic is that between flip-flop bits (see Fig. 24)

Therefore, test mode clocking can be faster than normal data clockingIn larger circuits with many serial bits to shift-in, using a faster clock fortest time gains a good saving in time



1D

Q

C1

OutFFDataIn

DataClock

SerialInTestClock

Figure 25: Scan flip-flop with dual clocking.

module DualClockFF (input DataIn, DataClock, SerialIn, TestClock, output reg OutFF); wire Clock;

assign Clock = DataClock | TestClock;always @ (negedge Clock) begin

if (DataClock) OutFF <= DataIn;else if (TestClock) OutFF <= SerialIn;

endendmodule

Figure 26: Dual clock scan flip-flop Verilog code.



Fig. 25

AND-OR logic at flip-flop input selects DataIn when DataClock is 1 andselects SerialIn when TestClock is 1While either clock is 1, proper data appear at flip-flop D-input, and afterclock becomes 0, data at D are clocked into flip-flopProblems

Hazard may occur in logic at flip-flop D-inputLogic gates at inputs of circuit flip-flops increase the worst-case delay ofcircuit

To reduce flip-flop D-input logic delay, clocking scheme of Fig. 27 canbe used



Figure 27: Two-port three-clock flip-flop.

Figure 28: Two-port flip-flop timing.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 44 / 84


Figs. 27 and 28

For loading DataIn into flip-flop, ClockA and ClockB are assertedalternatively, while ClockC remains at 0For loading SerialIn, ClockC and ClockB are applied in alternativeorders, and in this case ClockA is inactiveWhen ClockA is asserted, while ClockB is 0, data on DataIn is latchedinto master latch and appears on M

When ClockB is asserted, data on M is latched into flip-flop outputSituation is similar when ClockA is inactive and ClockC toggles

This flip-flop avoids multiplexer delay of previously mentioned flip-flopsClocking mechanism allows different clock speeds for normal and testmodesThis structure has overhead of having to handle three clock signals



Figure 29: Two-port flip-flop symbol.

Figure 30: Dual-port flip-flop Verilog code.



Figure 31: LSSD design.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 47 / 84


LSSD (Level Sensitive Scan Design) (Fig. 31)

Was first used by IBM in 1977Overall operation is the same as that of Fig. 24For normal operation, ClockA and ClockB are usedIn test mode, ClockC and ClockB become complementary clocks


Full Scan Design and Test

This section shows flow of DFT from a problem specification togenerating test and developing a test program

The example that is used is Residue-5 circuit

This is a sequential circuit, for testing of which DFT techniques areessential

Residue-5 design should be taken through following steps (The last twosteps will not be discussed)

Design and design validationSynthesis and netlist generationUnfoldingCombinational test generationScan insertionDeveloping a virtual testerTest set verification


Full Scan Design and Test: Design and Design Validation

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Figure 32: residue5 partial Verilog code.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 50 / 84

Full Scan Design and Test: Design and Design Validation

Residue-5 circuit is described in Fig. 32

Coding style is according to Huffman model of Fig. 1Register part specifies a resetting mechanism, which means that thisreset signal does not participate in combinational part of circuit

Keeping reset and other flip-flop control signals away fromcombinational part is good for postmanufacturing testing

The design described in an HDL must be validated

A testbench for functional testing of design must be developedThis topic has been covered before


Full Scan Design and Test: Synthesis & Netlist Generation

Next step after design validation is synthesis

Synthesized Verilog code of Fig. 32 is shown in Fig. 33

An FPGA-based synthesis program and a netlist converter are used herefor synthesizingThis netlist uses primitives that are compatible with PLI functions forfault collapsing, fault simulation, and test generationThe netlist consists of basic gates with feedbacks through threeflip-flops

This is compatible with Huffman model of Fig. 1

Before going to next step of design, it is necessary to performpostsynthesis simulation of this netlist and make sure it is a correcttranslation of behavioral model of Fig. 32


Full Scan Design and Test: Synthesis & Netlist Generation

module residue5_net(clk, reset, in, out); input clk; input reset; input [1:0]in; output [2:0]out; wirewire_1, wire_2, . . .

. . .

. . .

. . .

. . .

in_0_0, in_0_1,

out_0_0, out_0_1,

pin #(2) pin_0 ({in[0], in[1]}, {in_0, in_1}); pout #(3) pout_0 ({out_0_7, out_1_7, out_2_5}, {out[0], out[1],

out[2]}); fanout_n #(8, 0, 0) FANOUT_3 (in_0, {in_0_0, in_0_1, in_0_2, in_0_3,

in_0_4, in_0_5, in_0_6, in_0_7}); fanout_n #(7, 0, 0) FANOUT_4 (in_1, {in_1_0, in_1_1, in_1_2, in_1_3,

in_1_4, in_1_5, in_1_6});

notg #(0, 0) NOT_1 (WIRE_3, in_1_0); notg #(0, 0) NOT_2 (WIRE_4, out_2_0);

and_n #(3, 0, 0) AND_14 (wire_25, {wire_6_5, wire_3_4, out_2_4}); or_n #(4, 0, 0) OR_2 (wire_21, {wire_25, wire_24, wire_23, wire_22}); dff INS_1 (out_0, wire_1, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0);dff INS_2 (out_1,wire_13, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0);dff INS_3 (out_2,wire_21, clk, reset, 1'b0, 1'b1, NbarT, Si, 1'b0);

endmodule

Figure 33: Postsynthesis residue5 netlist.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 53 / 84

Full Scan Design and Test: Unfolding

After synthesis, we start test generation process

Circuit in Fig. 33 is a sequential circuit, and test generation methods forsequential circuits are not efficient in terms of fault coverageFor this reason, we convert CUT to a combinational circuit by unfoldingit, as presented in Fig. 2

Unfolding means removing flip-flops and making their outputs andinputs, pseudo primary inputs and pseudo primary outputs

Fig. 34 shows residue5 netlist after being unfolded

out 0, out 1, and out 2 that used to be flip-flop outputs are nowmapped to PPI0, PPI1, and PPI2Former flip-flop inputs wire 1, wire 13, and wire 21 are now mapped toPPO1, PPO13, and PPO21New signals mentioned above also appear on circuit port list as inputsand outputs


Full Scan Design and Test: Unfolding

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Figure 34: Unfolded residue5 netlist.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 55 / 84

Full Scan Design and Test: Combinational TG

Netlist in Fig. 34 represents a combinational circuitWe can use random test generation methods and Verilog testbenches forimplementing them, as discussed earlier in this course

Verilog testbench should generate collapsed fault list before testgenerationUsing combinational test generation will result in 100% fault coverage

If we use sequential test generation (as discussed previously), testgeneration will take longer time (clock cycles), and worse, it will resultin less fault coverage


Full Scan Design and Test: Scan Insertion

To facilitate application of tests generated by procedure discussedabove to actual CUT, a scan for accessing state flip-flop inputs andoutputs is inserted in CUT

With insertion of this scan, block diagram of netlist of residue5 becomesas that shown in Fig. 35For this purpose, postsynthesis netlist of Fig. 33 is modified to includenecessary scan flip-flops and signals

Synthesis tool, that generated original netlist, used flip-flop types thatalready included serial shift facilities that were not used in this netlistFig. 36 shows this flip-flop

In Fig. 35

Notation for flip-flop D inputs marked by 1,2D and 1,3D specifies thatboth D inputs are controlled by clock signal number 1Upper input requires mode 2 to be active and lower input needs mode 3Modes 2 and 3 are determined by a 1 or a 0 on lower-left inputs offlip-flop



Figure 35: residue5 with scan chain.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 58 / 84


�

�

�

�

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Figure 36: Flip-flop with scan facilities.



Figure 37: Scan-inserted circuit under test.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 60 / 84


Netlist of Fig. 37

Takes advantage of shift features of flip-flop of Fig. 36This netlist has additional scan control inputs NbarT and Si

NbarT input connects to NbarT inputs (shift control) of state flip-flopsSi input connects to flip-flop 0 (INS 1), output of which goes to input ofthe next, eventually forming a chain of three scan flip-flops

Signal out 2 that is output of last flip-flop drives So serial output signal


Full Scan Design and Test: Tester

Netlist of Fig. 37 implements original desired functionality of design,as well as our inserted test hardware

Once manufactured, it has to be tested with a test plan that depends ontest architecture that we have developed, i.e., full scanTest program running on an ATE implements this test planBlock diagram of tester testing full scan version of Residue-5 circuit isshown in Fig. 38



Figure 38: Tester for residue5.



Fig. 38

Main task of tester is to read predetermined test data from an externalfile, apply it to CUT, get output of CUT, and compare the responsewith expected response from external fileInput data read from test file has two parts

One part (PI) is directly applied to circuit’s primary inputs, in[1:0]The other (Pseudo PI) is serialized and applied through Si

Timing of these data is such that when all serial bits have been shiftedin scan chain, parallel data must be applied to in[1:0]Output also has two parts

First part (PO) becomes available on out[2:0] immediately after allinputs have been appliedState outputs (Pseudo PO) become available after flip-flops have beenclocked and then shifted out through So

Arrangement of inputs and outputs in a line read from test file is shownin Fig. 39



Figure 39: Arrangement of stimulus and response in line.


Scan Architectures

Full scan is part of a larger category of DFT techniques that arereferred to as scan architectures


Scan Architectures: Full Scan Design

Full scan DFT technique

Feedback registers are given additional capability of acting asshift-registers in test modeFull scan chains all registers together and provides a serial-in and aserial-out portsThis method enables serial access for controlling all flip-flop outputs(circuit’s present state) and observing all flip-flop inputs (circuit’s nextstate)Full scan refers to the fact that all circuit flip-flops are included in scanchainProblem with full scan is long chain of flip-flops that test data have tobe shifted into that reflects on test time



Figure 40: Huffman model with multiple vector inputs, outputs, and states.



Figure 41: Full scan DFT technique.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 69 / 84

Scan Architectures: Shadow Register DFT

An alternative design to full scan design is use of shadow registers

This technique duplicates feedback registersIt uses one set for normal operation of circuit and another set for testpurposesThis method reduces test time by overlapping time of test datapreparation and response collection with normal operation of circuit



Figure 42: Shadow register.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 71 / 84


Shadow test procedureNormal mode

NbarT = 0Circuit has its normal inputs, and normal feedback registers provide datafor present state of circuitShadow registers are put in their serial shift modeTherefore, simultaneous with normal operation, test data on Si areshifted into shadow registers with TclkWhen all test data are shifted in, NbarT is asserted

Test modeNbarT = 1 −→ disables shifting serial data into shadow register, anddisables clk, and test states (TS1 and TS2) will drive ps1 and ps2We also drive PI1 and PI2 with their corresponding test dataWith test inputs provided to all combinational block inputs, responsebecomes available on PO1, PO2, ns1, and ns2Primary output part of response (PO1 and PO2) can be read at this timeClocking circuit loads ns1 and ns2 into shadow registersNbarT = 0 −→ clk is enabled and circuit is put in normal mode −→ thisputs shadow registers in shift mode −→ new test data inputs are shiftedfrom Si, and part of test response on ns1 and ns2 are shifted out via So



Shadow vs. full scan

The biggest advantage of shadow registers is capability of online testingIts disadvantage is doubling the number of feedback flip-flopsTiming

Having a separate clock for test (Tclk) enables faster shifting of testdata into shadow registersOn the other hand, multiplexers in feedback path cause a delay in thispathThis delay slows down normal clock speed and affects systemperformance

For test generation, combinational methods can be used with unfoldedversion of CUT

This is because insertion of shadow registers makes all combinationalpart inputs and outputs accessible


Scan Architectures: Partial Scan Methods

Partial scan

Problem of test time in full scan designs can be alleviated by scanchains that include only part of feedback registersMethod of selecting registers that are put in scan varies from one partialscan method to another

But in general, selection must be done such that combinational testgeneration methods can still be used for test data generation



Figure 43: Partial scan, starting with Huffman model.



Figure 44: Partial scan datapath.



Fig. 43 or 44

We assume combinational part of circuit consists of two combinationalblocksCircuit primary inputs split and go to both blocks, A and B, and outputsof blocks form circuit’s primary outputsPartial scan is possible in this circuit because

One feedback register is driven by block A; output of this register goesto input of block BThe other feedback register is driven by block B; output of this registergoes to block A

To test all logic in this circuit, it is only necessary to put feedbackregister R2 in a scan pathRemoval of R1 from full scan would still qualify resulting circuit modelfor combinational test generation



Test generation for combinational part of circuit of Fig. 43 (or 44) isdone by a circuit model that removes R1, and then unfolds circuit

This combinational model is shown in Fig. 45Since this model does not have any feedback loops, it is treated as acombinational circuit

Figure 45: Partial scancombinational model.

Figure 46: Test vector arrangement.



Partial scan test procedureNbarT = 1 −→ R1 disabledClock R2, shift PPI1 test data into R2, also of previous test seriallycollect PPO1Apply PI1 test data to PI1 input, collect response from PO1NbarT = 0 −→ R1 enabled, clock onceApply PI2 test data to PI2 input, collect response from PO2Clock onceReturn to step 1



Partial scan vs. full scan

Partial scan reduces test time by having fewer bits to shift inOn the other hand, partial scan has a more complex test procedureThe main problem is that there is no unique partial scan method, andnot all circuits can take advantage of a partial scan methodFor finding proper registers to scan, a topological processing of circuit isnecessaryA partial scan method fits well with pipeline architectures

In this case, test procedure becomes dependent on depth of pipeline


Scan Architectures: Multiple Scan Design

Problem of long scan chain can be moderated by using multipleindependent or parallel scan chains

Multiple independent scan chains

Each scan register has its shift, load, and clock controlIf the number of flip-flops in scan chains in a design are not the same,they need independent shift and clock enable control signals

Multiple parallel scan chains

All scan registers are controlled by the same set of signalsIf registers to be scanned can be put into groups of equal number ofcells, they can be regarded as parallel scan registers with the same set ofcontrol signals



Figure 47: Multiple parallel scan chains.Moslem Amiri, Vaclav Prenosil Digital Systems Testing December, 2012 82 / 84


Fig. 47R1 and R2 are put into two separate scan chains with Si1 and Si2 inputsand So1 and So2 outputsRegisters R1 and R2 have the same length

Therefore, scan chains are two parallel registers with the same clock andNbarT control inputs

Multiple scan test procedure (Fig. 47)Input test data consist of PI1, PI2, PPI1, PPI2Test responses consist of PO1, PO2, PPO1, PPO2For testing, NbarT = 1 −→ R1 and R2 are in shift modeIndividual test data bits from corresponding test data segments (PPI1and PPI2) are read and applied simultaneously to Si1 and Si2While shifting-in occurs, previous results are collected from So1 and So2When shifting is complete, NbarT = 0, parallel test data for PI1 andPI2 are applied, and PO1 and PO2 are readClock once, return to step 1

Multiple scan features (compared with full scan)Significantly reduces test timeIts test generation is no different than that for full scanNeeds extra test pins, and for independent scans, extra controls


References

Zainalabedin Navabi, Digital System Test and Testable Design:Using HDL Models and Architectures, Springer, 2010.


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