digital rpt

7/28/2019 Digital Rpt

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AbstractIn this paper, two digital systems are designed with

the help of EDA (Electronic Design Automation) tools. The

design process consists of the HDL coding, synthesis, place and

route and the digital simulations at each stage. Moreover, the

optimization and verification are also essential procedures during

the digital design.

Index TermsHuffman, Simulation, Synthesis, Verilog

I. INTRODUCTIONHE electronic design can be classified into two types:

analog design and digital design [1]. The designs in this

paper are two digital systems.

The design flow of digital system is shown in Fig.1, which

begins from high level description design. Secondly, it is

synthesized. Then the circuit is placed and routed

automatically to signoff finally.

Fig.1 The Procedure of Analog Design

In this paper, two digital systems are designed in the similar

procedure. Firstly, the specifications are created. Secondly, the

behavior of system is described in Verilog and verified with

simulation. Then, the HDL file is synthesized to test again.After then, the EDA software draws the layout. Finally, the

whole design is analyzed and the conclusion is drawn.

II. HUFFMAN ENCODERA. Design Procedure

1) Huffman Coding SchemeHuffman coding is a widely sued encoding method, which

compress size-fixed symbols into variable length symbols

according to their probability [2]. The symbol arises more

frequently has a shorter code and the symbol appears less

times has a longer size of code conversely. Therefore, the

Huffman code can compress the size of data quickly and

effectively.

Firstly, in order to obtain the Huffman code, the probability

of each digit in the unique sequence needs to be calculated.

After calculation, the probabilities of all the digits are listed in

Table.1.TABLE 1

THE PROBABILITY OF ALL THE DIGITS

Digit Appear Times Probability

0 11 8.66%

1 21 16.54%

2 18 14.17%

3 14 11.02%

4 21 16.54%

5 6 4.72%

6 16 12.60%

7 1 0.79%

8 14 11.02%

9 5 3.94%

Secondly, the two least probable digits are assigned the

longest code-words, which are only different in the last one

word [2]. After that, the encoding procedure is repeated until

all the digits have been merged. Fig.2 shows the process of

Huffman encoding.

Fig.2 The Process of Huffman Encoding

DigitalDesign ofHuffman Encoder andSequence Detector

Pengwei Feng, 25706993

T


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Thirdly, the binary Huffman codes are obtained according

to Fig.2, which is 0 when goes left down and 1 when goes

right down. Table.2 has presented all the Huffman codes of

the ten digits. And the compression ratio is given by:

=

!"#$!"!"#$%!"#$"%&"!"#$!"!"#$%&''&( !"#" =

!.!"!#

!= 0.39 (1)

TABLE 2THE HUFFMAN CODE OF DIGITS

Digit Huffman Code

0 001

1 111

2 101

3 011

4 110

5 0001

6 100

7 00000

8 010

9 00001

2) Logic DesignThis design is a Huffman compression circuit for the given

specific sequence. The input interfaces are Clock, Clear and

Serial Bit In. And the output interfaces are M and F, where M

shows the size of used memory and F indicates that the

memory has overflowed. Fig.3 displays the block diagram of

this design.

Fig.3 TheBlock Diagram of Huffman Encoder

At first, the input digits are converted to binary ASCIIcodes and applied to Serial Bit In terminal bit by bit. Secondly,

if the memory has not overflowed, the input bit will be shifted

into an 8-bit Register at each clock edge and the amount of

stored bits will also be recorded by a counter.

Then, the stored data is tested by an Encoder when the

Register has received 8 bits. If this ASCII codes have matched

one of these ten digits, the corresponding Huffman code will

be stored into another 5-bit Register and the length of code

will also be record.

Finally, the stored Huffman code is shifted into Memory bit

by bit at each clock edge if the memory has not overflowed

and the rest room of memory is enough for the coming

Huffman codes. The complete codes are included in Appendix

A.

3) SynthesisWhile the behavior logic design is finished, the HDL

description file is imported into synthesis software, for

instance, Synopsys, to convert that into Register Transfer

Level (RTL) Netlist, which will map generic and logic cellsand optimize the design to meet constraints [3].

During synthesis, a clock with a period of 8ns is defined to

constrain most of the paths [3].

After synthesis, a synthesized RTL file, a SDC file and a

standard delay file (SDF) will be obtained.

4) Place and RouteIn previous stage, the synthesized RTL file in Verilog

format and the SDC file are obtained, which can be used to

place and route automatically in Cadence Encounter.

Moreover, the software can also optimize the time, of which

the report is showed in Fig.4. At this stage, the layout of the

designed circuit is drawn and can be used for fabrication.

At last, the GDS file of layout and its SDF file are generated

and saved for further use.

Fig.4 TheReport of Timing Optimization

B. OptimizationIn the first attempt of design, all the codes was stored into

memory as soon as the data is encoded, which means that the

memory has to shift more than three bits at one clock. It will

need more shift registers and consume more power.

Fig.5 The Area and Power Report

In order to optimize that, a 5-bit register is applied here,

which can save the encoded Huffman code temporary. Then,

the code is shifted into memory one bit each clock. As the data


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is encoded every eight cycles and the longest codes are five

bits, there will be enough cycles for shifting the temporary

code. In this way, the memory just needs to store one bit each

clock. Thus the power consumption is reduced and the design

is optimized.

Fig.5 shows the area and power reports after optimization

during synthesis.

C.

Testing and Verification1) Behavior Simulation

After finishing the Verilog HDL description of Huffman

Encoder, it needs to be tested by simulation to verify whether

its behavior has met the given specifications.

To begin with the behavior simulation, a testbench should

be written at first, which contains the clock signal and the

specific input data. Secondly, Verilog description file of

Huffman Encoder and the testbench are compiled and

simulated in Modelsim. Finally, the corresponding output

signal can be acquired to analysis and verify the behavior of

the system.

In the testbench, the clock cycle is set to be 10ns and the

input data is assumed to be six digits 024579 in ASCII plusan irrelevant ASCII code 11000000. Table.3 has listed all

these input data and the expected output of M according to the

Huffman code in Table.2. The complete codes of testbench are

included in Appendix B.TABLE 3

THE DATA OF TESTBENCH

Clock

CycleSymbol

ASCII

Code

Expected

M

1-8 0 00110000 3

9-16 2 00110010 6

17-24 4 00110100 9

25-32 5 00110101 1333-40 7 00110111 18

41-48 9 00111001 23

49-56 A 11000000 23

56- -- -- 23

Fig.6 The Waves of Behavior Simulation

Fig. 6 shows the wave plots after behavior simulation.

Firstly, It can be seen from Fig.6 (1) that the size of M is

updated every eight-clock cycle, which is due to the 8-bit

register talked in previous stage. Secondly, Fig.6 (2) shows

that the data stored in M changes from 0 to 3, then 6, then 9,

then 13, then 18 and keeps 23 in the rest clock cycles, which is

the same with the assumption in Table.3.

In addition, in order to test the behavior of F, the initial

value of F is set to be 65530 and the simulation is run again.Then it will overflow after received two 3-bit Huffman codes,

which is shown in Fig.6 (3).

2) Post-synthesis SimulationAfter synthesis, the simulation is repeated again at gate

level, which has taken the delay of gates into consideration

this time.

To perform that, import the synthesized Verilog file, SDF

file and the same testbench into Modelsim.

Fig.7 shows the result of simulation. It can be seen from

Fig.7 (1) that the plot is almost the same with behavior

simulation. However, there is a slight delay of 1.032ns in the

output this time, which is shown in Fig.7 (2). In addition,

some violating states also exist between two states of M in

Fig.7 (3). However, they only last for a few picoseconds,

which can be ignored compared with the period of clock.

Fig.7 The Waves of Post-synthesis Simulation

3) Post-layout SimulationAfter layout, the simulation is repeated again, which has

Fig.8 The Waves of Post-layout Simulation


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taken the delay of real components and connecting wires into

consideration this time.

To perform that, import the netlist file of layout, SDF file

and the same testbench into Modelsim.

Fig.8 displays the result of simulation. It shows that the

wave is generally the same with post-synthesis simulation,

which also have the violating states in Fig8 (3). However, the

delay in output has increased to 2.776ns after place and route.

III. SEQUENCE DETECTORA. Design Procedure

1) Specific SequenceThe second design is a sequence detector which can detect

and match the first 80 digits of the given sequence. This

sequence needs to be matched is shown in Fig.9. All the

overloop conditions of the sequence are marked. Specifically,

the underlined numbers are the 2-bit overloop situations and

the circled numbers are the 3-bit overloop situations

respectively, which will be taken into consideration when

design the logic behavior in the next step.

Fig.9 The Given Sequence

2)Logic DesignThe input interfaces of this sequence detector are Clock,

Reset and Serial Data In. And the output interfaces are Digit

Match and Sequence Match, where Digit Match is kept for one

cycle to indicate that one digit has been matched and

Sequence Match is high for one cycle to shows that al the

sequence has been matched. Fig.10 shows the block diagram

of this design.

Fig.10 TheBlock Diagram of Sequence Detector

At first, the input digits are converted to binary ASCII

codes and applied to Serial Data In terminal bit by bit.

Secondly, the input bit will be shifted into an 8-bit Register at

each clock edge and the amount of stored bits will also be

recorded by a counter.

Then, the State Machine will run when the Register has

received 8 bits and transfer the output into Output Controller

to indicate the value of final outputs. The states transition ofState Machine is displayed in Fig.11.

Fig.11 The Transition of State Machine

Moreover, the Output Controller is also controlled by the

counter of Register, which will set all the output to zero if the

counter has not reach eight. Therefore, Digit Match and

Sequence Match are kept for only one clock cycle if digits are

matched. The complete codes are included in Appendix A.

3) Synthesis & Place and RouteWhen the behavior logic design is finished, the Verilog

description file is synthesized and routed as same as in the first

design. In addition, the report of timing optimization isshowed in Fig.12.

Fig.12 TheReport of Timing Optimization

B. OptimizationIn the first attempt of design, all the value of outputs was

assigned between the states. Thus, the State Machine will be

more complex while it not only processes the transition of

state but also the value of output. Moreover, the outputs from

S1 to S79 have never changed. Thus, assigning them again

and again in the State Machine will also consume some

necessary power [4].

In order to optimize that, an Output Controller is attached,

which controls the value of output according to the State

Machine. It only has three states: S0 (Digit Match is 0 and

Sequence Match is 0), S80 (Digit Match is 1 and Sequence


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Match is 1), and the default state (Digit Match is 1 and

Sequence Match is 0). Thus, it has reduced the number of

unnecessary changes in output. Therefore, the consumption of

power is reduced finally [4].

Fig.13 shows the area and power reports after optimization

during synthesis.

Fig.13 The Area and Power Report

C. Testing and Verification1) Behavior Simulation

In order to verify the behavior of the designed Sequence

Detector, it needs to be tested by simulation.

Firstly, a specific testbench needs to be designed to start the

behavior simulation. It provides the specific input sequence

data and clock signal to the tested module. Secondly, Verilog

description file of Sequence Detector and the testbench are

compiled and simulated in Modelsim. Finally, the

corresponding output signal can be obtained to analysis and

verify the behavior of the design.

In the testbench, the clock cycle is set to be 10ns and the

input data is assumed to begin with the ASCII codes of

11345, then that of the given 80 digits and end with that of

24597. Table.4 has listed all these input data and the

expected output of Digit Match and Sequence Match. The

complete codes of testbench are included in Appendix B.

TABLE 4

THE DATA OF TESTBENCH

Clock

CycleDigits

Expected

D-Match

Expected

S-Match

1-40 11345 0 0

41- 0 1 0

: : : 0: given digits 1 0

: : : 0

-700 3 1 1

701-720 24597 0 0

Fig. 14 displayss the wave plots after behavior simulation.

Firstly, It can be seen from Fig.14 (1) that the output of Digit

Match keeps high for one clock cycle after each eight clocks

when the circuit start to receive the 80 digits. Secondly, Fig.14

(2) shows that after matching all the digits in given sequence,

the output of Sequence Match becomes high and then low

after one clock cycle, which is the same with the assumption

in Table.4.

Fig.14 The Waves of Behavior Simulation

2) Post-synthesis SimulationSimilarly to part I, the behavior simulation of Sequence

Detector is repeated again at gate level after synthesis. It can

simulate the delay of gates at practice.

To begin with, the synthesized Verilog file and the same

testbench was compiled and imported into Modelsim. In

addition, the SDF file also needs to be included in the

simulation.

Fig.15 shows the result of post-synthesis simulation. Fig.15

(1) indicates that the plots are almost the same with behavior

simulation in Fig.14 (1). However, there is a little delay of

0.486ns in the output of both Digit Match and Sequence

Match this time, which is shown in Fig.15 (2).

Fig.15 The Waves of Post-synthesis Simulation

3) Post-layout SimulationAfter layout, the simulation is repeated again, which will

simulate the delay between all the cells and connecting wires.

To perform that, import the netlist file of layout, SDF file

and the same testbench into Modelsim again.


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Fig.16 (1) shows the waves after simulation. It indicates that

the output plots are the same with that of post-synthesis

simulation practically. However, the delay in output terminals

has increased to 2.388ns after place and route in Fig.16 (2).

Fig.16 The Waves of Post-layout Simulation

IV. CONCLUSIONIn this assignment, two digital systems are designed, tested

and verified by pre-synthesis, post-synthesis and post-layout

simulation. Finally, all the outputs have met the given

specifications.

However, there are still some outstanding problems in these

designs. Firstly, in the Huffman Encoder, the complete codes

will be stored into memory three to five clock cycles later after

the data is encoded. It means that the memory cannot be used

and read immediately when the data is encoded. Secondly, the

Sequence Detector has eighty one states, which is so many

that needs to be improved with state minimization in thefuture.

During these practices of design, we have learnt the design

flow of digital design, how to describe the behavior of a

system using HDL, and how to transfer that into RTL file and

layout, which can be used for further fabrication.

In the future, we need to get to know more about the

principles of synthesis, which can helps to describe and model

the behavior of a system more effective and minimize the

consumption of power as well.

APPENDIX A

1) Huffman Encoder

modulehuffman (F, M, Clock, Clear, Serial_Bit_In);

input Clock, Clear, Serial_Bit_In;

output F;

output [15:0] M;

reg F;

reg [15:0] M;

reg [65534:0] memory;

reg [7:0] Data_8bit;

reg [2:0] count;

reg [4:0] Code;

reg [2:0] Length;

//************** 8 bit data register ****************//

always @(posedge Clockornegedge Clear)

begin

if(!Clear)

begin

count


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Code[2:0]


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s1: begin

if (Data_8bit == 8'b00110001) //1

next_state = s2;

else if (Data_8bit == 8'b00110000)

next_state = s1;

else next_state = s0;

end

s2: begin

if (Data_8bit == 8'b00110001) //1

next_state = s3;


next_state = s1; //if '0' is in, it means the first digit is matched

else next_state = s0; //else, no digit has been matched

end

s3: begin

if (Data_8bit == 8'b00110011) //3

next_state = s4;


next_state = s1;


end

s4: begin

if (Data_8bit == 8'b00110001) //1

next_state = s5;


next_state = s1;


end

s5: begin

if (Data_8bit == 8'b00110001) //1

next_state = s6;


next_state = s1;


end

s6: begin

if (Data_8bit == 8'b00110100) //4

next_state = s7;


next_state = s1;


end

s7: begin

if (Data_8bit == 8'b00110111) //7

next_state = s8;


next_state = s1;


end

s8: begin

if (Data_8bit == 8'b00110100) //4

next_state = s9;


next_state = s1;


end

s9: begin

if (Data_8bit == 8'b00110010) //2

next_state = s10;else if (Data_8bit == 8'b00110000)

next_state = s1;


end

s10: begin

if (Data_8bit == 8'b00111000) //8

next_state = s11;


next_state = s1;


end

s11: begin

if (Data_8bit == 8'b00110100) //4

next_state = s12;


next_state = s1;


end

s12: begin

if (Data_8bit == 8'b00110000) //0

next_state = s13;


end

s13: begin

if (Data_8bit == 8'b00110001) //1

next_state = s14;


next_state = s1;


end

s14: begin

if (Data_8bit == 8'b00110000) //0

next_state = s15;

else if (Data_8bit == 8'b00110001) //overloop '011'

next_state = s3;


end

s15: begin

if (Data_8bit == 8'b00111001) //9

next_state = s16;


next_state = s2;


next_state = s1;


end

s16: begin

if (Data_8bit == 8'b00110000) //0

next_state = s17;


end

s17: begin

if (Data_8bit == 8'b00110001) //1

next_state = s18;


next_state = s1;


end

s18: begin

if (Data_8bit == 8'b00111000) //8

next_state = s19;


next_state = s3;


next_state = s1;


end

s19: begin

if (Data_8bit == 8'b00110001) //1

next_state = s20;

else if (Data_8bit == 8'b00110000)next_state = s1;


end

s20: begin

if (Data_8bit == 8'b00110110) //6

next_state = s21;


next_state = s1;


end

s21: begin

if (Data_8bit == 8'b00111000) //8


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next_state = s22;


next_state = s1;


end

s22: begin

if (Data_8bit == 8'b00110010) //2

next_state = s23;


next_state = s1;


end

s23: begin

if (Data_8bit == 8'b00111000) //8

next_state = s24;


next_state = s1;


end

s24: begin

if (Data_8bit == 8'b00110001) //1

next_state = s25;


next_state = s1;


end

s25: begin

if (Data_8bit == 8'b00110010) //2

next_state = s26;


next_state = s1;


end

s26: begin

if (Data_8bit == 8'b00110001) //1

next_state = s27;


next_state = s1;


end

s27: begin

if (Data_8bit == 8'b00110110) //6

next_state = s28;


next_state = s1;


end

s28: begin

if (Data_8bit == 8'b00110011) //3

next_state = s29;


next_state = s1;


end

s29: begin

if (Data_8bit == 8'b00110010) //2

next_state = s30;


next_state = s1;else next_state = s0;

end

s30: begin

if (Data_8bit == 8'b00110100) //4

next_state = s31;


next_state = s1;


end

s31: begin

if (Data_8bit == 8'b00110001) //1

next_state = s32;


next_state = s1;


end

s32: begin

if (Data_8bit == 8'b00110011) //3

next_state = s33;


next_state = s1;


end

s33: begin

if (Data_8bit == 8'b00110100) //4

next_state = s34;


next_state = s1;


end

s34: begin

if (Data_8bit == 8'b00110001) //1

next_state = s35;


next_state = s1;


end

s35: begin

if (Data_8bit == 8'b00110110) //6

next_state = s36;


next_state = s1;


end

s36: begin

if (Data_8bit == 8'b00110010) //2

next_state = s37;


next_state = s1;


end

s37: begin

if (Data_8bit == 8'b00110001) //1

next_state = s38;


next_state = s1;


end

s38: begin

if (Data_8bit == 8'b00110000) //0

next_state = s39;


end

s39: begin

if (Data_8bit == 8'b00110110) //6

next_state = s40;


next_state = s2;


next_state = s1;

else next_state = s0;end

s40: begin

if (Data_8bit == 8'b00110010) //2

next_state = s41;


next_state = s1;


end

s41: begin

if (Data_8bit == 8'b00110110) //6

next_state = s42;



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next_state = s1;


end

s42: begin

if (Data_8bit == 8'b00110001) //1

next_state = s43;


next_state = s1;


end

s43: begin

if (Data_8bit == 8'b00111001) //9

next_state = s44;


next_state = s1;


end

s44: begin

if (Data_8bit == 8'b00111000) //8

next_state = s45;


next_state = s1;


end

s45: begin

if (Data_8bit == 8'b00110010) //2

next_state = s46;


next_state = s1;


end

s46: begin

if (Data_8bit == 8'b00110110) //6

next_state = s47;


next_state = s1;


end

s47: begin

if (Data_8bit == 8'b00110011) //3

next_state = s48;


next_state = s1;


end

s48: begin

if (Data_8bit == 8'b00110100) //4

next_state = s49;


next_state = s1;


end

s49: begin

if (Data_8bit == 8'b00110001) //1

next_state = s50;


next_state = s1;


end

s50: begin

if (Data_8bit == 8'b00110010) //2

next_state = s51;


next_state = s1;


end

s51: begin

if (Data_8bit == 8'b00110010) //2

next_state = s52;


next_state = s1;


end

s52: begin

if (Data_8bit == 8'b00110100) //4

next_state = s53;


next_state = s1;


end

s53: begin

if (Data_8bit == 8'b00110011) //3

next_state = s54;


next_state = s1;


end

s54: begin

if (Data_8bit == 8'b00110110) //6

next_state = s55;


next_state = s1;


end

s55: begin

if (Data_8bit == 8'b00110010) //2

next_state = s56;


next_state = s1;


end

s56: begin

if (Data_8bit == 8'b00110100) //4

next_state = s57;


next_state = s1;


end

s57: begin

if (Data_8bit == 8'b00111001) //9

next_state = s58;


next_state = s1;


end

s58: begin

if (Data_8bit == 8'b00110010) //2

next_state = s59;


next_state = s1;


end

s59: begin

if (Data_8bit == 8'b00110000) //0

next_state = s60;


end

s60: begin

if (Data_8bit == 8'b00110011) //3next_state = s61;


next_state = s2;


next_state = s1;


end

s61: begin

if (Data_8bit == 8'b00110101) //5

next_state = s62;


next_state = s1;



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end

s62: begin

if (Data_8bit == 8'b00110001) //1

next_state = s63;


next_state = s1;


end

s63: begin

if (Data_8bit == 8'b00111000) //8

next_state = s64;


next_state = s1;


end

s64: begin

if (Data_8bit == 8'b00110001) //1

next_state = s65;


next_state = s1;


end

s65: begin

if (Data_8bit == 8'b00110100) //4

next_state = s66;


next_state = s1;


end

s66: begin

if (Data_8bit == 8'b00110001) //1

next_state = s67;


next_state = s1;


end

s67: begin

if (Data_8bit == 8'b00110110) //6

next_state = s68;


next_state = s1;


end

s68: begin

if (Data_8bit == 8'b00110001) //1

next_state = s69;


next_state = s1;


end

s69: begin

if (Data_8bit == 8'b00111001) //9

next_state = s70;


next_state = s1;


end

s70: beginif (Data_8bit == 8'b00110011) //3

next_state = s71;


next_state = s1;


end

s71: begin

if (Data_8bit == 8'b00110110) //6

next_state = s72;


next_state = s1;


end

s72: begin

if (Data_8bit == 8'b00110001) //1

next_state = s73;


next_state = s1;


end

s73: begin

if (Data_8bit == 8'b00110001) //1

next_state = s74;


next_state = s1;


end

s74: begin

if (Data_8bit == 8'b00110100) //4

next_state = s75;


next_state = s1;


end

s75: begin

if (Data_8bit == 8'b00110010) //2

next_state = s76;


next_state = s1;


end

s76: begin

if (Data_8bit == 8'b00110100) //4

next_state = s77;


next_state = s1;


end

s77: begin

if (Data_8bit == 8'b00110101) //5

next_state = s78;


next_state = s1;


end

s78: begin

if (Data_8bit == 8'b00110000) //0

next_state = s79;


end

s79: begin

if (Data_8bit == 8'b00110011) //3

next_state = s80;


next_state = s2;


next_state = s1;


end

s80: begin

if (Data_8bit == 8'b00110000) //new sequence start from '0'next_state = s1;


end

default: next_state = s0;

endcase

end

end

//************************* end *******************************//

//************* Sequential Block_3 : Output *************//

always @(posedge Clockor negedge Reset)

begin

if(!Reset)

begin


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12

Sequence_Match

digital rpt

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