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Digital Quantum Computing based on

Superconducting Electronics

O. Mukhanov Seeqc, Inc., Elmsford, NY

NY CREATES Seminar (online)

2020-May-20

Outline of Presentation

MotivationSuperconducting SFQ TechnologyDigital Quantum Computing System Initial resultsConclusions

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Quantum Computing TodayGoogle 53-qubit “Sycamore” Quantum Supremacy setup

From ICQT conf. July 2019 By Erik Lucero, Google | Wired, Dec. 2018

ENIAC (1946, University of Pennsylvania)

How this installation transformed to modern computers?

Qubit Control: current microwave based approach

Large, expensive electronics racks distant from qubits

Analog qubit control:- Complex- High latency- Noisy- Expensive- Large I/O count- Non-scalable

Microwave equipment

Just Qubit Ctrl; Not including I/0 for readout and tunable coupler*Google quantum supremacy chip: C. Neill et. al., Science 360, 6385, 195-199 (2018)

Qubit Control Wiring Overhead

Rent’s Rule should be used for Quantum Circuits

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Qubitcount

Using µwaves*

Large I/O Count = scalability problem. Long Wires = latency problem

Additional system integration considerations: Cost: current cost of a cable channel from room

temperature to milliKelvin stage is ~ $5,000 (per Oxford Instruments). Typically ~2-3.5 cables on average per

superconducting qubit (transmon) ~ > $10-11M cable cost for a 1000 qubit

system. Most expensive cables are between 4K to 20 mK stages

Reliability of a few hundred-channel cabling farm of a dilution refrigerator system is likely be not sustainable.

Options for co-located cryogenic classical circuits CryoCMOS Can work in cryogenics, but still dissipates relatively large power Best fit is for semiconductor spin qubits (Microsoft, Intel, EPFL). Google, Microsoft, Intel teams developed mixed-signal circuits for superconducting

and spin qubits (ISSCC’19, IEDM’19, ISSCC’20). General approach: recreating room temperature electronics with cryoCMOS.

Superconductor electronics Advantage: very low-power, very fast electronics based on Single Flux Quantum

(SFQ) logic.

Problem: much lower integration density than CMOS• Recreating microwave electronics (AWG, etc.) with SFQ logic is a complex task

(will require too much hardware). The result may not be competitive.

Is there a competitive SFQ-based approach?

SFQ Pulse: Low Energy Quantized-area pulse

• SFQ pulse width: tSFQ ~ Φ0/2IcR where 2IcR - pulse height

• High Speed: for Nb junctions, ultimate limit tSFQ → 0.4 ps; for complex RSFQ circuits, practical fclock ~ 1/(10 tSFQ)

• Low Power: SFQ pulse energy ~ ¾ Φ0Ic ~ 2 x10-19 Joule (for Ic ~ 100 µA for 4K operation) or ~2x10-20 -21 Joule (for Ic ~ 1-10 µA for 20K operation)

Maximum Clock Frequency for IC can reach ~100s GHz at low power

2IcRtSFQ

V

t

∫ Φ= 0VdtQuantized area Single Flux Quantum (SFQ) pulse generated by overdamped Josephson junction

RSFQ Technology - productized

∫Vdt = Φ0 = h/2e = 2.07 mV·ps

Both Data and Clock are SFQ voltage pulses V(t) with quantized areas

RSFQ - Rapid Single Flux Quantum(invented in mid-80s*, adopted to Hypres since early 90s, became the

main digital superconducting electronics world-wide by mid-90s)

750 GHz digital frequency divider internal memory gate-level pipelining high-throughput low switching power dc bias only local timing amendable for synchronous and asynchronous schemes

@4K, ESFQ= 10-19J@20 mK, ESFQ= 10-21J

* O. A. Mukhanov, V. K. Semenov, and K. K. Likharev, “Ultimate performance of the RSFQ logic circuits," IEEE Trans. Magn., MAG-23, pp. 759-762, Mar. 1987.

The 1st real (commercial-grade) application of digital superconducting electronics

DSP-Decimation FilterADC modulator

30 GS/s X-band Rx chip

Sumitomocryocooler

compressor

vacuum enclosurewith LTS chipand HTS filters mounted inside

output amplifiers

current source

temperaturecontroller

data acquisition and processing board (FPGA)

2005-2007

Low-pass Rx chip

HYPRES’ RSFQ Digital-RF Receiver

circa 2010

O. A. Mukhanov, D. Kirichenko, I. V. Vernik, T. V. Filippov, A. Kirichenko, R. Webber, V. Dotsenko, A. Talalaevskii, J. C. Tang, A. Sahu, P. Shevchenko, R. Miller, S. B. Kaplan, S. Sarwana, and D. Gupta, “Superconductor Digital-RF receiver systems,” IEICE Trans. Electron., vol. E91-C, pp. 306-317, Mar. 2008.

D. Gupta et al., "Modular, Multi-Function Digital-RF Receiver Systems," in IEEE Transactions on Applied Superconductivity, vol. 21, pp. 883-890, 2011.

Circa 2005

Energy-Efficient Successors of RSFQ Logic

Several post-RSFQ logics (ERSFQ, eSFQ , RQL, AQFP) were introduced ERSFQ and eSFQ achieve the fundamental SFQ energy dissipation related to magnetic

flux crossing Josephson junction ESFQ ~ IbiasΦ0 ~ 10-19 Joule Eliminates static dissipation from bias resistors (dominating dissipation) Retains all advantages of conventional RSFQ:

dc-powered, amendable for serial biasing to reduce total dc bias current ballistic interconnects (no extra power for integrate connections) high speed operation (can work at 100s of GHz) largely preserves already developed cell libraries

Icb = Ib

Vb = Φ0⋅ƒclk

Lb

Conventional RSFQ Energy-Efficient RSFQ (ERSFQ)

PS= Ib Vb

PD= Ib Φ0 PD= Ib Φ0

PS= 0

Ic

Ib ~ ¾ Ic

Vb

Rb

Ic

SFQ SFQ

Power Dissipation in ERSFQ/eSFQ

ERSFQcircuit

Ib VbVI

000

)()()( Φ⋅=⋅⋅=⋅⋅= ∫∫ b

T

b

T

IdttVIdttVtIE

Dissipated energy per one clock period:

Total power dissipation:

P = fclk⋅ Ib⋅Φ0

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It is difficult to improve this system

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We want to redesign it with this:

Digital Quantum Computer

cryostat configuration

O. Mukhanov et al., "Scalable Quantum Computing Infrastructure Based on Superconducting Electronics," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2019

Resonant Excitation of Qubits by SFQ pulses

Feasibility proven by Wisconsin and Syracuse University groups

By varying distance between SFQ pulses in the train using control theory, one can achieve higher fidelities as shown by Saarland Univ. team

R. McDermott, M. G. Vavilov, B. L. T. Plourde, F. K. Wilhelm, P. J. Liebermann, O. A. Mukhanov, T. A. Ohki, “Quantum-classical interface based on single flux quantum digital logic,” Quantum Sci. Technol., 2018

Replacing microwaves with digital SFQ pulse train

R. McDermott and M. G. Vavilov, “Accurate Qubit Control with Single Flux Quantum Pulses,” Phys. Rev. Appl. 2, 014007 (2014)

By varying distance between SFQ pulses in the train using control theory, one can achieve higher fidelities as shown by Saarland Univ. team

Recent theoretical advance shows that achieving >99.99% fidelities is doable with low SFQ hardware complexity (55 bit shift register with 25 GHz clock) K. Li, R. McDermott, M. Vavilov, ”Scalable Hardware-Efficient Qubit

Control with Single Flux Quantum Pulse Sequences,” arXiv:1902.02911 [quant-ph]

R. McDermott, M. G. Vavilov, B. L. T. Plourde, F. K. Wilhelm, P. J. Liebermann, O. A. Mukhanov, T. A. Ohki, “Quantum-classical interface based on single flux quantum digital logic,” Quantum Sci. Technol., 2018

Improving Fidelity by using Optimal Control

Pulse Generation Unit (PGU)

Using superconducting SFQuClass circuits

100 µm

100 µm

Single Flux Quantum Classical circuits fit for a proximal location to qubits

SFQuClassTM circuit technology: • Energy-efficient ERSFQ or eSFQ

varieties of RSFQ logic• rescaling JJ critical currents to

<10µA (~10-20 J per switching).• use of high-kinetic inductors.• qubit-aware SFQ circuit layout

SFQ pulser generating SFQ pulse at each cycle of input sinewave clock

Fragment of PGU for storing and generating the optimal SFQ pulse pattern at 25 GHz clock

Fabricated with SeeQC 1000 A/cm2 critical current density process and a unit Josephson junction critical

current scaled down to 10 mA from 125 mA typical for the SFQ circuits designed for operation at 4 K.

qMCM = qubit chip + SFQ controller chip

SFQ Control Chip(made in SeeQC)

2-transmon chip (made in Syracuse U.)

Assembled at SeeQC multichip module (qMCM) mounted in dilution fridge at Syracuse U.Wisconsin-Syracuse-SeeQC Project

728_ABMCM16_SFQfon8_RabiWidth_vs_SFQpower

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

RabiWidth ( s)

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SFQ

Pow

er (d

B)

Qubit shows clear thresholding behavior in Rabi oscillation experiments when the SFQ circuit dc current bias and trigger power are varied proving the SFQ qubit control action

724_ABMCM16_SFQfon8_RabiWidth_vs_switchbias

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

RabiWidth ( s)

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0.45

Switc

h Bi

as (V

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Courtesy of Britton PlourdeMeasured at Syracuse University

Digital SFQ Control of Qubit

Triggering the SFQ driver near ω01/8 results in clear Rabi chevrons – direct evidence of qubit coherent behavior

Courtesy of Britton Plourde

Measured at Syracuse University

Initial Testing: Digital SFQ Control

SFQ**

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Not including I/0 for readout and tunable coupler – only qubit control *Google quantum supremacy chip: C. Neill et. al., Science 360, 6385, 195-199 (2018)

Qubitcount

Getting close to microprocessor-like Rent’s rule exponentRent’s Rule for Quantum Circuits

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µwaves***Wires from 4K to 20mK classical SFQ chip (classical-to-classical non-coaxial cabling only)

No wires to Quantum Chip (capacitive and magnetic coupling only)

Seeqc (Digital) Conventional (Analog) Google (analog) Microsoft (mixed signal) Intel (mixed signal)

Technology SFQ and SFQuClass CMOS (at room temp) CryoCMOS (3K)[ISSCC2019]

CryoCMOS (20mK)[IEDM2019]

CryoCMOS (3K)[ISSCC2020]

Ctrl Signal Digital pulses pattern Analog microwave waveforms

Analog microwave waveforms

Analog waveforms Analog waveforms

Readout Digital to mK Analog to RT Analog to RT Analog to RT Analog to RT

Qubit type Superconducting qubits Superconducting qubits Superconducting qubits Spin-qubits, Majorana qubit (goal) Spin qubits, transmon (potential)

Clock speed 20 – 40 GHz 0.3 – 2 GHz 0.3 GHz 0.1GHz 1 GHz

Power (for Ctrl) 0.0002 mW/qubit 20 mW/qubit 2 mW (potential) 0.2 mW 1.7 mW/qubit (analog part) + 300 mW (digital part)

Heat from cables(limit for available DRs)

Limits to 1M-100M qubits

Limits to 100-150 qubits (360 qubits optimistically)

? 0.1M (without accounting for readout)

?

Interference Low High High Moderate Moderate

Latency(interconnect delay)Latency (readout/control cycle)

Picosecond scaleTens nanoseconds

Subnanosecond scale (or ~100,000x longer)

Milliseconds (or ~100,000x longer).Readout is still conventional

Milliseconds (or ~100,000x longer)Readout is still conventional

Milliseconds (or ~100,000x longer)Readout is still conventional

Rapid Loop Possible Not Possible Not Possible Not Possible Not Possible

Cost $100/qubit for up to 50 qubit processor <$10/qubit for > 50 qubit processor

$40,000/qubit (liner scale)

$4,000/qubit (liner scale)(guess)

$1,000/qubit (guess) $3,000/qubit(guess)

Qubit Readout/Control: Analog vs Digital

Large, expensive electronics racks distant from qubits

Small, low-cost cryogenic chips in close proximity to qubits

5 mm

Analog qubit control:- Complex- High latency- Noisy- Expensive- Large I/O count- Non-scalable

Digital qubit control:- Naturally integrated- Low latency- Less noise- Low cost- Reduced I/O scaling law- Scalable

Not to scale

Conventional: Microwave based

New: Digital SFQ based

SFQ digital circuits SFQ pulse train

Microwave equipment

R. McDermott et al., “Quantum-classical interface based on single flux quantum digital logic,” Quantum Sci. Technol., 3 (2), 024004, 2018O. Mukhanov et al., "Scalable Quantum Computing Infrastructure Based on Superconducting Electronics," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2019

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SFQuClass Digital Quantum Management (DQM) system-on-a-chip to scale a quantum computer

Proximally co-located and integrated with qubit chips in a cryo-cooled environment to maximize digital control:

o Controls and reads out qubits with digital pulses instead of microwaves

o Increases system speed and reduces latency

o Dramatic cost reduction

o Reduces environmentally induced error

o Reduces energy dissipation and heat/noise brought in via analog systems

o Reduces system complexity

o Designed to work with all superconducting qubits

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Hybrid classical-quantum computers

We are building the industry’s first truly hybrid quantum-classical computing system with an integrated SFQ digital quantum management co-processor supported by superconductive classical logic

o Co-located in the same cryogenic system as quantum and SFQuClass DQM layers

o Provide 10-40 GHz speed classical processing resources in support of quantum-classical algorithms and error correction

o Manages digital readout and control of quantum layer

o Seeqc classical computing layer enables industry leading fast hybrid quantum-classical software

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Application-specific quantum computers

We are building a computing platform that is

commercially scalable for targeted problem-specific

applications

o Reduce system resources required to solve high-value problems

o Increase quantum computer performance for given number of qubits

o Quantum hardware and software are tightly co-designed

ConclusionsSFQ-enabled Digital Quantum Computer Drastic Reduction of I/O count (similar Rent’s rule as

for modern CMOS microprocessors) Close proximity = low latency Advantage for algorithms and for Quantum Error

Correction

Cryogenically co-located classical processors/memoryQuantum (and quantum-classical) algorithms matched to

the hardware

more information at seeqc.com