digital principles and system design

Download Digital Principles and System Design

Post on 17-Oct-2015

323 views

Category:

Documents

0 download

Embed Size (px)

DESCRIPTION

Digital Principles and System Design

TRANSCRIPT

  • SARDAR RAJA COLLEGE OF ENGINEERINGALANGULAM

    DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

    MICRO LESSON PLAN

    SUBJECT NAME : DIGITAL PRINCIPLES AND SYSTEM DESIGN

    SUBJECT CODE : CS 2202

    SEMESTER : III

    YEAR : II

    STAFF NAME

    KALIMUTHU V

    AP/ECE DEPTE-MAILID:v.kalimuthuamutha@gmail.com

  • SUBJECT DESCRIPTION

    CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C

    (Common to CSE & IT) 3 1 0 4

    AIM:

    To provide an in-depth knowledge of the design of digital circuits and the use ofHardware Description Language in digital system design.

    OBJECTIVES:

    To understand different methods used for the simplification of Boolean functions To design and implement combinational circuits To design and implement synchronous sequential circuits To design and implement asynchronous sequential circuits To study the fundamentals of VHDL / Verilog HDL

    TEXT BOOKS

    1. M.Morris Mano, Digital Design, 3rd edition, Pearson Education, 2007.

    REFERENCES

    1. Charles H.Roth, Jr. Fundamentals of Logic Design, 4th Edition, Jaico Publishing

    House, Cengage Earning, 5th ed, 2005.

    2. Donald D.Givone, Digital Principles and Design, Tata McGraw-Hill, 2007.

  • CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C

    (Common to CSE & IT) 3 1 0 4

    UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 8

    Review of binary number systems - Binary arithmetic Binary codes Boolean algebra

    and theorems - Boolean functions Simplifications of Boolean functions using Karnaugh

    map and tabulation methods Implementation of Boolean functions using logic gates.

    UNIT II COMBINATIONAL LOGIC 9

    Combinational circuits Analysis and design procedures - Circuits for arithmetic

    operations - Code conversion Introduction to Hardware Description Language (HDL)

    UNIT III DESIGN WITH MSI DEVICES 8

    Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable

    logic - HDL for combinational circuits

    UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC 10

    Sequential circuits Flip flops Analysis and design procedures - State reduction and

    state assignment - Shift registers Counters HDL for Sequential Circuits.

    UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC 10

    Analysis and design of asynchronous sequential circuits - Reduction of state and flow

    tables Race-free state assignment Hazards. ASM Chart.

    TUTORIAL= 15 TOTAL : 60 PERIODS

    TEXT BOOKS

    1. M.Morris Mano, Digital Design, 3rd edition, Pearson Education, 2007.

    REFERENCES

    1. Charles H.Roth, Jr. Fundamentals of Logic Design, 4th Edition, Jaico Publishing

    House, Cengage Earning, 5th ed, 2005.

    2. Donald D.Givone, Digital Principles and Design, Tata McGraw-Hill, 2007.

  • HOURS WEEKNO TOPICST/ R

    BOOKNO

    PAGE NOA/ V

    CLASS

    UNIT I BOOLEAN ALGEBRA AND LOGIC GATES

    01

    I

    Review of binary number systems T1 1-802 Binary arithmetic T1 8-1503 Binary codes T1 15-31

    04 Boolean algebraand theorems T1 31-34

    05

    II

    Boolean functions T1 40-60

    06Simplifications of Boolean functionsusing Karnaugh map and tabulationmethods

    T1 63-80

    07 Implementation of Boolean functionsusing logic gates T1 80-112 yes08 III09 Tutorial

    UNIT II COMBINATIONAL LOGIC

    10

    IVCombinational circuits T1 121-122 yes11

    12 Combinational circuits Analysis T1 122-1241314

    V

    design procedures T1 124-12715 Circuits for arithmetic

    operations T1 128-1421617 Code conversion T1 142-154 Yes18

    VI19Introduction to Hardware DescriptionLanguage (HDL) T1 112-117

    20 Tutorial21

    UNIT III DESIGN WITH MSI DEVICES

    22

    VIIDecoders T1 142-14623

    24 encoders T1 146-1482526 Multiplexers and demultiplexers T1 148-154 yes27

    VIII28 Memory and programmable

    logic T1 268-29730

    31

    HDL for combinational circuits T1 154-16732IX

    33

  • 34 IX Tutorial35

    UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC

    36

    XSequential circuits T1 172-177 yes37

    38 Flip flops T1 177-1843940 Analysis and design procedures T1 184-20141

    XI42

    State reduction andstate assignment T1 201-213

    43444546 XII Shift registers T1 223-2474748

    XIII49 Counters T1 248-2635051

    HDL for Sequential Circuits. T1258-

    263,333-344

    5253

    XIV5455 Tutorial T156

    UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC

    57

    XV

    Analysis and design of asynchronoussequential circuits T1 351-371 yes

    58 Reduction of state and flowtables T1 371-37759

    6061

    XVI

    Race-free state assignment T1 377-3826263 Hazards T1 382-38764

    ASM Chart R1 565-387656667 Tutorial

    Note:

    T1- M.Morris Mano, Digital Design, 3rd edition, Pearson Education, 2007.

    R1- Charles H.Roth, Jr. Fundamentals of Logic Design, 4th Edition, Jaico Publishing

    House, Cengage Earning, 5th ed, 2005.

  • QUESTION BANK

    UNIT I

    BOOLEAN ALGEBRA AND LOGIC GATES

    PART A (2 Marks)

    1.Define the term digital.

    2.What is meant by bit?

    3.What is the best example of digital system?

    4.Define byte?

    5.List the number systems?

    6.State the sequence of operator precedence in Boolean expression?

    7.What is the abbreviation of ASCII and EBCDIC code?

    8.What are the universal gates?

    9.What are the different types of number complements?

    10.Why complementing a number representation is needed?

    11.How to represent a positive and negative sign in computers?

    12.What is meant by Map method?

    13.What is meant by two variable map?

    14.What is meant by three variable map?

    15.Which gate is equal to AND-inverter Gate?

    16.Which gate is equal to OR-inverter Gate?

    17.Bubbled OR gate is equal to--------------

    18. Bubbled AND gate is equal to--------------

    19.What is the use of Dont care conditions?

    20.Express the function f(x, y, z)=1 in the sum of minterms and a product of maxterms?

    21.What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate?

  • 22.What are the methods adopted to reduce Boolean function?

    23.Why we go in for tabulation method?

    24.State the limitations of karnaugh map.

    25.What is tabulation method?

    26.What are prime-implicants?

    27.Explain or list out the advantages and disadvantages of K-map method?

    28.List out the advantages and disadvantages of Quine-Mc Cluskey method?

    29. Convert the (153.513)10 to Octal.

    30. Simplify the following Boolean functions to a minimum number of literals

    (a) (x y)(x y)

    (b) xy xz yz .

    31. Draw the logic diagram for the Boolean expression ((A B) C)D usingNAND gates.

    32. Perform subtraction using 1s complement (11010)2 (10000)2.

    PART B (16 Marks)

    1. (a) Explain how you will construct an (n+1) bit Gray code from an n bit

    Gray code (8)

    (b) Show that the Excess 3 code is self complementing (8)

    2. (a) Prove that (x1+x2).(x1. x3+x3) (x2 + x1.x3) =x1x2 (8)

    (b) Simplify using K-map to obtain a minimum POS expression: (8)

    (A + B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D)

    (A+B+C+D) (8)

    3. Reduce the following equation using Quine McClucky method of

    minimization F (A,B,C,D) = _m(0,1,3,4,5,7,10,13,14,15) (16)

    4. (a) State and Prove idempotent laws of Boolean algebra. (8)

    (b) using a K-Map ,Find the MSP from of F= _(0,4,8,12,3,7,11,15) +_d(5) (8)

    5 (a) With the help of a suitable example ,explain the meaning of an redundant prime i

  • Implicant (8)

    (b) Using a K-Map, Find the MSP form of F= _ (0-3, 12-15) + _d (7, 11) (8)

    6 (a) Simplify the following using the Quine McClusky minimization technique(8)

    D = f(a,b,c,d) = _ (0,1,2,3,6,7,8,9,14,15).Does Quine McClusky take care of dont

    care conditions? In the above problem, will you consider any dont care conditions?

    Justify your answer

    (b) List also the prime implicants and essential prime implicants for the above case(8)

    7 (a) Determine the MSP and MPS focus of F= _ (0, 2, 6, 8, 10, 12, 14, 15) (8)

    (b) State and Prove Demorgans theorem(8)

    8 Determine the MSP form of the Switching function

    F = _ ( 0,1,4,5,6,11,14,15,16,17,20- 22,30,32,33,36,37,48,49,52,53,56,63) (8)

    9. (a) Determine the MSP form of the Switching function(8)

    F( a,b,c,d) =_(0,2,4,6,8) + _d(10,11,12,13,14,15)

    (b) Find the Minterm expansion of f(a,b,c,d) = a(b+d) + acd(8)

    10 Simplify the following Boolean function by using the Tabulation Method

    F= _ (0, 1, 2, 8, 10, 11, 14, 15)

    11 State and Prove the postulates of Boolean algebra

    12 (a) Find a Min SOP and Min POS for f = bcd + bcd + acd + abc + abcd

    13 Find an expression for the following function usingQuine McCluscky method

    F= _ (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30)

    14 State and Prove the theorems of Boolean algebra with illustration

    15 Find the MSP representation for

    F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method

    Draw the circuit of the minimal expression using only NAND gates

    16 (a) Show that if all the gates in a two level AND-OR gate networks are replaced by

    NAND gates the output function does not change

    (b) Why does a good logic designer minimize the use of NOT gates?

  • 17 Simplify the Boolean function F(A,B,C,D) = _ m (1,3,7,11,15) + _d (0,2,5) .if dont

    care conditions are not taken care, What is the simplified Boolean function .What are

    your comments on it? Implement both circuits

    18 (a) Show that if all the gate in a two level OR-AND gate network are replaced byNOR gate, the output function does not change.

    (

Recommended

View more >