digital lab manual ec1010

7/24/2019 Digital Lab Manual EC1010

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EC1010-DIGITAL SYSTEM LAB

LAB MANUAL

SYLLABUS

1) Study of Gates & Flip-flops

2) Half Adder and Full Adder

3) Magnitude Comparator (2-it)

!) "n#oders and $e#oders

%) Multipleer and $emultipleer

') Code Conerter

) *mplementation of #om+inational logi# fun#tions using standard *C,s

) Syn#.ronous Counters

/) 0ipple Counter

1)Mod - Counter

11)S.ift 0egister S*S45S*6456*6456*S4

12)*mplementation of #om+inational logi# fun#tions using standard *C,s

13)Simulation eperiments using 6spi#e

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. 1


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SRM UNIVERSITY

Bharathi Salai, Ramapuram, Chennai-600 089.

Subject Code: EC1010 DegreeBranch: B.!ech"C" Subject #ame:DIGITAL SYSTEMS LAB $earSemSec : %%%%%&, B, C, D,"

LIST OF EPERIMENTS

17 8erify t.e trut. ta+le of 9ogi# gates and FlipFlops

27 8erify t.e trut. ta+le of Adders7

37 8erify t.e trut. ta+le of Su+tra#tors7

!7 8erify t.e trut. ta+le of "n#oders 7%7 8erify t.e trut. ta+le of $e#oders7

'7 8erify t.e trut. ta+le of Multipleer

7 8erify t.e trut. ta+le of $emultipleer

7 8erify t.e trut. ta+le of single +it Comparator

/7 8erify t.e trut. ta+le of !-it inary to gray #ode #onertors7

178erify t.e trut. ta+le of !-it Gray to inary #ode #onertors7

1178erify t.e trut. ta+le of #ounters7

1278erify t.e trut. ta+le of s.ift registers

137$esign and implementation of 9ogi# gates using 6spi#e1!7$esign and implementation of Flip Flops using 6spi#e

1%7$esign and implementation of Adders using 6spi#e

1'7$esign and implementation of Su+tra#tors using 6spi#e

PREPARED BY !OD/ECE


'ormat #o: ()-0*%++ue #o.: 0*%++ue Date: 0.0*.09


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EX.

NO

DATE NAME OF THE EXPERIMENT PAGE

NO

MARKS SIGNAT

INDEX

EPT NO" 1 STUDY OF LOGIC GATES

DATE "



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AIM"

:o study a+out logi# gates and erify t.eir trut. ta+les7

APPARATUS RE#UIRED"

T!EORY"

Cir#uit t.at ta;es t.e logi#al de#ision and t.e pro#ess are #alled logi# gates7

"a#. gate .as one or more input and only one output7

405 A$ and 4: are +asi# gates7 A$5 40 are ;no

17 A$ GA:" *C ! 1

27 40 GA:" *C !32 1

37 4: GA:" *C !! 1

!7 A$ GA:" 2 *?6 *C ! 1

%7 40 GA:" *C !2 1

'7 "@-40 GA:" *C !' 1

7 A$ GA:" 3 *?6 *C !1 1

7 *C :0A*"0 *: - 1

/7 6A:CH C40$ - 1!

$


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:.e 40 gate performs a logi#al addition #ommonly ;no


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OR GATE"

NOT GATE"

SYMBOL" PIN DIAGRAM"

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E-OR GATE "

SYMBOL " PIN DIAGRAM "

2-INPUT NAND GATE"

SYMBOL" PIN DIAGRAM"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. '


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3-INPUT NAND GATE "

NOR GATE"

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RESULT"

:.us t.e +asi# logi# gates .ae +een studied and outputs are erified7

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. )


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EPT NO " 2 DESIGN OF ADDER AND SUBTRACTOR

DATE "

AIM"

:o design and #onstru#t .alf adder5 full adder5 .alf su+tra#tor and full su+tra#tor

#ir#uits and erify t.e trut. ta+le using logi# gates7

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 A$ GA:" *C ! 1

27 "@-40 GA:" *C !' 1

37 4: GA:" *C !! 1!7 40 GA:" *C !32 1

37 *C :0A*"0 *: - 1

!7 6A:CH C40$S - 23

T!EORY"

!ALF ADDER"

A .alf adder .as t


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!ALF SUBTRACTOR"

:.e .alf su+tra#tor is #onstru#ted using @-40 and A$ Gate7 :.e .alf

su+tra#tor .as t


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0

0

1

1

0

1

0

1

0

0

0

1

0

1

1

0

*-Ma+ o SUM" *-Ma+ o CARRY"

SUM AB AB CARRY AB

LOGIC DIAGRAM"

FULL ADDER

FULL ADDER USING TO !ALF ADDER

TRUT! TABLE"



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A B C CARRY SUM

0

0

00

1

1

1

1

0

0

11

0

0

1

1

0

1

01

0

1

0

1

0

0

01

0

1

1

1

0

1

10

1

0

0

1

*-Ma+ o SUM"

SUM ABC ABC ABC ABC

*-Ma+ o CARRY"

CARRY AB BC AC

LOGIC DIAGRAM"



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!ALF SUBTRACTOR

TRUT! TABLE"

A B BORRO DIFFERENCE

0

0

11

0

1

01

0

1

00

0

1

10

*-Ma+ o DIFFERENCE"

DIFFERENCE AB AB

*-Ma+ o BORRO"

BORRO AB

LOGIC DIAGRAM"

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FULL SUBTRACTOR

FULL SUBTRACTOR USING TO !ALF SUBTRACTOR"

TRUT! TABLE"

A B C BORRO DIFFERENCE

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0

0

0

0

1

11

1

0

0

1

1

0

01

1

0

1

0

1

0

10

1

0

1

1

1

0

00

1

0

1

1

0

1

00

1

*-Ma+ o Dee4e"

Dee4e ABC ABC ABC ABC

*-Ma+ o Boo5"

Boo5 AB BC AC

PROCEEDURE"

(i) Conne#tions are gien as per #ir#uit diagram7

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(ii) 9ogi#al inputs are gien as per #ir#uit diagram7

(iii) 4+sere t.e output and erify t.e trut. ta+le7

RESULT"

:.us t.e adders and su+tra#tors .ae +een designed and outputs are erified

using trut. ta+les7

EPT NO " 3

DATE "

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. 1'


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DESIGN AND IMPLEMENTATION OF CODE CON6ERTOR

AIM"

:o design and implement !-+it

(i) inary to gray #ode #onerter

(ii) Gray to +inary #ode #onerter

(iii) C$ to e#ess-3 #ode #onerter

(i) "#ess-3 to C$ #ode #onerter

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 @-40 GA:" *C !' 1

27 A$ GA:" *C ! 1

37 40 GA:" *C !32 1!7 4: GA:" *C !! 1

%7 *C :0A*"0 *: - 1

'7 6A:CH C40$S - 3%

T!EORY"

:.e aaila+ility of large ariety of #odes for t.e same dis#rete elements of

information results in t.e use of different #odes +y different systems7 A #onersion

#ir#uit must +e inserted +et


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#ode5 t.e input lines must supply t.e +it #om+ination of elements as spe#ified +y #ode

and t.e output lines generate t.e #orresponding +it #om+ination of #ode7 "a#. one of

t.e four maps represents one of t.e four outputs of t.e #ir#uit as a fun#tion of t.e four

input aria+les7

A t


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G3 B3*-Ma+ o G2"

*-Ma+ o G1"

*-Ma+ o G0"



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TRUT! TABLE"7 Ba8 +9: 7 Ga8 4o;e o9:+9: 7

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

11

0

0

0

0

1

1

1

1

0

0

0

0

1

1

11

0

0

1

1

0

0

1

1

0

0

1

1

0

0

11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

01

0

0

0

0

0

0

0

0

1

1

1

1

1

1

11

0

0

0

0

1

1

1

1

1

1

1

1

0

0

00

0

0

1

1

1

1

0

0

0

0

1

1

1

1

00

0

1

1

0

0

1

1

0

0

1

1

0

0

1

10



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LOGIC DIAGRAM"

GRAY CODE TO BINARY CON6ERTOR

*-Ma+ o B3"

B3 G3



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*-Ma+ o B0"

TRUT! TABLE"

7 Ga8 Co;e 7 Ba8 Co;e 7

G3 G2 G1 G0 B3 B2 B1 B0

0

00

0

0

0

0

0

1

1

1

11

1

1

1

0

00

0

1

1

1

1

1

1

1

10

0

0

0

0

01

1

1

1

0

0

0

0

1

11

1

0

0

0

11

0

0

1

1

0

0

1

1

00

1

1

0

0

00

0

0

0

0

0

1

1

1

11

1

1

1

0

00

0

1

1

1

1

0

0

0

01

1

1

1

0

01

1

0

0

1

1

0

0

1

10

0

1

1

0

10

1

0

1

0

1

0

1

0

10

1

0

1



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LOGIC DIAGRAM"

BCD TO ECESS-3 CON6ERTOR

*-Ma+ o E3"

E3 B3 B2


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*-Ma+ o E2"

*-Ma+ o E1"



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*-Ma+ o E0"

TRUT! TABLE"

7 BCD +9: 7 E>4e?? @ 3 o9:+9: 7

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

11

1

1

1

0

0

0

0

1

1

1

1

0

0

0

01

1

1

1

0

0

1

1

0

0

1

1

0

0

1

10

0

1

1

0

1

0

1

0

1

0

1

0

1

0

10

1

0

1

0

0

0

0

0

1

1

1

1

1

>

>>

>

>

>

0

1

1

1

1

0

0

0

0

1

>

>>

>

>

>

1

0

0

1

1

0

0

1

1

0

>

>>

>

>

>

1

0

1

0

1

0

1

0

1

0

>>

>

>

>



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LOGIC DIAGRAM"

ECESS-3 TO BCD CON6ERTOR

*-Ma+ o A"

A 1 2 3 $ 1

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*-Ma+ o B"

*-Ma+ o C"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. 2)


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*-Ma+ o D"

TRUT! TABLE"

7 E>4e?? @ 3 I+9: 7 BCD O9:+9: 7

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

11

1

0

1

1

1

1

0

0

00

1

1

0

0

1

1

0

0

11

0

1

0

1

0

1

0

1

01

0

0

0

0

0

0

0

0

01

1

0

0

0

0

1

1

1

10

0

0

0

1

1

0

0

1

10

0

0

1

0

1

0

1

0

10

1



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PROCEDURE"

(i) Conne#tions


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EPT NO" $

DATE "

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM"

:o design and implement

(i) 2 +it magnitude #omparator using +asi# gates7

(ii) +it magnitude #omparator using *C !%7

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 A$ GA:" *C ! 2

27 @-40 GA:" *C !' 1

37 40 GA:" *C !32 1

!7 4: GA:" *C !! 1

%7 !-*: MAG*:E$"

C4M6A0A:40

*C !% 2

'7 *C :0A*"0 *: - 17 6A:CH C40$S - 3

T!EORY"

:.e #omparison of t


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A A3 A2 A1 A

3 2 1

:.e euality of t.e t


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* MAP



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TRUT! TABLE

A1 A0 B1 B0 A B A B A B

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 00 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0

PIN DIAGRAM FOR IC '$(%"



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LOGIC DIAGRAM"

( BIT MAGNITUDE COMPARATOR



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TRUT! TABLE"

A B AB AB AB

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1

PROCEDURE"



2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. 3(


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RESULT"

EPT NO " %

DATE "

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. 3)


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DESIGN AND IMPLEMENTATION OF MULTIPLEER AND

DEMULTIPLEER

AIM"

:o design and implement multipleer and demultipleer using logi# gates and

study of *C !1% and *C !1%!7

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 3 *?6 A$ GA:" *C !11 2

27 40 GA:" *C !32 1

37 4: GA:" *C !! 1

27 *C :0A*"0 *: - 1

37 6A:CH C40$S - 32

T!EORY"

MULTIPLEER"

Multipleer means transmitting a large num+er of information units oer a

smaller num+er of #.annels or lines7 A digital multipleer is a #om+inational #ir#uit

t.at sele#ts +inary information from one of many input lines and dire#ts it to a single

output line7 :.e sele#tion of a parti#ular input line is #ontrolled +y a set of sele#tion

lines7 ormally t.ere are 2ninput line and n sele#tion lines


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BLOC* DIAGRAM FOR $"1 MULTIPLEER"

FUNCTION TABLE"

S1 S0 INPUTS Y

0 0 D0 D0 S1 S0

0 1 D1 D1 S1 S0

1 0 D2 D2 S1 S0

1 1 D3 D3 S1 S0

Y D0 S1 S0 D1 S1 S0 D2 S1 S0 D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEER"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. $1


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TRUT! TABLE"

S1 S0 Y OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

BLOC* DIAGRAM FOR 1"$ DEMULTIPLEER"



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FUNCTION TABLE"

S1 S0 INPUT

0 0 D0 S1 S0

0 1 D1 S1 S0

1 0 D2 S1 S0

1 1 D3 S1 S0

Y S1 S0 S1 S0 S1 S0 S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEER"



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TRUT! TABLE"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. $$


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INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 01 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN DIAGRAM FOR IC '$1%0"

PIN DIAGRAM FOR IC '$1%$"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. $%


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PROCEDURE"




RESULT"

EPT NO " &

DATE "

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. $&


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DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM"

:o design and implement en#oder and de#oder using logi# gates and study of

*C !!% and *C !1!7

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 3 *?6 A$ GA:" *C !1 2

27 40 GA:" *C !32 337 4: GA:" *C !! 1

27 *C :0A*"0 *: - 1

37 6A:CH C40$S - 2

T!EORY"

ENCODER"

An en#oder is a digital #ir#uit t.at perform inerse operation of a de#oder7 An

en#oder .as 2ninput lines and n output lines7 *n en#oder t.e output lines generates t.e

+inary #ode #orresponding to t.e input alue7 *n o#tal to +inary en#oder it .as eig.t

inputs5 one for ea#. o#tal digit and t.ree output t.at generate t.e #orresponding +inary

#ode7 *n en#oder it is assumed t.at only one input .as a alue of one at any gien time

ot.er


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generally .as fe


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LOGIC DIAGRAM FOR ENCODER"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. $)


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TRUT! TABLE"

INPUT OUTPUT

Y1 Y2 Y3 Y$ Y% Y& Y' A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR ENCODER"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. %0


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TRUT! TABLE"

INPUT OUTPUT

I0 I1 I2 I3 A B

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

LOGIC DIAGRAM FOR DECODER"



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TRUT! TABLE"

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

PROCEDURE"




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RESULT"

EPT NO " 'DATE "

CONSTRUCTION AND 6ERIFICATION OF $ BIT RIPPLE COUNTER AND

MOD 10/MOD 12 RIPPLE COUNTER

AIM"



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:o design and erify ! +it ripple #ounter mod 1? mod 12 ripple #ounter7

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 F9*6 F946 *C !' 2

27 A$ GA:" *C ! 1

37 *C :0A*"0 *: - 1

!7 6A:CH C40$S - 3

T!EORY"

A #ounter is a register #apa+le of #ounting num+er of #lo#; pulse arriing at its

#lo#; input7 Counter represents t.e num+er of #lo#; pulses arried7 A spe#ified

seuen#e of states appears as #ounter output7 :.is is t.e main differen#e +et


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LOGIC DIAGRAM FOR $ BIT RIPPLE COUNTER"

TRUT! TABLE"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. %%


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CL* #D #C #B #A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1$ 0 1 0 0

% 0 1 0 1

& 0 1 1 0

' 0 1 1 1

( 1 0 0 0

) 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 013 1 1 0 1

1$ 1 1 1 0

1% 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. %&


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TRUT! TABLE"

CL* #D #C #B #A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

$ 0 1 0 0

% 0 1 0 1

& 0 1 1 0' 0 1 1 1

( 1 0 0 0

) 1 0 0 1

10 0 0 0 0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. %'


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TRUT! TABLE"

CL* #D #C #B #A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

$ 0 1 0 0

% 0 1 0 1

& 0 1 1 0

' 0 1 1 1

( 1 0 0 0

) 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 0 0 0 0

PROCEDURE"




2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. %(


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RESULT"

EPT NO " (

DATE "

DESIGN AND IMPLEMENTATION OF 3 BIT SYNC!RONOUS UP/DON

COUNTER

AIM"

:o design and implement 3 +it syn#.ronous up?do


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APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 F9*6 F946 *C !' 2

27 3 *?6 A$ GA:" *C !11 1

37 40 GA:" *C !32 1

!7 @40 GA:" *C !' 1

%7 4: GA:" *C !! 1

'7 *C :0A*"0 *: - 1

7 6A:CH C40$S - 3%

T!EORY"

A #ounter is a register #apa+le of #ounting num+er of #lo#; pulse arriing at its

#lo#; input7 Counter represents t.e num+er of #lo#; pulses arried7 An up?do


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0 0 0 1 0 0 0 0 0 1

1 0 0 0 0 0 1 0 0 1

1 0 0 1 0 1 0 0 1 1

1 0 1 0 0 1 1 0 0 1

1 0 1 1 1 0 0 1 1 1

1 1 0 0 1 0 1 0 0 1 1 1 0 1 1 1 0 0 1 1

1 1 1 0 1 1 1 0 0 1

1 1 1 1 0 0 0 1 1 1

* MAP

STATE DIAGRAM"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. &1


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C!ARACTERISTICS TABLE"

# #:1 *

0 0 0

0 1 1

1 0 11 1 0

LOGIC DIAGRAM"



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PROCEDURE"




RESULT"

EPT NO " )

DATE "



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DESIGN AND IMPLEMENTATION OF S!IFT REGISTER

AIM"

:o design and implement

(i) Serial in serial out

(ii) Serial in parallel out

(iii) 6arallel in serial out

(i) 6arallel in parallel out

APPARATUS RE#UIRED"

Sl7o7 C4M64": S6"C*F*CA:*4 =:>7

17 $ F9*6 F946 *C !! 2

27 40 GA:" *C !32 1

37 *C :0A*"0 *: - 1

!7 6A:CH C40$S - 3%

T!EORY"

A register is #apa+le of s.ifting its +inary information in one or +ot. dire#tions

is ;no


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LOGIC DIAGRAM"

SERIAL IN SERIAL OUT"

TRUT! TABLE"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. &%


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CL*

Sea Sea o9:

1 1 0

2 0 0

3 0 0

$ 1 1

% 0

& 0

' 1

LOGIC DIAGRAM"

SERIAL IN PARALLEL OUT"

TRUT! TABLE"

CL* DATA

OUTPUT

#3 #2 #1 #0

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

$ 1 1 0 0 1

LOGIC DIAGRAM"

PARALLEL IN SERIAL OUT"

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. &&


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TRUT! TABLE"

CL* #3 #2 #1 #0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM"

PARALLEL IN PARALLEL OUT"

TRUT! TABLE"

CL*

DATA INPUT OUTPUT

D3 D2 D1 D0 #3 #2 #1 #0

1 1 0 0 1 1 0 0 1

2013 REG., / ODD / III SEM/ ECE / EC1010 / DIGITAL LAB MANUAL Page No. &'


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2 1 0 1 0 1 0 1 0

PROCEDURE"




RESULT"

digital lab manual ec1010

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