Custom Single PurposeProcessors: Hardware

Outline

Introduction Combinational logic Sequential logic Custom single-purpose processor design RT-level custom single-purpose processor design

Chapter 2: Custom single-purpose processors

Custom single-purpose processor basic model

controller and datapath

controller datapath

…

…

externalcontrolinputs

externalcontrol outputs

…

externaldata

inputs

…

externaldata

outputs

datapathcontrolinputs

datapathcontroloutputs

Store and manipulate system data• registers

• functional units• wires

• multiplexers

Control datapath I/OMonitor external I/O

… …

a view inside the controller and datapath

controller datapath

… …

stateregister

next-stateand

controllogic

registers

functionalunits

externalcontrolinputs

externalcontrol outputs

externaldata

inputs

externaldata

outputs

How would you implement a

GCD in software?

Example: greatest common divisor

(b) desired functionality

y = y -x7: x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

(c) state diagram

Describe in words Behavioral design Determine I/O Black box view Create algorithm Convert algorithm to “complex” state

machine Known as FSMD: finite-state machine with

datapath Essentially a flow chart Different than earlier state diagrams

• Arithmetic expressions are allowed• Other variables are allowed

Can use templates to perform such conversion

GCD

(a) black-box view

x_i y_i

d_o

go_i

Our single purpose is to design a GCD!

int x,y

State diagram templates

Assignment statement

a = bnext statement

a = b

next statement

Loop statement

while (cond) { loop-body-

statements}next statement

loop-body-statements

cond

next statement

!cond

J:

C:

Branch statementif (c1) c1 stmtselse if c2 c2 stmtselse other stmtsnext statement

c1

c2 stmts

!c1*c2 !c1*!c2

next statement

othersc1 stmts

J:

C:

Action of this state

Condition state C

Join state J

Loop body

Creating the datapath

Create a register for any declared variable x, y, d

Create a functional unit for each arithmetic operation

Connect the ports, registers and functional units Based on reads and writes Connect “write’s” source to that

variable’s register A source may be an input port,

functional unit or other registers Use multiplexers for multiple

sources Create unique identifier

for each datapath component control input and output

y = y -x7: 8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x - y

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

x_i y_i

d_o

0: x 0: y

9: d

Datapath

FSMDFSM

In order to implement this design, we need to convert the FSMD into a regular FSM that simply consists of Boolean functions and I/O variables (along with control I/O).

Essentially same structure as FSMD Replace complex actions/conditions with datapath configurations

Replace every variable write by actions that set the select signals of the MUX in front of that variable’s register, such that the write’s source passes through the MUX, and assert the load signal of that register.

Replace every logical operation in a condition by the corresponding functional unit control output

Any signal that is not explicitly assigned a state, is implicitly assigned a zero (0), e.g., x_ld is assigned a 0 in every state, except for 3 and 8, where it is assigned a “1”

Creating the controller’s FSM

Same structure as FSMD Replace complex actions/conditions with

datapath configurations Replace every write by actions that set the select

signals of the MUX in front of the variable’s reg., and assert the load signal of that reg.

Replace every logical operation in a condition by the corresponding functional unit control output

y = y -x7: x = x - y8:

6-J:

x!=y

5: !(x!=y)

x<y !(x<y)

6:

5-J:

1:

1

!1

x = x_i3:

y = y_i4:

2:

2-J:

!go_i

!(!go_i)

d_o = x

1-J:

9:

7: 8:

6-J:

5:

6:

5-J:

1-J:

9:

3:

4:

1:1

!1

2:

2-J:

!go_i

!(!go_i)

go_i

0000

0001

0010

0011

0100

0101

0110

0111 1000

1001

1010

1011

1100

Controller

x_i y_i

d_o

0: x 0: y

9: d

Datapath

d_ld

x_ld

y_ld

Implementing the FSM

Complete the controller design by implementing the FSM we have just created Use the standard sequential design techniques for this purpose

Complete the state diagram Create the transition table Generate Boolean functions from the transition table Simplify the Boolean expressions, etc.

Note that in the previous design, there werea total of 13 states, which in general, requires 4 FFs hence 4 state variables,I1, I2, I3, I4, with outputs Q1 ~ Q4.

Controller implementation model

y_sel

x_selCombinational

logic

Q3 Q0

State register

go_i

x_neq_y

x_lt_y

x_ld

y_ld

d_ld

Q2 Q1

I3 I0I2 I1

Splitting into a controller and datapath

y_sel = 1y_ld = 1

7: x_sel = 1x_ld = 1

8:

6-J:

x_neq_y=1

5:x_neq_y=0

x_lt_y=1 x_lt_y=0

6:

5-J:

d_ld = 1

1-J:

9:

x_sel = 0x_ld = 13:

y_sel = 0y_ld = 14:

1:1

!1

2:

2-J:

!go_i

!(!go_i)

go_i

0000

0001

0010

0011

0100

0101

0110

0111 1000

1001

1010

1011

1100

Controller

Controller implementation model

y_sel

x_selCombinational

logic

Q3 Q0

State register

go_i

x_neq_y

x_lt_y

x_ld

y_ld

d_ld

Q2 Q1

I3 I0I2 I1

subtractor subtractor

x_i y_i

d_o

0: x 0: y

9: d

n-bit 2x1 n-bit 2x1

<

7: y-x8: x-y6: x<y5: x!=y

!=

Datapath

x_sel

y_sel

x_neq_y

x_lt_y

d_ld

x_ld

y_ld

Controller state table for the GCD example

Inputs Outputs

Q3

Q2

Q1

Q0

x_neq_y

x_lt_y

go_i

I3 I2 I1 I0

x_sel

y_sel

x_ld

y_ld

d_ld

0 0 0 0 * * * 0 0 0 1 X X 0 0 00 0 0 1 * * 0 0 0 1 0 X X 0 0 00 0 0 1 * * 1 0 0 1 1 X X 0 0 00 0 1 0 * * * 0 0 0 1 X X 0 0 00 0 1 1 * * * 0 1 0 0 0 X 1 0 00 1 0 0 * * * 0 1 0 1 X 0 0 1 00 1 0 1 0 * * 1 0 1 1 X X 0 0 00 1 0 1 1 * * 0 1 1 0 X X 0 0 00 1 1 0 * 0 * 1 0 0 0 X X 0 0 00 1 1 0 * 1 * 0 1 1 1 X X 0 0 00 1 1 1 * * * 1 0 0 1 X 1 0 1 01 0 0 0 * * * 1 0 0 1 1 X 1 0 01 0 0 1 * * * 1 0 1 0 X X 0 0 01 0 1 0 * * * 0 1 0 1 X X 0 0 01 0 1 1 * * * 1 1 0 0 X X 0 0 11 1 0 0 * * * 0 0 0 0 X X 0 0 01 1 0 1 * * * 0 0 0 0 X X 0 0 01 1 1 0 * * * 0 0 0 0 X X 0 0 01 1 1 1 * * * 0 0 0 0 X X 0 0 0

Current statevalues

ControllerI/P variables Next state

values

ControllerO/P variables

Other issues…

There are a total of 7 inputs to the controller 128 rows for TT Reduce number of rows, using * for some I/P combinations Tedious to optimize by hand

Use CAD tools ! CAD tools that automatically generate digital gates from sequential programs

(behavioral design), FSMDs or FSMs or logic equations are known as sythesis tools.

Data path can also be further optimized: Merge functional units (one instead of two subtractors), but we would then need more

multiplexers. Merge certain states into single states

Be careful about timing issues: All statements in a single state are implemented concurrently in an FSMD! Actions consisting of writes to variables do NOT actually update the variables until

after the next clock cycle, since all variables are implemented as registers. Assuming that an outgoing arc from a state is using the updated value is a very common mistake. If we want to assign a value to a variable, and then branch based on that value, we NEED to insert an additional state. This is what the empty states in FSMD are for.!

Completing the GCD custom single-purpose processor design

We finished the datapath We have a state table for the

next state and control logic All that’s left is combinational

logic design

This is not an optimized design, but we see the basic steps

… …

a view inside the controller and datapath

controller datapath

… …

stateregister

next-stateand

controllogic

registers

functionalunits

Summary

Custom single-purpose processors Straightforward design techniques Can be built to execute algorithms Typically start with FSMD CAD tools can be of great assistance