digital hcal readout studies

Digital HCAL readout studies

1 - Readout for Prototype (Laboratoire Leprince-Ringuet-IN2P3)

2 - Readout for a large scale detector (SEL-SEE - Seoul National University)

CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

WARNING

Studies for the prototype

The LLR electronic group working on the project A.Karar, F.Dohou, A.Montgermont

Design Test

Construction

of a test set-up for the readout of a digital HCAL


1.2 mm

TFE/N2/IB 80/10/10

Efficiency to mip > 98%

Pads outside

Pads inside

Signal on 50 : 1-3 V

1x1 cm2by courtesy of Vladimir Ammossov

Two examples of RPC as active element

Pad size

Gas gap thickness

Gas mixture

First measurement


Signal output of the RPCSignal (on 50 1 V


Possible readout scheme for a VFE 64 channel chip

Reading the chips through a token ring

RequirementsThin PCB (1mm)combining pads and circuitryThin packaging, TQFP 1 mmLow power dissipation ~ 1 mW/ch


Scheme of the test set-up

Test all these idea with readout for cosmicTest all these idea with readout for cosmic


The test set-up


The FPGA part


RPC - FPGA interface

The requirements Current to voltage conversion Pulse stretching Digital output (CMOS compatible) Low input impedance Overvoltage protection of FPGA Low power consumption

The conditioning circuit

RPC conditioning by current mirror circuit


VO

LT

microseconde

Results with Current Mirror circuit

Output signal

Input signal


The FPGA-DAQ on PC

On MATLABOn MATLABAll readout chainis ready


Design of Readout Electronicsfor digital HCAL on Linear Collider

Jaehong Park, Taeyeon Lee, Jinho Sung,

Sanghyun Min, Donghwan Lee

System Electronics Laboratory

School of Electrical Engineering

Seoul National University, Seoul, Korea


Rise time: 3nsWidth: 10~15nsAmplitude: 300~500mV

System configuration

• Input signal condition

• System configuration

Readoutelectronics

Control

Data

Detector64 signals

Control station

1cm

1cm

Pad

8 x 8 = 64 pads

Typical for RPC


Readout Electronics Design

• Functional Block Diagram of Readout

1

2

64

65

76

Bunchcrossingcounter

1 256

Serializer

Serial_data

Empty

1

2

64

DACThreshold

ComparatorPad

FIFO76 x 256

Count pulse

Clear

Loader WCLK, WEN/ Seriallink

CLK

Control

LEFF/

CLK, Selector input

RCLK,REN/

Q

EF/

Count pulse

Clear

DAC input

Reset/

Retrieve

Counted

FPGADAC

Connector

Comparators


Simulation Results of FPGA

• Load Dead pixel configuration

• Set DAC Command: SET DAC Upper 2bitLower 8bit Update DAC

Command: RESET Command: LOAD CFG DAC DATA MASK DATA

Simulation Results of FPGA

• Measure

• Retrieve

Command: MEASURE Measuring Process

Command: RETRIEVE Bunch Cross Counter 12bit Comparator Data 64bit

Test Circuit Design

• Test Circuit– Check out the functions of Readout Electronics– Test circuit size: 9x9 cmTest circuit size: 9x9 cm22

FPGA DAC Connector Comparators

Component side Solder side


ConclusionAll the pieces of the puzzle have been

Designed Built

Tested

FPGA with in front, .

a Current Mirror circuit (LLR) or ADC+discriminator (SELSEE-SNU) We are ready to read the prototype very soon for a RPC-type signal

The possibility to design a thin, simple, cheap electronic readout for the digital HCAL,

has been demonstrated

At least, one conclusion NOW


digital hcal readout studies

Documents