digital electronics tutorial: number system & arithmetic circuits solutions
DESCRIPTION
Digital Electronics Tutorial: Number System & Arithmetic Circuits Solutions. Number System. Conversion to Base 10 FFA 16 1101100 2 1000 2 1000 16 Binary Addition in 2’complement 100 110 + 000 111 100 111 + 000 101 100 111 + 100 100 011 111 + 010 111 Binary Subtraction in 2’complement - PowerPoint PPT PresentationTRANSCRIPT
Digital Electronics
Tutorial: Number System & Arithmetic Circuits
Solutions
Number System
Conversion to Base 10 FFA16
11011002
10002
100016 Binary Addition in 2’complement
100 110 + 000 111 100 111 + 000 101 100 111 + 100 100 011 111 + 010 111
Binary Subtraction in 2’complement 100 110 - 000 111 100 111 - 000 101 100 111 - 100 100 011 111 - 010 111
Number System Solutions (1/3)
Conversion to Base 10 FFA16 = F × 162 + F × 161 + A × 160
= 15 × 162 + 15 × 161 + 10 × 160 = 4090
11011002 = 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20
= 108
10002 = 1 × 23 + 0 × 22 + 0 × 21 + 0 × 20
= 8
100016 = 1 × 163 + 0 × 162 + 0 × 161 + 0 × 160
= 4096
Number System Solutions (2/3)
Binary Addition in 2’complement
100 110 + 000 111 __________ 101 101
100 111 + 000 101
__________ 101 100
100 111 + 100 100 __________
Overflow1 001 011
011 111 + 010 111
__________Overflow 110 110
Number System Solution (3/3)
Binary Subtraction in 2’complement 100 110 - 000 111 = 100 110 + 111 000 + 1 100 111 - 000 101 = 100 111 + 111 010 + 1 100 111 - 100 100 = 100 111 + 011 011 + 1 011 111 - 010 111 = 011 111 + 101 000 + 1
100 110 + 111 000
1 Overflow1 011 111
100 111 + 111 010 1
Overflow1 100 010
100 111 + 011 011
1 1 000 011
011 111 + 101 000 1 1 001 000
Arithmetic Circuits
Implement a combinational logic circuit that converts a 4-bit sign and magnitude numbers into corresponding 4-bit two’s complement numbers. Draw an input/output conversion truth table, intermediate K-maps, and your minimised two-level logic description.
Arithmetic Circuits Solution (1/4)
ABCD EFGH0000 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 00001001 11111010 11101011 11011100 11001101 10111110 10101111 1001
CD
AB 00 01 11 10
00 0 0 1 0 01 0 0 1 1
11 0 0 1 1
10 0 0 1 1
E = AB + AC + AD
Arithmetic Circuits Solution (2/4)
ABCD EFGH0000 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 00001001 11111010 11101011 11011100 11001101 10111110 10101111 1001
CD
AB 00 01 11 10
00 0 1 1 0 01 0 1 0 1
11 0 1 0 1
10 0 1 0 1
F = A’ B + B C’ D’ + A B’ D + A B’ C
Arithmetic Circuits Solution (3/4)
ABCD EFGH0000 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 00001001 11111010 11101011 11011100 11001101 10111110 10101111 1001
CD
AB 00 01 11 10
00 0 0 0 0 01 0 0 1 1
11 1 1 0 0
10 1 1 1 1
G = C D’ + A’ C + A C’ D
Arithmetic Circuits Solution (4/4)
ABCD EFGH0000 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 00001001 11111010 11101011 11011100 11001101 10111110 10101111 1001
CD
AB 00 01 11 10
00 0 0 0 0 01 1 1 1 1
11 1 1 1 1
10 0 0 0 0
H = D
Bit-Serial Adder
The traditional binary adder operates on all of its input bits at the same time, calculating the sum output bits in parallel. Consider an alternative way to implement a binary adder using a so-called bit serial approach. The two numbers to be added are presented to a Finite State Machine one bit at a time, with the lowest order bits presented first. The Finite State Machine produces at its output the lowest order bit of the sum, then the next higher order sum bit, and so on, until all of the input bits have been processed and all of the output sum bits generated.
(a) Design a simple datapath for the bit-serial adder down to the gate level, and identify the interface between your control finite state machine and the datapath. Consider how to deal with carry-in and carry-out in your design.
(b) Show your state diagram for a 4-bit bit-serial adder, where the outputs of the state machine are the control signals of the datapath you designed in (a).
(c) Demonstrate how your subsystem works by showing step-by-step how it executes the summation of 0110 and 1100. The carry-in to the low order bit is initially zero.
Bit-Serial Adder Solution (1/3)
(a) Design a simple datapath for the bit-serial adder down to the gate level, and identify the interface between your control finite state machine and the datapath. Consider how to deal with carry-in and carry-out in your design.
Signals: SHIFT, CinSELECT, SELECT, CE
Bit-Serial Adder Solution (2/3)
(b) Show your state diagram for a 4-bit bit-serial adder, where the outputs of the state machine are the control signals of the datapath you designed in (a).
Bit-Serial Adder Solution (3/3)
(c) Demonstrate how your subsystem works by showing step-by-step how it executes the summation of 0110 and 1100. The carry-in to the low order bit is initially zero.
A[3:0] = 0110 B[3:0] = 1100 Cin = 0 0110 + 1100 = 1 0010
A[3:0] = 0110 B[3:0] = 1100
Step 1: SELECT = 00 CinSELECT = 0 SUM = 0000 Cout = 0
Step 2: SELECT = 01 CinSELECT = 1 SUM = 1000 Cout = 0
Step 3: SELECT = 10 CinSELECT = 1 SUM = 0100 Cout = 1
Step 4: SELECT = 11 CinSELECT = 1 SUM = 0010 Cout = 1
Cout Sum