digital electronics 1

7/27/2019 Digital Electronics 1

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DIGITAL ELECTRONICSCHAPTER 1

Arslan Qamar MalikLecturer


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Basic Logic Operations

There are 5 basic logic operationsrepresenting the digital electronic circuits.

NOT AND

OR

NAND

NOR


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Digital Logic Circuits -

Gates The device/circuit that performs single logic

operation is called Gate.

Combinational Gates The gates that perform one or more of the basic

logical operations are referred to as CombinationalGates.

Outputs depend only on the present value of theinputs.


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Gates Sequential Gates

The gates that perform sequential logicoperations are referred to as Sequential Gates.

Outputs depend on the past values of the inputsas well as present values.


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States For all digital circuits, a variable can only have

two states, 0 and 1. Such variable is calledBinary variable.

Considering voltage as a variable, Binary0state representing low vol tageand binary1state representing high vol tage.


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Inverter If the input voltage is low, the output voltage

will be high and vice versa.

Since this device performs logical NOToperation, this device is also called NOT gate.

It makes no difference if the inverting circle isat the input or output.


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Digital Logic Circuits Non-

Inverter

Non-Inverting devices are also termed asBuffers.

Buffers are used to regenerate voltage levels. Buffers adjust degraded high levels to higher

and degraded low levels to lower.


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Ideal Logic Inverter

A typical operating voltage ofmany logic families is 5V.

Ideal Power dissipation of all

logic families is zero. In actualcase, the power dissipation isminimized for optimum design.

Ideally, the logical 1 output voltage is at the powersupply voltage Vcc.

Ideally, the logical 0 output voltage is at ground (0V).


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Ideally, the transition between output logicstates occurs abruptly at an input of Vcc/2.

Logical input 0 is represented

by the voltage range0 VIN < Vcc/2. Logical input 1 is represented

by the voltage range

Vcc/2 < VIN < Vcc. VIN = Vcc/2 has an undefined

output and gives

unpredictable results.

Ideal Logic Static & PowerCharacteristic


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Ideal Logic Transient

Characteristic

Upon transition of the input from logical 0 tological 1, the output instantaneously switchesfrom logical 1 to logical 0 without any delay.

In actual case, the transitionbetween states is not

instantaneous and a delay

between the output andinput transitions is present.


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Ideal Logic Input & Output

Impedances

Transient response and driving ability (fan-out)of logic gates are directly dependent upon thegates input and output impedance.


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Impedances

The previous figure shows a logic inverter drivingmultiple (identical) logic inverters. It is observedthat the driving gate must provide enough outputcurrent to drive all the load gates.

IOUT= NIINwhere the primed terms referred to load gates.

The input current is zero for a very large inputimpedance and driving capabilities are maximized.

An infinite input impedance is desired to obtaininfinite driving capability.


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Impedances

The input capacitance of load gates must becharged through the output resistance of thedriving inverter. Thus, a smaller outputresistance will provide a larger charging currentfor the load capacitance and a faster switchingtime.

Ideally, the output resistance must be zero.

A smaller input capacitance can also speed upthe switching time of the load gates.


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Inverter Voltage Transfer

Characteristic

Voltage Transfer Characteristic (VTC) for logicinverters have been standardized.

VTC is the graph between Vout and VIN.

On vertical axis, VOH

and VOL

correspond to output high and

output low voltage levels

respectively.

On the horizontal axis, VIL is

input low voltage and VIH is

the input high voltage.


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Inverter Voltage Transfer

Characteristic

As the input voltage is increased from 0V, VIL isthe maximum input voltage that provides a high

output voltage (logical 1 output).

VIH is the minimum input voltage that provides alow output voltage (logical 0

output).

VOH, VOL, VIL and VIH arereferred to as the critical

voltages of the VTC.


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Logic Swing and Transition Width

Logic Swing The magnitude of voltage difference between the

output high and low voltage levels.

VLS

= VOH

VOL

Transition Width

The amount of voltage change that is required of theinput voltage to cause a change in the output voltage

from the high to the low level (and vice versa).VTW = VIH - VIL


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Noise in Digital Circuits

Noise Variations in the steady-state voltage levels of digital

circuits (i.e. Logical 1 and logical 0 states) areundesirable and cause logic errors. This variation istermed as Noise.

Noise Margins Voltage Noise Margin represents the safety margin

for the high and low voltage levels.

Noise voltages must have magnitudes less than thevoltage noise margins.

VNMH = VOH VIHVNML = VIL - VOL


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Noise Sensitivities

The effects of input variations are quantified in termsof the noise sensitivities.

The high noise sensitivity is defined as the difference

between input and midpoint voltage for VIN at VOH. The low noise sensitivity is defined as the difference

between input and midpoint voltage for VIN at VOL.

VNSH = VOH VMVNSL = VM - VOL


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Noise Immunities

The ability of a gate to reject noise.

The high and low noise immunities are defined as thequotient of the noise sensitivities and the logic swing.

VNIH = VNSH / VLSVNIL = VNSL / VLS


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FAN-IN and FAN-OUT

A general logic gate has multiple inputs and multipleoutputs.

By multiple outputs we mean the output of a given gate isconnected to (driving) the inputs of several load gates.

FAN-IN: the number of inputs of a gate.

FAN-OUT: the number of outputs of a gate.

Maximum FAN-OUT depends on the input and output

current of a driving gate. The maximum fan-out possible during the driving gates

logical 1 output state is

Nhigh = IOUT(high)/ IIN (high)


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FAN-IN and FAN-OUT

The maximum fan-out possible during the driving

gates logical 0 output state is

Nlow = IOUT(low)/ IIN (low)

i h i i


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Transient Characteristics

Switching Speed Definitions

td = delay time

tr = rise time

ts = storage time

tf= fall time

ton = turn on time

toff= turn off time

ton = td + tr toff= ts + tf

i h i i


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Propagation Delays

When the input voltage changes from one level toanother, the output voltage response is delayed intime. This is referred to as Propagation Delay.

i h i i


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The low to high propagation delay time tPLH

refersto the low to high transition of the output.

The high to low propagation delay time tPHL refersto the high to low transition of the output.

The overallpropagation delaytime tp(avg) is

tp(avg) = (tPLH + tPHL) / 2

P Di i ti


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Power Dissipation

Power Dissipation for an ideal gate is obtained byrealizing that it is equal to the power supplied. Thisis true for a gate with single power supply.

Power dissipation is different for the output high

(logical 1 output) and output low (logical 0 output)states and they are termed as PCC(OH) andPCC(OL), respectively.

The average power dissipation for a gate with thetwo possible output states as follows:

PCC(avg) = (PCC(OH) + PCC(OL))/ 2

P Di i ti


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Power Dissipation

PCC(avg) = [(ICC(OH) + ICC(OL)) / 2 ] xVCC Some logic circuits have 2 power supplies, one with a

positive voltage and one with a negative voltage. In

this case, both currents (ICC

and IEE

) are obtained for

each of the output high and output low logic states.

P Di i ti


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Power Dissipation

Average power supplied by the gate with two possible

states is then as follows:

P D l P d t


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Power Delay Product

Low power dissipation and short propagation delay

times are both desirable for digital logic circuits.

Faster propagation delay times are achieved at thecost of increased power dissipation.

Lower power dissipation results in longer propagationdelays.

Power Delay Product is the merit for digital logic gate

and is represented as follows:

PD = PDISS(avg) x tp(avg)

Smaller the Power Delay Product is for a gate, the

more ideal the gate is. Ideally, PD equals to 0 Joules.


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METAL OXIDE SEMICONDUCTOR

FIELD EFFECT TRANSISTOR

(MOSFET)

CHAPTER 16


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Introduction to MOSFET

BJTs are current-controlled devices. Thecurrent controlling terminal is Base.

FETs are voltage-controlled devices. The

current controlling terminal is Gate. In FETs, the current-controlled mechanism is

based on an electric field established by thevoltage applied to the Gate.

BJTs are Bipolar Junction transistors i.e. Thecurrent is due to the movement of both typesof charge carriers e.g. Holes and Electrons.


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Introduction to MOSFET

FETs are uni-polar devices i.e. The current isdue to the movement of the only one of thetwo types of charge carriers e.g. either due to

Holes or due to Electrons. Metal-Oxide Semiconductor FET (MOSFET) is

a very popular kind of FET due to thefollowing.

MOS transistors can be made quiet small.

Manufacturing process is comparatively simple.

Digital Logic operations can be implemented

using only MOSFETs.


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N-MOSFET

Metal Gate N-MOSFET The Enhancement-Type N-MOSFET is the most widely

used FET.

The transistor is fabricated on p-type substrate.

Two heavily doped n-type regions arecreated in p-typesubstrate.

A thin layer of SiO2 (aperfect insulator) is onthe surface of thesubstrate which

ensures IG=0A.


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N-MOSFET

Metal is deposited on top of the oxide layer to formthe Gate electrode of the device.

Other terminals i.e. Source, Drain and substrate arealso made over metal surface.

That is how the name ofthe device is set as MetalOxide Semiconductor

FET.


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N-MOSFET

Silicon Gate N-MOSFET Most of the modern MOSFETs are fabricated using a

process known as Silicon-Gate Technology.

Gate electrode is formed using a certain type of silicon

named Polysilicon.


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Enhancement-type N-MOSFET

Operation with No Gate Voltage Two back to back diodes exist in series between drain

and source.

One diode is formed by pn-junction between n+ drain

and p-type substrate.

Second diode is formed by pn-junction between n+source and p-type substrate.

These diodes prevent current conduction from drain to

source when voltage VDS is applied.

Both pn-junctions must be made Reverse-Biased.


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Creating a Channel for Current Flow Lets have VDS = 0V (source and drain are grounded).

Applying VGS (gate to source voltage) at Gate makingfree holes being repelled and pushed downwards in

the p-type substrate.

The Depletionregion is nowpopulated by the

electrons under theGate region.


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When a significant number of electrons accumulateunder the Gate, an n-region is created that connectsDrain and Source regions.

Applying VDS, current flows through this induced n-

region. This induced region will now become a Channel for

current to flow from Drain region to source region.

The device is now named as N-channel MOSFET.

Note that the N-channel is created in p-type substrate.


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Device Symbol

N-channel enhancement-type N-channel enhancement-type N-channel enhancement-typeMOSFET MOSFET MOSFET


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N-MOSFET Modes of Operation

Threshold Voltage The value of VGS at which a significant number of

mobile electrons accumulate in the channel region toform a conducting channel is called Threshold Voltage.

It is denoted by Vt. For n-channel MOSFET, Vt is positive.

To conduct current from Drain to Source terminal, the

VGS must be greater than Vt.

Greater the VGS from Vt, wider will be the channel andgreater will be the flow of current (ifVDS >0).

Effective Voltage = VGS - Vt.


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Increasing VGS above the threshold voltage (Vt)enhances the channel, hence the device named asEnhancement-type N-MOSFET.

Gate current is negligibly small thus current entering

at the drain terminal is equal to the current leaving atthe source terminal.


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Cutoff Mode IfVGS for N-MOSFET is less than Vt, the device is

in the cutoff mode of operation and no currentflows in the channel.

Linear Mode

As VGS is increased above Vt, the device is in Linearmode and ID is proportional to that increase.

ID is also proportional to the increase in VDSthatcauses ID to flow. VDS should be less than (VGS- Vt).

ID (Linear) = k[(VGS- Vt) VDS (V2

DS/2)]

k is the transconductance parameter.


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Saturation Mode

IfVDS is increased above the effective voltage(VGS- Vt) while VGS > Vt, the device operates in the

Saturation mode. It is evident that the VDS is dropped successfully

along the length of the channel and the lessamount will be available at the Source end if

compared it with the value at Drain end.


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Saturation Mode

Thus for a constant value ofVGS (i.e. VGS> Vt), ID isno longer in direct proportion ofVDS and the

current starts levelling off and maintains level forfurther increase in VDS. This condition is calledPinched-off.

ID (Sat) = k[(VGS- Vt)2]/2

ID (Sat) = k[(VGS- Vt)2(1+ VDS)]/2

Where is channel-length modulation parameter


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Saturation Mode At pinched-off, the depth of the channel is

decreased to zero but the flow of current is notcut-off rather it is maintained from Drain to

Source. Pinched-off occurs at VDS= VGS- Vt


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Family of Curves

The ID versus VDS graph is plotted to identifythe family of curves.

Three modes of operation are evident in the

graph.


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MOSFET: Device & Process

Transconductance Parameters The parameter k is referred to as Device

Transconductance parameter of a MOSFET.

W and L are channels width and lengthrespectively.

The parameter k is referred to as ProcessTransconductance parameter and its value isset at the fabrication level.


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Transconductance Parameters The parameter k is calculated by the following

expression:

is the electron/hole mobility in the channel.

COX is the gate oxide capacitance per unit area.

Different electron mobility is set industrially for

N-channel and P-channel MOSFET. Electronmobility is related to the average drift of

electrons/holes under the influence of electric

field.


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Transconductance Parameters N-channel MOSFET, the electron mobility is

N = 580 cm2/V.s

P-channel MOSFET, the hole mobility is

N = 230 cm2/V.s


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MOSFET: Gate Capacitance per

Unit Area (COX) COX is the Gate capacitance per unit area of

the parallel-plate capacitor formed by the

Gate electrode and the Channel.


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Unit Area (COX) Dielectric is provided by the silicon oxide layer

between Gate electrode and Channel.

COX = OX / tOXOX is the permittivity of the silicon oxide which

is the measure of the ability of Silicon oxide to be

polarized by the electric field.

tOX is the thickness of the oxide layer.


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Unit Area (COX) OX = 3.9 x O

O is the permittivity of vacuum. O = 8.854 x 10

-12 F/m

thus

OX = 3.45 x 10-11 F/m


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P-MOSFET

The P-channel MOSFET is fabricated on n-typesubstrate.

Two heavily doped p-

type regions arecreated in n-typesubstrate.

In P-MOSFET, the free

charges which movefrom end-to-end arepositively charged(holes).


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P-MOSFET

The device operates in exactly the similarmanner as N-MOSFET.

VGS and VDS are negative voltages.

Thus, Vt is a negative Threshold voltage.

The current ID enters the Source terminal and

leaves through the Drain terminal.


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Gate Oxide Capacitances

CGD is the capacitance between Gate andDrain.

CGS is the capacitance between Gate and

Source. CGB is the capacitance between Gate and

Body.


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Gate Oxide Capacitances

Total Gate Capacitance is the sum of thecapacitances between Gate and remainingregions of semiconductor.

CG = CGS + CGD + CGBCG = L*W* COX


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Exercise

Consider a process technology for whichLmin=0.4m, tox =8nm, N = 450cm

2/V.s

Vt

= 0.7V

a) Find Coxand kn

b) For MOSFET with Width=8m and Length=0.8m,calculate the values of VGS and VDS(min) needed tooperate the transistor in the saturation mode with a dccurrent (ID ) equals 100A.

c) Find the value of VGS required to cause the device tooperate as a 1k resistor for a very small VDS.


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Depletion-Type N-MOSFET

Threshold Voltage

As VGS is getting more negative, a value will reachwhen the channel is completely depleted of all

charge carriers (ID = 0A). The current remains zero for further increase in

VDS.

This negative value of VGS

is the ThresholdVoltage.

The device will not work if VGS is less than thethreshold voltage.


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The ID-VDS characteristics of a depletion-typen-channel MOSFET is shown below.


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The ID-VGS characteristic of a depletion-typen-channel MOSFET is shown below when thedevice is in saturation mode.

IDSS is the draincurrent when thedevice is insaturation mode

and VGS = 0V.


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Depletion-Type P-MOSFET

In P-MOSFET, the polarities of all voltages(including Vt) are reversed.

In P-MOSFET, the ID flows from the source

terminal and leaves at the drain terminal. The graph shows

the behaviour oftwo types ofMOSFETs whenthey are operatingin saturation mode.


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Exercise

For a Depletion-Type NMOS Transistor withVt= -2V, and k = 2mA/V

2, find the minimumVDS required to operate in the saturation

region when VGS = +1V. What is thecorresponding value of ID?


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Exercise

The Depletion-Type MOSFET has k = 4mA/V2and Vt= -2V. Neglecting the effect of VDS on IDin the saturation region, find the voltage that

will appear at the source terminal.


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MOSFET circuits at DC

Design the circuit to obtain ID = 0.4mA. Findthe value required for R and the dc voltageVD. The NMOS transistor has Vt=2V, nCOX =20A/V2, L = 10m and W = 100m. Neglectthe channel modulation effect (=0).


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RESISTOR LOADED NMOS

INVERTER (CHAPTER 18)


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MOSFET Amplifier & Switch

MOSFET acts as Voltage-controlled currentsource as long as the device is in Saturationregion.

Linear Amplification is achieved by followingthe two steps:

DC bias the MOSFET device

Superimposing the input signal to be amplified on

the dc bias voltage.

For the linear amplification, the input voltage(Vi) is kept small to make the change in drain

current proportional to the change in Vi.


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Large Scale Operation

Graphical Representation of Voltage TransferCharacteristics


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Operation as a Switch

To use MOSFET as a switch, the device is tooperate at the extreme positions in thetransfer curve.

The device is turned off when Vi < Vt. This isthe extreme left position on the transfercurve i.e. Vo = VDD and ID = 0A.

The device is turned on when Vi = VDD. This isthe extreme right position on the transfercurve i.e. Vo = 0V and ID is maximum.


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Operation as a Switch

The MOSFET is behaving as a Logic Inverter.High voltage level is close to VDD and Low

voltage level is close to 0V.


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Operation as a Linear


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Amplifier

VI should be taken small to restrict theoperation in almost linear segment of thetransfer curve.

The output voltage Vo will be then proportionalto the input voltage Vi.

The Linear Amplifier produces the same

waveform with the larger factor defined by thevoltage gain of the amplifier.

Since the slope is negative, the CS-amplifier is

an inverting Amplifier.


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Amplifier

If the amplitude of the input signal VI isincreased, the output signal will become

distorted since the operation will no longer berestricted to the saturation region of transfercurve.


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l i l i f


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Analytical Expressions of

Transfer Characteristics

Cut-off Region Vi < Vt Vo= VDD

Saturation Region Vi > Vt

Vo > Vi Vt

ID (Sat) = k(Vi - Vt)2/2

By putting the value of ID(sat) in the dc bias equation (VO =

VDD - IDRD), VO can be calculated.


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A l ti l E i f


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Analytical Expressions of

Transfer Characteristics Remaining critical points of VTC can be

calculated as follows:

Input Low Voltage (VIL)

Input High Voltage (VIH)

Midpoint Voltage (VM)

E i


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Exercise

Consider the following CS circuit. Constructthe Voltage Transfer Characteristic for the

case when kn(W/L) = 1mA/V2, Vt = 1V, RD =

18k and VDD = 10V.


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SATURATED ENHANCEMENT-ONLY

LOADED NMOS INVERTER

S t t d E h t O l


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Saturated Enhancement-Only

Loaded NMOS Inverter

In the previous section, we have discussed

Resistor Loaded NMOS Inverter.

In this section, the behaviour of an Inverter with

two Enhancement-Only NMOS transistors willbe studied.

This type of inverter is more practical than

resistor-loaded inverter since the resistor isthousands of times larger than a MOSFET.

Remember, any logic operation can be

implemented using just MOSFET devices.

O ti d h


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Operation: Saturated Enhancement-Only Loaded NMOS Inverter

The figure shows that the inverter is connected

with a Saturated Enhancement-Only NMOS

transistor as a Load device.

With the Gate and Drain of

the load NL connected,

VDS,L = VGS,L > VGS,L - VT,L

Thus the load device canonly operate in Saturation

mode.


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Operation: S t t d E h t


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When VIN > VT,O, the transistors NO and NL begin

to conduct equal drain currents.

As VDS,O VGS,O VT,O, NO is in Saturation mode.

ID,O (Sat) = ID,L (Sat)

kO (VGS,O VT,O)2 / 2 = kL (VGS,L VT,L)

2 / 2

Since VGS,O = VIN and VGS,L = VDD - VOUT

kO (VIN VT,O)2 / 2 = kL (VDD - VOUT VT,L)2 / 2

Solving the equation for VOUT, we have



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When VDS,O VGS,O VT,O , NO transistor is in

Triode region of operation.

NL transistor is still in saturation region of

operation.



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Graphical Representation of Voltage Transfer

Characteristics

ID,O = ID,L

VDS,L = VDD - VDS,O

ID,L = kL [(VDD VT,L) VDS,O]2 / 2

The above equation works in

similar manner as the loadline equation for the resistor-

loaded transistor.


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Operation: Saturated Enhancement


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Analytical Expressions of VTC

Triode Region

NL is in saturation region and NO is in Linear or Triode

region of operation. VGS,O > VT,O

VDS,O VGS,O VT,O

Operation: Saturated Enhancement-


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Remaining critical points of VTC can becalculated as follows:






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LINEAR ENHANCEMENT-ONLY

LOADED NMOS INVERTER


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Operation: Linear Enhancement-


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Operation: Linear Enhancement-Only Loaded NMOS Inverter

When VDS,O VGS,O VT,O , NO transistor is in

Triode region of operation.

NL transistor is also in Linear region of operation.



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Operation: Linear Enhancement-Only Loaded NMOS Inverter

Graphical Representation of Voltage Transfer Characteristics ID,O = ID,L VDS,L = VDD - VDS,O VGS,L = VGG - VDS,O

ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2]

ID,L = kL [(VGG - VDS,O VT,L) (VDD - VDS,O)2]- (VDD - VDS,O)

2 / 2]

The above equation works insimilar manner as the load

line equation for the resistor-

loaded transistor and Saturated

NMOSFET loaded transistor.


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Operation: Linear EnhancementOnly Loaded NMOS Inverter

The resulting curve is the transfer curve.

The output does not reach 0V as the inputincreased to the maximum value of supply voltage.

This can be confirmed

while looking at the family

curve of this type of transistor

(i.e. VIN = VDD).



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Cut-off Region

VIN = VGS,O

VGS,O < VT,O

VOH = VDD

In resistor-loaded transistor, VOH = VDD.

In Saturated-loaded NMOS, VOH = VDD - VT,L.



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Saturation Region VGS,O > VT,O

VDS,O VGS,O VT,O

VIN = VGS,O

VDS,L = VDD - VOUT VGS,L = VGG - VOUT



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Triode Region

NL and NOare in Linear or Triode region of operation.

VGS,O > VT,O VDS,O VGS,O VT,O



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pOnly Loaded NMOS Inverter



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pOnly Loaded NMOS Inverter


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Enhancement-Depletion Loaded


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p

NMOS Inverter

In the previous section, we have discussedLinear Enhancement-only NMOS Inverter.

In this section, the behaviour of Linear

Enhancement-Depletion loaded NMOSinverter will be studied.

The advantage of using this type of

inverter is that the output will be equal tothe supplied source voltage without thesecond VGG.


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Enhancement-Depletion Loaded


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p

NMOS Inverter

The figure shows that the inverter isconnected with a Enhancement-DepletionNMOS transistor as a Load device.

The Load can operate in theLinear and saturation

region of operation.

With the Gate and Sourceconnected together,

VGS,L = 0V.


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Operation: Enhancement-


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p

Depletion Loaded NMOS Inverter

When VIN > VT,O, the transistors NO and NL beginto conduct equal drain currents.

As VDS,O VGS,O VT,O, NO is in Saturation mode.

ID,O (Sat) = ID,L (Linear)kO (VGS,O VT,O)

2 / 2 = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2]

Apply the following substitutions: VGS,O = VIN

VGS,L = 0V VDS,L = VDD - VOUT



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p


When the output drops below VDD VT,L , VDS,L

becomes large enough for NL to enter the

saturation region.

ID,O (Sat) = ID,L (Sat)

kO (VGS,O VT,O)2 / 2 = kL [(VGS,L VT,L)

2 (1 + LVDS,L ) / 2

Since ID,L is less dependent on VDS,L , thus the drain current

will be constant with respect to the output (VDS,O). When VDS,O VGS,O VT,O , NO transistor is in Triode

region of operation.



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p


Graphical Representation of Voltage TransferCharacteristics ID,O = ID,L

VDS,L = VDD - VDS,O VDS,L = VDD VOUT

When Load is in Linear:

ID,L = kL [(VGS,L VT,L) VDS,L - VDS,L2 / 2]

ID,L = -kL [ VT,L (VDD - VDS,O)2]- (VDD - VDS,O)

2 / 2]

When Load is in Saturation:ID,L = kL [(VGS,L VT,L)

2 (1 + LVDS,L ) / 2



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The voltage transfer characteristic can be obtained

in the same graphical manner.

The curve for load transistor (NL) is non-linear.

VGS,O and VDS,O are read from the intersection ofoutput load curve with the family of curves. These

points are then mapped into the VGS,O and VDS,O

coordinate axes.



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The resulting curve is the transfer curve.

The output does not reach 0V as the inputincreased to the maximum value of supply voltage.

This can be confirmed

while looking at the family

curve of this type of

transistor (i.e. VIN = VDD).

Operation: Enhancement-Depletion


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p pLoaded NMOS Inverter


Cut-off Region

VIN = VGS,O

VGS,O < VT,O VOH = VDD

In resistor-loaded transistor, VOH = VDD.

In Saturated-loaded NMOS, VOH = VDD - VT,L.

In Linear-loaded NMOS, VOH = VDD.



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p pLoaded NMOS Inverter


Saturation Region VGS,O > VT,O

VDS,O VGS,O VT,O VIN = VGS,O

VDS,L = VDD - VOUT

VGS,L = 0V



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pLoaded NMOS Inverter


Triode Region

NL and NO are in Saturation and Linear region of

operation respectively. VGS,O > VT,O

VDS,O VGS,O VT,O



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Analytical Expressions of VTC Midpoint Voltage (VM)



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NMOS GATES

NMOS Gates


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In this chapter, we describe the design ofmulti-input NMOS logic gates such asNAND, NOR, complex AND-OR-Inverts

(AOI) and other special function logicgates.

Each of these gates has a single Load

device in the same fashion as the NMOSinverters.

NMOS NOR Gate


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The NMOS inverter with a resistor or MOSFETconnected as a load device can be made to

perform the logical NOR function.

This can be done by placing the additional

NMOS transistors in parallel with the outputNMOS transistor.

NMOS NOR Gate


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Each of the output N-channel MOSFET shouldhave the same channel width (W) and length (L)

to achieve the same value of VOL regardless of

which input is high.

We have discussed that Enhancement-DepletionNMOS inverter is more practical inverter than

any other kind.

NMOS NOR Gate


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Output High Voltage If both inputs of NMOS NOR gate are low, both

output transistors (NA and NB) will be cutoff.

The output will be unchanged from that of

inverters discussed in previous sections. For Enhancement-Depletion loaded NMOS

inverter, VOH = VDD.

For Saturated-Enhancement,

VOH = VDD VT,L

For Resistor /Linear Enhancement

VOH = VDD

NMOS NOR Gate


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Output Low Voltage If any of the inputs is high, a highly conductive

path from the output to ground is formed byenhancement of a drain-to-source channel.

Thus low voltage will be achieved at the output. Thus, logical NOR operation is achived.

This parallel output NMOS structure is referred toas a Parallel Pull-down as there are several pulldown paths from the output to ground.

NMOS NOR Gate


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How VOL can be improved? The output low voltage is inversely dependent

upon ko.

Single Input Voltage High

If single input voltage is high, the VOL will be same asof single input inverter.

NMOS NOR Gate


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How VOL can be improved? Both Input Voltages high

If both inputs are high, both transistors will conductdrain current.

If both input voltages are same and processtransconductance parameter is same, the outputtransistor can be considered to act as a single N-channel MOSFET.

The device transconductance parameter (k0) will be:

NMOS NOR Gate


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Since the VOL is inversely proportional to kO, the VOLwill be reduced for an NMOS NOR gate with twoinputs high.

More inputs can be added by adding more paralleloutput NMOS transistors. In this way, the VOL can be

improved (i.e. more close to 0V) by making multipleinputs high.

VOH is not dependent on increasing number of inputs.

NMOS NOR Gate


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Input Low Voltage (VIL) The input low voltage of NOR gates is same as

those for the corresponding single inverter.


The input high voltage of NOR gates is same asthose for the corresponding single inverter.

NMOS NAND Gate


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The NMOS inverter with a resistor or MOSFETconnected as a load device can be made to

perform the logical NAND function.

This can be done by placing the additional

NMOS transistors in series with the outputNMOS transistor.

The gate terminal of each

NMOS transistor is used as aNAND logic gate input.

NMOS NAND Gate


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Each of the input N-channel MOSFETshould have the same channel width (W)and length (L).

We have discussed that Enhancement-Depletion NMOS inverter is more practicalinverter than any other kind.

NMOS NAND Gate


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Output High Voltage VA Low, NA cutoff

If bottom transistor NA has low input gate voltage,then NA will be in cutoff state and the source

terminal of NB has no conductive path to ground. Thus regardless of the input state for NB, the NAND

gate must be in the output high state.

VB Low, NB cutoff

We consider VA in the input high state, NA will beactive and a conductive path exists from source ofNB to ground. Thus source of NB is at virtual groundsince VDS,A is very small due to zero ID,A.

NMOS NAND Gate


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NB is now acting like an inverter. Low input voltagemakes NB in cutoff state and no pull-down pathexists from the output to the virtual ground.

Thus, the high output state is noticed at the output.

Thus, either input low results in output high state andthe NAND functionality will be achieved.

The output high voltage will be unchanged from otherNMOS inverters.

VB Low, VA Low Both inputs low yields the output high state verifying the

logical NAND operation.

NMOS NAND Gate


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Output Low Voltage For VA = VGS,A is high, the NA will be active and a

conductive path exists from source of NB toground. Thus source of NB is at virtual ground.

For VB is high, the NB is also active and aconductive path exists from the output to thevirtual ground.

Thus the NAND gate is in the output low state due

to the pull-down path available from output tovirtual ground.

NMOS NAND Gate


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How VOL can be improved? The VOL is degraded (increased) from the single

inverter by following the stacked pull-downconfiguration of NMOS transistors.

There will be a longer pull-down path from theoutput to ground. That means the length of thetwo channels will be added.

If width and process transconductance

parameters remain constant, then

NMOS NAND Gate


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Since VOL is inversely proportional to devicetransconductance parameter (ko), low value of kowill increase the VOL.

A greater channel width is needed for each

transistor to compensate this degradation of VOL. Due to this degradation of performance, the

NMOS NOR gates are preferred over NMOSNAND gates.

NMOS NAND gates can accommodate more thantwo inputs (ideally up to 3) by simply adding moreNMOS transistors in series to the pull-downsequenced transistors.

NMOS NAND Gate


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Input Low Voltage (VIL) The input low voltage of NAND gates is dependent

on ko.


The input high voltage of NAND gates is dependenton ko.

NMOS OR/AND Gate


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OR Gate: can be obtained using NMOS logicfamilies by simply connecting inverter to theoutput of NOR gate.

NMOS OR/AND Gate


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AND Gate: can be obtained using NMOS logicfamilies by simply connecting inverter to theoutput of NAND gate.

NMOS Complex Logic Gates


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Complex AND-OR invert logic gates can beconstructed by connecting NMOS transistorsin series and parallel combinations within the

same circuit. Class Work:Design the Enhancement-depletion loaded

NMOS logic gates for the following logic functions.

F = (AB + CD)

F = AB + CD F = ABC + D + EF

F = ((A+B)(C+D) + E(F+G))



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Following is the design of NMOS logic gateperforming logic function: (AB + CD)



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Following is the design of NMOS logic gateperforming logic function:

((A+B)(C+D) + E(F+G))



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Determine the logic function for the followingcircuit.

NMOS X-OR/X-NOR Gates


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Exclusive-OR and Exclusive NOR can easily beobtained using NMOS transistors.

VA = High and VB = High

When both inputs are high, the output of the X-OR willbe low. The output of X-NOR will be high.

VA = High and VB = Low

When VA is high and VB is low, the output of the X-OR

will be high. The output of X-NOR will be low. VA = Low and VB = High

When VA is low and VB is high, the output of the X-ORwill be high. The output of X-NOR will be low.

NMOS X-OR/X-NOR Gates


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VA = Low and VB = Low When both inputs are low, the output of the X-OR will

be low. The output of X-NOR will be high.



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Determine the logic function for the followingcircuit.

NMOS Transmission Gates


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NMOS device acts as a Switch by toggling thegate input voltage ON and OFF.

When the Gate voltage is high, the NMOS switch

is ON and when Gate voltage is low, the NMOS

switch is OFF.

This analysis offers the ability of transferring the

driving logic voltage from one side of NMOS

channel to the other side on CONDITION. NMOS switches are traditionally called

Transmission Gates or Pass.



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When VEN is high, the highly conductive pathfrom NT output to the source exists thattransfers the driving voltage VOUT to the input

VIN. This results in VOUT = VIN.



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When VEN is low, the NT is cutoff and the inputVIN is isolated from the output VOUT. Thus VINis floating.



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Example:

Design a Multiplexer (4x1) using NMOSTransmission gates.

digital electronics 1

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