digital design methodology

8/3/2019 Digital Design Methodology

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Digital Design Methodology


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Conventional System Design C

lassical design methods relied on schematicsand manual methods to design a circuit

Such as Solution of Boolean expression i.e.

Boolean Algebra

K-Map

STGs ASM

ASMDs


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Digital Design Technique

The Basic of digital design concept is computerbased languages (HDLs) to design circuits of

enormous size and complexity.

The Complex Circuits are described as the

function of a computer program which then

converts to the complex circuits


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Advantages

No team of engineers can correctly design and manage, bymanual methods, the details of state-of- the-art integratedcircuits (ICs)

Language-based designs are portable and independent oftechnology, allowing design teams to modify and re-use

designs to keep pace with improvements in technology. As physical dimensions of devices shrink, denser circuits

with better performance can be synthesized from anoriginal digital model.

The most significant gain that results from the use of an

HDL is that a working circuit can be synthesizedautomatically from a language-based description,bypassing the laborious steps that characterize manualdesign methods (e.g., logic minimization with Karnaughmaps).


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Commonly Used HDLs

Verilog (ASIC & FPGA)

VDHL (ASIC & FPGA)

Spice (Analog Circuit Design)

Verilog-A (Hybrid) System C (Hybrid)

Superlog (Hybrid)


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Design Flow


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Design Specification

The design flow begins with a written specification forthe design.

The specification document can be a very elaboratestatement of functionality, timing, silicon area, powerconsumption, testability, fault coverage, and othercriteria that govern the design.

At a minimum, the specification describes thefunctional characteristics that are to be imple- mentedin a design.

Typically, state transition graphs, timing charts, andalgorithmic- state machine (ASM) charts are used todescribe sequential machines, but interpretation of thespecification can be problematic.


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Design Partition

In today's methodologies for designing ASICs andFPGAs, large circuits are partitioned to form an

architecture a configuration of interacting

functional units, such that each is described by abehavioral model of its functionality.

The process by which a complex design is

progressively partitioned into smaller and

simpler functional units is called top-down

design or hierarchical design.

HDLs support top-down


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Design entry

Design entry means composing a language-baseddescription of the design and storing it in anelectronic format in a computer.

Modern designs are described by hardwaredescription languages, like Verilog, because it takessignificantly less time to write a Verilog behavioraldescription and synthesize a gate-level realization of alarge circuit than it does to develop the gate-levelrealization by other means, such as bottom-up

manual entry. Synthesis tools create an optimal internal

representation of a circuit before mapping thedescription into the target technology.


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Simulation and Functional Verification

The functionality of a design is verified either bysimulation or by formal methods. Our discussion

will focus on simulation that is reasonable for the

size of circuits we can present here. The designflow iterates back to Step 3 until the functionality

of the design has been verified.

The verification process is threefold; it includes

(1) development of a test plan,

(2) development of a test bench, and

(3) execution of the test.


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(1) Test Plan Development

A carefully documented test plan is developed

to specify what functional features are to be

tested and how they are to be tested. For

example, the test plan might specify that the

instruction set of an arithmetic and logic unit

(ALU) will be verified by an exhaustive

simulation of its behavior, for a specific set ofinput data.


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(2) Testbench Development

The testbench is a Verilog module in which the unit undertest (UUT) has been instantiated, together with patterngenerators that are to be applied to the inputs of the modelduring simulation.

Graphical displays and/or response monitors are part of the

testbench. The testbench is documented to identify the goals and

sequential activity that will be observed during simulation(e.g., "Testing the opcodes").

If a design is formed as an architecture of multiplemodules, each must be verified separately, beginning withthe lowest level of the design hierarchy, then the integrateddesign must be tested to verify that the modules interactcorrectly.


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(3) Test Execution and Model Verification

The testbench is exercised according to the test

plan and the response is verified against the

original specification for the design, e.g. does the

response match that of the prescribed ALU? This step is intended to reveal errors in the

design, confirm the syntax of the description


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Design Integration and Verification

After each of the functional subunits of a

partitioned design have been verified to have

correct functionality, the architecture must be

integrated and verified to have the correctfunctionality.

This requires development of a separate

testbench whose stimulus generators exercisethe input-output functionality of the top-level

module, monitor port and bus activity across

module


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Presynthesis Sign-Off

A demonstration of full functionality is to be

provided by the testbench, and any dis-

crepancies between the functionality of the

Verilog behavioral model and the design

specification must be resolved. Sign-off occurs

after all known functional errors have been

eliminated.


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Gate-Level Synthesis and Technology

Mapping

After all syntax and functional errors have beeneliminated from the design and sign- off hasoccurred, a synthesis tool is used to create an

optimal Boolean description and compose it inan available technology.

In general, a synthesis tool removes redundantlogic and seeks to reduce the area of the logicneeded to implement the functionality andsatisfy performance (speed) specifications. Thisstep produces a netlist of standard cells or a

database that will configure a target FPGA.


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Continued


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Example

Design Specification

Design a 4-bit ripple carry adder using 1 bit

full adder through Behavioral Modeling inVerilog HDL

There are two way

ByC

lassical Method By Digital Design Techniques

digital design methodology

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