digital counters

APHY 104 Exercise 5. Flip-Flops and Sequential Circuits (Counters)

Methodology

*Materials: 74LS112 ICs (JK), basic logic gate ICs, training board, wires

Each counter required for this exercise was first designed manually before implementation. The

desired counting sequences were initially determined and the state diagrams were drawn. We

then proceeded to create excitation tables for each counter, from which we constructed the

corresponding Karnaugh maps. The necessary flip flop inputs were then determined by

simplifying the logic expressions from the Karnaugh maps. After implementing each circuit, the

desired counting function was then verified by the laboratory instructor.

Results and Discussion

It should be noted early that all counters designed and implemented during this activity used JK

flip flops, but as a T flip flop. As such, the J and K inputs were the same at all times.

4-bit Synchronous Binary Counter

No. of Flip flops used: 4

Counting sequence: 0000 – 1111 (resets to 0000 after 1111)

Present State Next State Inputs

D C B A D C B A TD TC TB TA

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 1 0 1 0 0 0 1 1

1 0 1 0 1 0 1 1 0 0 0 1

1 0 1 1 1 1 0 0 0 1 1 1

1 1 0 0 1 1 0 1 0 0 0 1

1 1 0 1 1 1 1 0 0 0 1 1

1 1 1 0 1 1 1 1 0 0 0 1

1 1 1 1 0 0 0 0 1 1 1 1

Table 1. Excitation Table for the binary counter

Figure 1. Karnaugh maps for the flip flop states.

Getting the simplified expressions from the K-maps, we have:

TD = ABC, TC = AB, TB = A, TA = 1

The obtained expressions were then used for the design of the counter. For the TD and TC inputs,

we used an AND gate and a triple-input AND gate respectively.

4-bit Synchronous Decade Counter


Counting sequence: 0000 – 1001 (resets to 0000 after 1001)

Creating an excitation table and K-maps for the decade counter would only yield the same logic

expressions for the flip flop inputs (TD = ABC, TC = AB, TB = A, TA = 1). But unlike the binary counter,

we only want the circuit to count from 0 (0000) until 9 (1001). It is then necessary to clear the

flip flops when the count reaches 10 (1010) and resets back to 0. This was achieved by using a

NAND gate (74LS00) having the outputs of the A and C flip flops as its inputs. The output of the

NAND gate was then connected to the CLR terminals of all flip flops. The said NAND output is 1

when the count is 1010 (first and third LED) and hence the counting is cleared.

3-bit Synchronous 0-2-4-7 Counter


As a T flip flop, the JK flip flop required the same inputs for the J and K terminal. This inputs were

again determined using Karnaugh maps and getting the simplified expressions. The designed

counter uses only 3 flip flops and a triple input AND gate (74LS11), with all CLR terminals

connected to the AND output. Upon reaching 7 (111), the counter resets back to 0 since the AND

gate activates the CLR terminals.

DC/BA oo o1 11 1o

oo

o1 1

11 1

1o

TD

DC/BA oo o1 11 1o

oo 1

o1 1

11 1

1o 1

TC

DC/BA oo o1 11 1o

oo 1 1

o1 1 1

11 1 1

1o 1 1

TB

DC/BA oo o1 11 1o

oo 1 1 1 1

o1 1 1 1 1

11 1 1 1 1

1o 1 1 1 1

TA

Summary and Conclusion

This activity basically employed the ability of flip flops to hold a specific state indefinitely. The

counters designed used a cascaded arrangement of the ICs to operate, with the number of flip

flops used based on the desired counting sequence.

The counters present in this activity were all made using flip flops (JK as T) and basic IC logic gates.

The said counters were all designed using excitation tables and Karnaugh maps, followed by the

actual implementation on the training board. The final circuits were fully functional and followed

the required counting sequence, as verified by our laboratory instructor.

References

1. Maini, A. K., Digital Electronics: Principles, Devices, and Applications. 2007

digital counters

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