Czech Technical University in Prague – Faculty of Electrical Engineering

Digital Control of Electric Drives

Ver.1.00

Special Peripherals for Control

J. Zdenek 2017

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Electric drive structure

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Control computer structure

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Control computer structure (with FPGA support)

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Interrupt controller

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Interrupt controller principle

Interrupt Request

Maskable Interrupt Enable/Disable

Interrupt Flag

Interrupt Enable

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Using timer and interrupt for period measurement

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Analog to Digital converter in embedded computer

Ana

log I

np

uts

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Quadrature encoder signals

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Precise pulse signal period measurement (Capture Unit)

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Precise pulse signal generation (Compare Unit)

CR

Prescaler Timer

Timer Count

Comparator

Compare Register

Program

Program

Event

Generator

Int

Event Register

Program

TC

ER

Clock

Output

INIT

RET

ISR

RET

Int

T0 T1 T2 T3

∆T1

ER ←

CR ← X+T1

ER ←

CR ← TC+T0

ISR

RET

X ← TC+T0 X ← X+T1

ER ←

CR ← X+T2

X ← X+T2

∆T2

Int

ISR

RET

ER ←

CR ← X+T3

X ← X+T3

∆T3

Int

time

Output

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Pulse signal generation (Carrier and Modulation wave)

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Pulse signal generation (Carrier and Modulation wave)

Digital Control of Electric Drives

Special Peripherals for Control

END

Czech Technical University in Prague – Faculty of Electrical Engineering