digital calibration of dac unit elements mismatch in...

34 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 1, JANUARY 2016

Digital Calibration of DAC Unit ElementsMismatch in Pipelined ADCs

Hamidreza Mafi, Mohammad Yavari, Member, IEEE, and Hossein Shamsi

Abstract—This paper presents a statistics-based digital back-ground calibration technique for digital-to-analog converter(DAC) unit elements mismatch in pipelined analog-to-digital con-verters (ADCs). The proposed calibration method continuouslymeasures and digitally mitigates sub-DAC (SDAC) mismatch er-rors in background during the normal data-conversion operation.In this method, the probability density function (PDF) of the sub-ADC (SADC) quantization error is analyzed using a two-levelpseudorandom noise (PN) sequence in order to extract and re-move SDAC mismatch errors. Behavioral simulation results areprovided for a 12-bit pipelined ADC architecture to validate the ef-fectiveness of the introduced method. Simulation results show thatthe signal-to-noise and distortion ratio (SNDR) is improved from48.4 dB to 70.2 dB using the proposed calibration technique. Thisscheme converges after approximately 30 × 106 clock cycles.

Index Terms—Adaptive signal processing, analog-to-digital con-verters (ADCs), digital calibration, digital-to-analog converters,pipelined ADCs.

I. INTRODUCTION

P IPELINED analog-to-digital converters (ADCs) arewidely used in high-speed low-power communication sys-

tems. In order to design high-speed pipelined ADCs, it is pre-ferred to use wide-bandwidth amplifiers with insufficient gain(e.g., single-stage or open-loop amplifiers) as the residue am-plifier [1]–[6]. Multi-bit switched-capacitor digital-to-analogconverters (DACs) are extensively employed to implement thesub-DAC (SDAC). A multi-bit switched-capacitor SDAC isoften realized using nominally identical DAC unit elements thatshare a common summing node [1], [7]–[14]. In low-powerpipelined ADCs, unit capacitors of SDACs are chosen accord-ing to the thermal noise restrictions rather than the matchinglimitations so as to reduce the power consumption of theresidue amplifier [6]–[8]. Unfortunately, the residue amplifiernon-idealities and mismatch among nominally identical DACunit capacitors restrict the signal-to-noise and distortion ratio(SNDR) of a pipelined ADC to less than 60 dB [7]–[12]. In

Manuscript received August 19, 2015; revised November 6, 2015; acceptedNovember 19, 2015. Date of current version February 15, 2016. This paper wasrecommended by Associate Editor A. M. A. Ali.

H. Mafi is with the Electrical Engineering Department, University of Zanjan,Zanjan, Iran (e-mail: [email protected]; [email protected]).

M. Yavari is with the Integrated Circuits Design Laboratory, Departmentof Electrical Engineering, Amirkabir University of Technology, Tehran 15914,Iran (e-mail: [email protected]).

H. Shamsi is with the Faculty of Electrical Engineering, K. N. Toosi Uni-versity of Technology (KNTU), Tehran, Iran (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2015.2512700

turn, the residue amplifier non-idealities and SDAC capacitorsmismatch need to be compensated to enhance the resolution ofthe pipelined ADC to greater than 60 dB. Hence several digitalcalibration methods have been developed to cancel the residueamplifier non-idealities and SDAC capacitors mismatch and toimprove the resolution of pipelined ADCs [6]–[21].

Digital calibration techniques can be categorized into back-ground and foreground methods. Foreground calibration tech-niques interrupt the ADC normal conversion operation, whereasbackground calibration schemes operate during the normaldata-conversion operation of ADC without the need for anyinterruption. Digital background calibration techniques havebeen employed to correct the residue amplifier non-idealities[11]–[14], [16]–[18], SDAC capacitors mismatch [8]–[10],[17], [19], and sub-ADC (SADC) offset errors [20]. Most ofresidue amplifier calibration techniques use a pseudorandomnoise (PN) sequence to measure and remove the conversionerrors [11]–[14]. The DAC noise cancellation (DNC) techniqueintroduced in [10] is widely used to remove the errors causedby mismatch among SDAC unit elements and improve theaccuracy of pipelined ADCs, simultaneously with residue am-plifier calibration methods [11]–[15]. This technique exploits adynamic element matching (DEM) algorithm that requires com-plex digital circuits [10]. Unfortunately, in high-speed pipelinedADCs, the propagation delay of the DEM method can be critical[9]. The SDAC capacitors mismatch calibration techniquesin [8] and [19] have fast convergence rates; however, thesemethods can only be employed to remove SADC mismatcherrors in the first stage of a pipelined ADC and also need anextra ADC.

This paper introduces a statistics-based digital backgroundcalibration technique for DAC unit elements mismatch inpipelined ADCs. The proposed method continuously extractsand digitally minimizes the conversion errors arising fromSDAC capacitors mismatch. Since this technique is fully com-patible with the residue amplifier calibration techniques in [11]and [12], it can be used concurrently with these calibrationmethods in contrast to the schemes of [8], [9], and [19]. Besides,the proposed scheme can be applied to as many stages as neededto mitigate the errors due to SDAC unit elements mismatch andit doesn’t require an extra ADC as opposed to the methods in[8] and [19]. The introduced algorithm alleviates the need forthe complex DEM algorithm with a critical propagation delayhence it can be exploited in high-speed pipelined ADCs incontrast to the technique in [10].

The remainder of the paper is organized as follows. Section IIbriefly reviews the structure of the pipelined ADC and digitalcancellation mechanism for SDAC unit elements mismatch.

1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

MAFI et al.: DIGITAL CALIBRATION OF DAC UNIT ELEMENT MISMATCH IN PIPELINED ADCs 35

Fig. 1. Architecture of a conventional pipelined ADC.

Section III presents the proposed statistics-based digital back-ground estimation technique for SDAC unit elements mismatch.Simulation results are provided in Section IV. Discussions arepresented in Section V. Finally, Section VI concludes the paper.

II. STRUCTURE OF PIPELINED ADCS AND DIGITAL

CANCELLATION MECHANISM FOR SDACUNIT ELEMENTS MISMATCH

Fig. 1 shows the structure of a conventional pipelined ADC,which is comprised of N low resolution pipeline stages. Forpresentation simplicity, all signals are scaled with the referencevoltage; therefore, the range of all signals is bounded to theinterval [−1, 1], similar to [9]–[14]. In addition, we concentrateon the calibration of SDAC mismatch in the first stage; hence,the remaining components of the first stage (i.e., the residueamplifier and the SADC) and the backend ADC comprised ofall the following (N − 1) stages are assumed to be ideal, as in-dicated in Fig. 1. In practice, the residue amplifier non-idealitiescan also be mitigated through a separate calibration mechanism,such as [11]–[14]. Nonetheless, imperfections in all the stagesconsisting of non-idealities of the residue amplifiers, SADCs,and SDACs are considered in the simulations of Section IV.

The SADC consists of L comparators. The input voltage,Vin, is compared with a set of fixed voltages ranging from −1to 1 in steps of ΔQS = 2/L, where ΔQS is the quantizationstep of the SADC [22], [23]. From the signal processing pointof view, the output of the ith comparator, dai, is either 1/2 or−1/2, where i = 1, . . . , L. The outputs of the SADC compara-tors, {da1, . . . , daL}, form the SDAC input, Da. The digitalmismatch correction (DMC) block converts its thermometerencoded input, Da, to a signed binary encoded output. TheDMC block is comprised of L digital weights, g1, . . . , gL. Theoutputs of the weights are obtained by multiplying the digitalweights, g1, . . . , gL, and their corresponding SADC outputs,da1, . . . , daL, respectively, and these outputs are then addedtogether to form the first stage digital output as

Dst1 =

L∑i=1

gi · dai. (1)

In traditional pipelined ADCs, the SDAC also consists ofL DAC unit elements, as shown in Appendix A, and the SADCoutputs, da1, . . . , daL, are directly applied to their correspond-ing 1-bit DAC elements, Δ1, . . . ,ΔL, respectively, where Δi

represents the step size of the ith 1-bit DAC element. Thus, theoutput of the ith 1-bit DAC element is equal to (Δi · dai). Inthe absence of the SDAC elements mismatch, the step size of allthe DAC unit elements would be identical to ΔQS. The SDACoutput voltage, Vd, is the summation of all the outputs of the1-bit DAC elements. The voltage Vd can be expressed as

Vd =

L∑i=1

Δi · dai. (2)

In ideal behavior, the SDAC output voltage can be represented by

Vd = Vin + eAD (3)

where eAD denotes the SADC quantization error. It can beproved that the probability density function (PDF) of the SADCquantization error, pEAD(eAD), is ideally restricted to the inter-val −ΔQS/2 < eAD < ΔQS/2 [22], [23]. In the remainder ofthe paper, the PDF of the SADC quantization error is supposedto be approximately uniform so as to clarify the presentation[see Section V-C]. The residue voltage is defined as following:

Vres = Vin − Vd. (4)

From (3) and (4), Vres is ideally equal to −eAD. Afterwards, theresidue voltage is amplified by the residue amplifier in order toproduce the output voltage as Vo1 = gA · Vres, where gA standsfor the residue amplifier gain. Ideally, the residue amplifierlinearly scales the residue voltage to the interval [−1, 1] [11].The voltage Vo1 is then quantized by the backend ADC togenerate the digitized output as Do1 = Vo1 + eBE, where eBE

denotes the quantization error of the backend ADC. In theremainder of the paper, eBE is omitted to simplify the presenta-tion similar to [9]–[14]. The digitized residue, Dres, is definedas the multiplication of the digitized output and the digitalcorrection weight, gD (i.e., Dres = Do1 · gD). In the ideal case,


Fig. 2. Pipelined ADC with the proposed SDAC mismatch calibration technique.

the digitized residue is the digital format of the residue voltage;therefore, the digital correction weight must be set to g−1

A .The ADC digital output, Dout, is identical to Dst1 +Dres,

as illustrated in Fig. 1. Hence it follows from (1), (2), and (4)that the ADC digital output is given by:

Dout = Vin +

L∑i=1

(gi −Δi) · dai. (5)

In the desired case, the digital output needs to be the digitalformat of the ADC input voltage (i.e., Dout = Vin). Hencethe DMC digital weights must be adjusted as gi = Δi fori = 1, . . . , L. In contrast, any deviation of the digital weightsfrom their corresponding SDAC step sizes (i.e., gi �= Δi fori = 1, . . . , L), leads to harmonic distortions in the ADC output[10], [13]. In reality, the SDAC step sizes are not known[10], [13]. As a result, the digital weights must be determinedduring the normal data-conversion operation. Accordingly, themain task of the digital SDAC unit element mismatch calibra-tion techniques is to continuously estimate the SDAC step sizesand to digitally adjust the digital weights of the DMC block inthe background during the normal conversion process.

III. STATISTICS-BASED DIGITAL BACKGROUND

ESTIMATION TECHNIQUE FOR SDAC UNIT

ELEMENTS MISMATCH

The modifications to the conventional architecture of thepipelined ADC are indicated in Fig. 2. As shown in the figure,the proposed calibration scheme is comprised of the digitalelement selection (DES) method to inject a two-level PN se-quence (i.e., PN ∈ {−1/2, 1/2}) into the residue voltage andthe statistics-based digital mismatch estimation (SDME) tech-nique to measure the SDAC step sizes. The estimated SDACstep sizes are then used by the DMC block to eliminate theconversion errors. Besides, the PN sequence is independent ofthe SADC quantization error. The presented scheme exploitsan SDAC with L+ 1 1-bit DAC elements, a DMC blockwith L+ 1 digital weights, and an L-level SADC, as depictedin Fig. 2.

Fig. 3. Structure of the DES block.

A. Digital Element Selection Algorithm

The DES block selects one of the 1-bit DACs according toa selection number, S, and injects the PN sequence into theresidue voltage through the chosen 1-bit DAC element, similarto [9], at each iteration k, where k stands for iteration-indexof the technique [see Section III-C]. The DES block consists ofL+ 1 switches, as depicted in Fig. 3. The SADC output bus andthe PN sequence together form the input set of the DES block,as shown in Fig. 2. All the switches share the PN sequence andthe selection number, S. The operation of the ith switch (SWi)is defined as

xi =

⎧⎪⎨⎪⎩

PN, if i = S

dai, if i < S,

dai−1, if i > S.

i = 1, . . . , L+ 1 (6)

It follows from (6) that the output of the ith switch with i < Sis connected to dai and with i > S it is connected to dai−1. Fur-thermore, PN is passed to the output of the Sth switch. It can beverified that the input set {da1, . . . , daS−1} is directly passed to


the output set {x1, . . . , xS−1} and the input set {daS, . . . , daL}is directly connected to the output set {xS+1, . . . , xL+1} aswell. The SDAC output, Vd, is the summation of all the 1-bitDAC elements, represented by

Vd =

S−1∑i=1

Δi · dai +ΔS · PN +

L+1∑i=S+1

Δi · dai−1 (7)

and the digital output of the first stage is also expressed as

Dst1 =

S−1∑i=1

gi · dai + gS · PN +

L+1∑i=S+1

gi · dai−1. (8)

With the addition of the PN sequence through the Sth 1-bitDAC element, the residue voltage is given by

Vres = −eS −ΔS · PN S = 1, . . . , L+ 1 (9)

where eS is the quantization error associated with the Sth 1-bitDAC element, which can be represented by

eS = −Vin +

(S−1∑i=1

Δi · dai +L+1∑

i=S+1

Δi · dai−1

). (10)

As seen from (9), the DES block adds the PN sequence tothe residue voltage. The SDME block exploits the injectedterm ΔS · PN (S = 1, . . . , L+ 1) to extract the step size of theSth 1-bit DAC element. Moreover, the term eS (S = 1, . . . ,L+ 1) is not a function of the PN sequence. In the absenceof SDAC unit elements mismatch, it can be proved that eS(S = 1, . . . , L+ 1) is equal to eAD. Due to the fact that theSDAC mismatch errors are practically below 1% and the SDMEmethod doesn’t require the exact probability distribution of eS(S = 1, . . . , L+ 1); consequently, the PDF of eS is consideredequal to the probability distribution of the SADC quantizationerror in order to clarify the presentation.

Since the introduced technique evaluates the residue voltagePDF using the pseudorandom noise sequence, the conditionalprobability density functions (CPDFs) of the residue voltagefor the modes PN = 1 and PN = −1 must be investigated. Inthis design, the pseudorandom noise sequence has the propertyP (PN = 1) = P (PN = −1) = 0.5, where P (x) denotes theprobability function of x. It follows from (9) that the residuevoltage is just a shifted version of the SADC quantization error,pEAD(eAD), depending on the two possible states of PN. There-fore, the residue voltage CPDFs can be expressed as functionsof the probability distribution of the SADC quantization error.As the SADC quantization error is distributed inside the interval[−ΔQS/2,ΔQS/2], from (9), it can be shown that the residuevoltage CPDF for the state PN = 1, is defined as

pVRES(Vres|PN = +1) = pEQ(−Vres −Δi/2) (11)

over the range [−(Δi +ΔQS)/2, (ΔQS −Δi)/2] and for thecase PN = −1, it is defined as

pVRES(Vres|PN = −1) = pEQ(−Vres +Δi/2) (12)

Fig. 4. (a) SADC quantization error distribution; (b) residue voltage PDFfor PN = +1 corresponding to the ith 1b DAC; (c) residue voltage PDF forPN = −1 corresponding to the ith 1b DAC.

inside the interval [(Δi −ΔQS)/2, (Δi +ΔQS)/2]. It followsfrom (11) and (12) that pVRES(Vres|PN = −1) is also a func-tion of pVRES(Vres|PN = +1) as:

pVRES(Vres|PN = −1) = pVRES(Vres −Δi|PN = +1). (13)

Fig. 4(b) and (c) demonstrate the CPDFs pVRES(Vres|PN=+1)and pVRES(Vres|PN = −1) corresponding to the PDF of theSADC quantization error depicted in Fig. 4(a), respectively,when PN is injected into the residue voltage through the ithDAC element. With the injection of the PN sequence, it followsfrom (11) and (12), and the independence of the PN sequencefrom the SADC quantization error that the residue voltage PDFis distributed from −(Δi +ΔQS)/2 to (Δi +ΔQS)/2.

It follows from (9) that without the addition of the PNsequence, the residue voltage is identical to −eAD and it isbounded to the interval [−ΔQS/2,ΔQS/2]; hence the nominalgain of the residue amplifier needs to be identical to 2/ΔQS soas to limit the output voltage inside the range [−1, 1]. In con-trast, with the injection of the PN sequence, the residue voltageis restricted to the interval [−(Δi +ΔQS)/2, (Δi +ΔQS)/2];as a consequence, the nominal gain of the residue amplifierneeds to be equal to 2/(Δi +ΔQS) in order to scale the outputvoltage to the interval [−1, 1]. In Appendix D, it is brieflyexplained that how the nominal gain of the residue amplifierand the SADC levels are selected in practice.

B. Statistics-Based Digital Mismatch Estimation Technique

The block diagram of the proposed SDME technique isshown in Fig. 5. The SDME block estimates the SDAC stepsizes. It is comprised of L+ 1 mismatch estimation (ME)channels. Each of the ME channels separately evaluates theprobability distribution of the SADC quantization error usingthe PN sequence in order to iteratively extract the SDAC stepsizes. All the ME channels share the signals S and PN. Ateach iteration, only one of the channels is active according tothe number S (the Sth ME channel). The set of the L+ 1estimated SDAC step sizes, G = {g1, . . . , gL+1}, is used by theDMC block to mitigate conversion errors caused by the SDAC


Fig. 5. Architecture of the SDME block.

mismatch, as depicted in Fig. 2. In other words, the DMCdigital weights are the estimated SDAC step sizes determinedby the SDME block.

In the absence of non-ideal circuit behavior, the digitizedresidue is the digital representation of the residue voltage. Forthis reason, the digitized residue CPDFs are equal to the residuevoltage CPDFs as well. In turn, the digitized residue CPDFs areideally represented by

pDRES(Dres|PN = +1) = pVRES(Dres|PN = +1) (14)

pDRES(Dres|PN = −1) = pVRES(Dres|PN = −1). (15)

It follows from (14) and (15) that pDRES(Dres|PN = −1) isalso a shifted version of pDRES(Dres|PN = +1) as following:

pDRES(Dres|PN=−1) = pDRES(Dres−Δi|PN=+1) (16)

within the interval −Δi < Dres < 0.It will be shown that the probability of a digitized residue

sample being less than −Δi/2 (i = 1, . . . , L+ 1) for the modePN = +1 is equal to the probability of a digitized residue sam-ple being less than Δi/2 for the case PN = −1. In order to ver-ify and exploit this feature, the estimation errors are defined as

EEi = EE+,i − EE−,i i = 1, . . . , L+ 1 (17)

where

EE+,i=P (−(ΔQS+Δi)/2<Dres<−gi/2|PN=+1) , (18)

EE−,i=P ((Δi −ΔQS)/2 < Dres < gi/2|PN = −1) (19)

where P (x1 < X < x2|PN) denotes the probability of hap-pening the event x1 < X < x2 on condition the PN sequence,which is defined as follows:

P (x1 < X < x2|PN) =

x2∫x1

pX(x|PN)dx. (20)

In (18) and (19), EE+,i and EE−,i represent the probability ofa digitized residue sample being less than −gi/2 for the state

Fig. 6. Digitized residue distribution: (a) For the case gi < Δi; (b) for the casegi = Δi; (c) for the case gi > Δi.

PN=+1 and the probability of a digitized residue sample beingless than gi/2 for the mode PN = −1, correspondingly, wheregi stands for the ith estimated SDAC step size. The estimationerrors can be expressed as following [see Appendix B]:

EEi =

−gi/2∫−Δi+gi/2

pDRES(Dres|PN= +1)dDresi=1, . . . , L+1.

(21)

From (21), it follows that

1) When gi<Δi, then the upper limit, −gi/2, is greater thanthe lower limit,−Δi+gi/2, hence EEi>0 [see Fig. 6(a)].

2) When gi = Δi, then the upper limit, −gi/2, is equal to thelower limit, −Δi + gi/2, hence EEi = 0 [see Fig. 6(b)].

3) When gi>Δi, then the upper limit, −gi/2, is less than thelower limit, −Δi + gi/2, hence EEi < 0 [see Fig. 6(c)].

Consequently, the estimation error, EEi (i = 1, . . . , L+ 1), isapproximately proportional to Δi − gi. In most applicationsof ADCs, the SADC quantization error PDF can be consideredapproximately uniform [see Section V-C]. For a uniformlydistributed SADC quantization error, it follows from (21) thatthe estimation errors are expressed as:

EEi = Δi − gi i = 1, . . . , L+ 1. (22)


In this special case, the estimation error, EEi (i = 1, . . . ,L+ 1), is linearly proportional to its corresponding differenceΔi − gi. If EEi (i = 1, . . . , L+ 1) is equal to 0 then it followsfrom (21) that the estimated SDAC step size, gi, is equal toΔi. In turn, the probability of a digitized residue sample beingless than Δi/2 (i = 1, . . . , L+ 1) for the state PN = −1 isidentical to the probability of a digitized residue sample beingless than −Δi/2 for the mode PN = +1.

It is worth mentioning that the estimation errors could beforced to zero using an adaptive search algorithm in order toobtain the SDAC step sizes. Unfortunately, the estimation errorsare not available during the normal conversion operation; there-fore, practical versions of the estimation errors are exploited as

IEi = IE+,i − IE−,i i = 1, . . . , L+ 1 (23)

where IEi, IE+,i, and IE−,i are the instantaneous format ofEEi, EE+,i, and EE−,i, correspondingly, given by

IE+,i = q(−gi/2−Dres|PN = +1) (24)

IE−,i = q(gi/2−Dres|PN = −1) (25)

where the operator q(x|PN = m) is also defined as

q(x|PN = m) =

{0, PN �= m

sgn(x), PN = m.(26)

In (26), the sign operator, sgn(x), is identical to 1 if 0 ≤ xand sgn(x) is equal to −1, otherwise [24]. In Appendix C, itis shown that the mean of the instantaneous estimation error,E[IEi] (i = 1, . . . , L+ 1), is equal to the estimation error, EEi.Furthermore, EEi (i = 1, . . . , L+ 1) is also approximatelyproportional to Δi − gi. For these reasons, in this design,an iterative search algorithm is exploited to determine theestimated SDAC step sizes. The update equations are given by

gi(n+ 1) = gi(n) + μ · IEi(n) · MEEi(S) i = 1, . . . , L+ 1(27)

where μ and n stand for the update step size and discrete-timeindex of the ADC [11], [21], [24], [25]. Besides, the operatorMEEi(S) = 1 if i = S and zero, otherwise. Hence the Sth MEchannel is only active, at each iteration. Fig. 7 demonstratesthe details of the ith ME channel. Because the ideal valuesof the DMC digital weights are equal to ΔQS, the estimatedSDAC step sizes are initialized to ΔQS by adding the constantΔQS to the output of the integrators as indicated in Fig. 7. Thisinitialization accelerates the convergence of the introducedalgorithm. As the desired values of the estimated SDAC stepsizes are finite and the dc gain of the discrete-time integratorsis infinite, the mean of the instantaneous estimation errors aremade identical to zero by the integrators in (27) [12], [24].Accordingly, the estimation errors approach zero after a numberof iteration steps and the estimated SDAC step sizes convergeto their actual values (i.e., gi → Δi for i = 1, . . . , L+ 1).In almost all adaptive calibration techniques, the steady-statevariations of the estimated SDAC step sizes are proportionalto the update step size, while the convergence time is inverselyproportional to the update step size; therefore, the update

Fig. 7. Detailed block diagram of the ith ME channel.

step size should be selected as a compromise between theconvergence time and the steady-state variations of theestimated SDAC step sizes [11], [12], [21], [24].

C. Complete Structure of the Proposed Technique

As detailed above, the DES switches and their correspondingSDME channels are iteratively chosen by the selection number,S. The selection number is updated every M clock cycleswhere M is an arbitrary integer (in this design, M = 32).Consequently, the iteration-index, k, is related to the discrete-time index as k = n/M . At each iteration, the Sth ME channeland the Sth DES switch are active for M clock cycles toestimate the step size ΔS according to the number S. In orderto estimate all the L+ 1 SDAC step sizes, the number Sneeds to be generated such that all the DES switches and theircorresponding SDME channels are selected repeatedly. For thisreason, an (L+ 1)-level number generator is used to produce Sin a repeating sequence as {1, 2, . . . , L+ 1}, at each iteration k.

IV. SIMULATION RESULTS

In order to validate the introduced digital background SDACunit elements mismatch calibration technique, behavioralsimulations in MATLAB/Simulink have been performed. Inthe simulations, an example 12-bit pipelined ADC is chosenthat is similar to [11] and [12]. The example ADC is comprisedof five 2-bit stages and a 4-bit flash ADC as the last stage, asshown in Fig. 8. In these simulations, the presented SDAC unitelement mismatch calibration technique (MCT) is employed tomeasure and cancel the conversion errors caused by the SDACunit elements in the first two stages, as indicated in Fig. 8. Thenominal gain of all the residue amplifiers is set to 4. As a result,all the digital correction weights (gD) need to be equal to1/4(= 1/gA). Since the SADC offsets are considered in all thestages of the ADC example, the output voltage range of eachstage needs to be intentionally reduced. In this ADC example,half the output voltage range of each of the stages is dedicatedto accommodate the SADC offset errors; accordingly, theideal output range, IOR, is considered identical to 0.5 [seeAppendix D]. For this reason, both the first two stages have a16-level SADC with the step size ΔQS = 2/16 and a 17-levelSDAC. Moreover, the next three stages have an 8-level SADCwith step size ΔQS = 2/8 and an 8-level SDAC. In addition,a full-scale sine-wave is exploited as the test input signal andthermal noise is included in each of the stages. The parameters


Fig. 8. The example pipelined ADC with the proposed calibration technique.

Fig. 9. The output spectrum of the ADC.

μ and M are set to 2× 10−6 and 32, respectively. In thesimulations, the following non-idealities are considered:

1) In all the stages, the gain error of the residue amplifiersare selected as independent Gaussian-distributed randomvariables with a mean of −1% and a standard deviationof 1%.

2) In the first two stages, the SDAC step sizes are chosen asindependent Gaussian-distributed random variables witha mean of 1/17 and a mismatch error of 1% standarddeviation and the SADC offsets are also chosen as in-dependent Gaussian-distributed random variables with astandard deviation of 0.05.

3) In the next three stages, the SDAC step sizes are chosen asindependent Gaussian-distributed random variables witha mean of 1/8 and a mismatch error of 1% standard devi-ation and the SADC offsets are chosen as independentGaussian-distributed random variables with a standarddeviation of 0.05.

4) In the last stage, the offset errors of the flash ADCare chosen as independent Gaussian-distributed randomvariables with a standard deviation of 0.05.

Fig. 9 depicts the output spectrum of the ADC before thecalibration, after the first stage calibration (i.e., just MCT 1 is

Fig. 10. INL and DNL of the 12-bit ADC before calibration.

Fig. 11. INL and DNL of the 12-bit ADC after the calibration of the first stage.

employed), and after the calibration of the first two stages (i.e.,MCT 1 and MCT 2 are exploited concurrently). Before the cal-ibration, the spurious-free dynamic range (SFDR) and SNDRare limited to 54.8 dB and 48.4 dB, respectively. After the firststage calibration, the SFDR and SNDR are improved to 71.2 dBand 56.7 dB, respectively. Finally, the SFDR and SNDR areenhanced to 78.5 dB and 70.2 dB, respectively, after the cal-ibration of the first two stages. Figs. 10–12 show the integralnonlinearity (INL) and differential nonlinearity (DNL) errors ofthe ADC before the calibration, after the first stage calibration,and after the calibration of the first two stages, correspond-ingly. After the calibration of the first two stages, the INLand DNL are improved from over 12 LSB and 1 LSB to lessthan 1 LSB and 0.5 LSB, respectively.


Fig. 12. INL and DNL of the 12-bit ADC after the calibration of the first twostages.

Fig. 13. Convergence of the SNDR.

Fig. 14. Convergence of the DMC digital weights.

Fig. 13 shows the convergence of the SNDR during theSDAC unit element mismatch calibration for three cases:

1) The calibration technique is only used in the first stage.2) The calibration technique is applied to the first two stages.3) The calibration technique is only applied to the first stage

and an ideal backend ADC is exploited instead of theremaining stages. In this case, the SNDR reaches 72.8 dBafter the calibration.

Fig. 14 demonstrates the convergence of the DMC digitalweights of the first two stages during the calibration. The SNDR

reaches 70 dB after approximately 30× 106 conversions. Theintroduced technique works well with sine-wave, Gaussian-distributed, and two-tone input signals with different ampli-tudes. Moreover, similar results are obtained with differentvalues of M .

V. DISCUSSIONS

It is worth mentioning that high-gain high-speed op-amps areoften difficult to design in advanced CMOS processes. For thisreason, it is preferred to use high-speed low-power amplifierswith insufficient gain as the residue amplifier. The gain of theresidue amplifier designed with a low-gain op-amp exhibitsnon-idealities and can be sensitive to temperature variationsand supply voltage drifts. In contrast, the mismatch among theSDAC unit elements tends to be constant (because capacitorsare typically constant over time and temperature). In Sections IIand III, it is supposed that the residue amplifier gain, gA, isaccurate and sufficiently stable over time. As a consequence,the digital correction weight, gD, is also considered identical tog−1A . Nevertheless, the residue amplifier gain variations cause

the digitized residue, Dres, to be identical to (gA/gD)Vres, andit follows from (9) that the digitized residue is represented by:

Dres= −(gAgD

)eS−

(gAgD

)ΔS · PN S=1, . . . , L+1. (28)

Hence it follows from (1), (2), and (4) that the ADC digitaloutput is also given by:

Dout =gAgD

Vin +

L+1∑i=1

(gi −

gAgD

Δi

)· dai. (29)

In this case, the SDME block continuously makes the DMCdigital weights, gi (i = 1, . . . , L+ 1), be equal to (gA/gD)Δi

so as to cancel the conversion errors at the digital output. Afterthe calibration, we have Dout = (gA/gD)Vin. Although theADC output has a gain error in this case, the ADC gain errordoesn’t have any severe effect in almost all ADC applications. Itmust be emphasized that the proposed technique is not sensitiveto the offset of the residue amplifier and SADC offset errors.Furthermore, the calibration technique can be employed so asto enhance the ADC (or a backend ADC) resolution to B bitsas long as the following stages effectively have a resolution of(B − 3) bits.

A. Implementation Complexity of the ProposedCalibration Technique

Fig. 15(a) demonstrates all the required bank of transmission-gates (T-gates) for the DES block implementation. In thisfigure, each line placed between two nodes represents a T-gate.The DES switches place two T-gates between the SADC output,dai, and SDAC inputs, xi and xi+1, for 1 < i < L, and (L+1) T-gates are also placed between the PN node and all theSDAC inputs. Therefore, the DES block needs 3L+ 1 T-gates.The DES technique configures the required path accordingto the selection number. For instance, Fig. 15(b) depicts theconnections between the SADC output and the SDAC inputfor S = 3. The switches of the DES block have a subtraction


Fig. 15. (a) Implementation of the DES block. (b) The configuration of theDES block for S = 3.

operator to subtract S − i in the ith switch of the DES block(i = 1, . . . , L+ 1). The PN sequence is passed to the output ofthe ith switch providing that all the output bits of the subtractionoperator are simultaneously low; otherwise, a simple digitalcombinational block selects the T-gate connecting dai to theith switch output, xi, or the T-gate passing dai−1 to xi whenthe output carry of the subtraction operator is high or low,respectively. Because the clocking of the DES block is 1/Mof the clock frequency of the system, the power dissipation ofthis block is not critical.

The SDME method is an all-digital block operating on thedigitized residue and doesn’t insert any circuit in critical paths.Consequently, the ADC speed isn’t affected by the SDMEblock. Each ME channel of the SDME block has two digitalsubtraction operators and two sign operations extracting theoutput sign of the subtraction operators. A digital combina-tional block enables the up or down pins of the accumulator,realizing the discrete-time integrator, according to the PN se-quence and the outputs of the two sign operators. It is worthto mention that the power consumption of the SDME blockis not critical since just one of the ME channels is active ateach iteration. Each ME channel needs a 20-bit accumulatorfor the implementation of each of the discrete-time integrators,similar to [10]. Nonetheless, since the unit elements mismatchis bounded in magnitude to 2%, the 5 most significant bits(MSBs) of the integrators are never used. Accordingly, a 15-bit accumulator is sufficient for the realization of each of thediscrete-time integrators. The output of each of the accumula-tors must also be divided by 220.

B. Comparison to Other Calibration Techniques

The propagation delay is defined as the number of T-gatelayers placed in series between the SADC output and SDACinput. The propagation delay can be expressed as following:

tpd ≈ 0.35 ·R · C · TL2 (30)

where C and R sand for the capacitance and equivalent resis-tance of each switch, respectively, and TL also denotes the num-ber of the series T-gate layers [13]. The DES method inserts justone T-gate layer between the SDAC input and SADC output,whereas the DEM encoder in [10] places at least log2(L) seriesof T-gate layers. Thus, the presented method has a minimaleffect on the digital complexity and resulted propagation delaythrough digital circuits, and it can be exploited in high-speed

pipelined ADCs in contrast to the technique in [10]. Moreover,the number of the SADC levels, L, needs to be an even numberin the DEM encoder of [10], whereas the DES method doesn’timpose such a limitation on L. Besides, the required T-gatesof the DES method are 3L+ 1, while the techniques in [13]and [14] need L2 T-gates. It is worth mentioning that, at eachiteration, only one of the ME channels is enable accordingto the selection number, while all the DNC channels in [10],[13], and [14] are active concurrently. Therefore, the powerconsumption of the introduced SDME is approximately 1/Lthat of the DNC method in [10], [13], and [14]. Due to theinjection of the PN sequence, the presented technique needstwice as many SADC levels as the DNC method in [10], [13],and [14]. In turn, the SADC dissipates more power because thenumber of the SADC comparators needs to be at least doubledand the standard deviation of the SADC comparators must bedecreased by a factor of more than two at the cost of quadru-pling the area of the SADC comparators [7]. In order to preventextra power consumption in the SADC, an offset calibrationapproach can help to keep (or even help to lessen) the sizeof the SADC comparators by reducing the standard deviationof the SADC offsets through the SADC offset calibrationmechanisms, e.g., [4], [20].

As explained earlier, the presented calibration scheme iscapable of continuously alleviating the conversion errors due tothe residue amplifier gain variations in addition to the mismatchamong the SDAC unit elements in contrast to the methodin [10]. However, the nonlinearity calibration techniques in[11] and [12] must also be exploited concurrently with theproposed scheme to compensate for the nonlinearity of theresidue amplifier in case the residue amplifier nonlinearity isnot negligible (since the described technique is fully compatiblewith the residue amplifier calibration methods of [11] and [12]).In conclusion, foreground calibration methods (e.g., [7]) shouldbe employed to eliminate the impact of the SDAC mismatcherrors on condition that the residue amplifier gain is suffi-ciently accurate and stable over time, whereas the describedscheme is preferable in the presence of the residue amplifiernon-idealities.

As shown in Section IV, even if the first stage errors arecanceled, the remaining stages can also limit the ADC SNDR.Hence the non-idealities of the following stages must also becanceled so as to achieve the desired SNDR. The introducedtechnique can be replicated to operate on multiple stages asrequired to achieve the target SNDR, and all the replicas ofthe presented technique can work simultaneously similar to theDNC method in [10]. The proposed method is not suitable toenhance the resolution of a stage followed by a low accuracybackend (e.g., a B-bit backend ADC with B < 7 bits) because,in this case, the algorithm does not estimate the digital weightsaccurate enough. The introduced scheme doesn’t need an extraADC as opposed to the methods in [8] and [19]. In addition,the schemes in [8], [9], and [19] are not compatible withthe residue amplifier calibration methods of [11] and [12].The method of [17] is also strongly sensitive to the inputsignal distribution as it directly operates on the input signal tocancel the SDAC mismatch errors, while the presented methoddepends on the digitized residue distribution. Since the SADC


TABLE ICOMPARISON OF THE PRESENTED METHOD WITH SIMILAR TECHNIQUES

resolution in the introduced technique must be conceptuallyincreased by 1 bit (practically by more than 1 bit) and the SDACin a 1.5-bit stage needs just one capacitor as well, the proposedmethod is suitable for multi-bit stages, allowing a redundancyof more than 1 bit, in order to compensate for the mismatchamong the SDAC unit elements. Table I provides a summarizedcomparison of the presented method with similar techniques.

C. Limitations of Input Signal

The input signal can affect the performance of the proposedscheme similar to other calibration techniques, e.g., [12], [16],and [17]. The convergence rate of the presented method isdecreased when the residue voltage probability distribution ex-hibits an interval with a too small magnitude. The algorithm canconverge to incorrect values or even fail to work if the residuevoltage PDF has a zero interval. The probability distribution ofthe residue voltage doesn’t effectively affect the convergencerate of the introduced method on condition that the residuevoltage PDF is continuous and is not too small inside its distri-bution range. The probability distribution of the residue voltageis also continuous and approximately uniform providing thatthe input signal PDF is piecewise linear and is not too smallwithin its distribution range. In most ADC applications (e.g.,communications, image processing, and radar applications),almost full-scale sine-wave or Gaussian-distributed signals areoften applied to an ADC; hence the PDF of the residue voltageis continuous and is not too small inside its distribution range.Consequently, the presented method also operates well withthese inputs.

For a deterministic input signal, to prevent the repeatingvariations of the SNDR after the convergence (as seen fromFig. 13), the number S should be generated in a randomfashion at the expense of a longer convergence time; however,for random input signals, the sequencing of S doesn’t impactthe SNDR after the convergence. The value of M must bechosen arbitrary between 1 < M < ∞; nevertheless, for a largevalue of M (e.g., M = 108), it takes M(L+ 1) clock cyclesin order to estimate all the SDAC step sizes by the proposedalgorithm. In addition, the value of M doesn’t effectively affectthe SNDR convergence of the introduced technique.

VI. CONCLUSION

In this paper, a statistics-based digital background calibrationtechnique for DAC unit elements in pipelined ADCs has beenintroduced. The proposed method continuously measures anddigitally mitigates the conversion errors resulted from SDACmismatch errors. This scheme can be used to increase theconversion rate of pipelined ADCs and/or reduce the power

Fig. A1. Simplified circuit implementation of a residue amplifier.

consumption of pipelined ADCs. The introduced method alle-viates the need for the complex DEM technique with a criticalpropagation delay in high-speed ADCs. Besides, this algorithmcan be applied to as many stages as required in order to achievethe desired accuracy without needing any extra ADC.

APPENDIX A

The simplified circuit implementation of a residue amplifierwith a multi-bit switched-capacitor SDAC is shown in Fig. A1.For analysis simplicity, a single-ended configuration is usedin this appendix; however, differential configuration is usuallyutilized in practice. During the sampling phase (i.e., ϕ1 is high),the input, Vin, is sampled into the nominally identical samplingcapacitors CS,i (i = 1, . . . , L). During the amplifying phase(i.e., ϕ2 is high), the control signals, XP,i and XN,i are 1 and 0,respectively, if the SDAC input, dai is equal to 1, and XP,i andXN,i are also 0 and 1, correspondingly, otherwise. Therefore,during ϕ2, the capacitor CS,i is connected to Vref or −Vref

depending on the SDAC input, dai (i = 1, . . . , L), where Vref

and −Vref denote the reference voltages normalized to 1 and−1, respectively, in this paper. It can be shown that the outputvoltage of the residue amplifier at the end of the amplificationphase is given by [7]

Vo = gA(Vin − Vd) (A.1)

where gA and Vd denote the gain of the residue amplifier andthe output of the SDAC defined as

gA =Ceq

CF + (CF + Ceq)A−1o

(A.2)

Vd =L∑

i=1

Δidai. (A.3)


In (A.2) and (A.3), Ao denotes the DC gain of the op-amp, andCeq and Δi stand for the total sampling capacitance and stepsize of the ith 1-bit DAC element, respectively, expressed asfollowing:

Ceq =

L∑i=1

CS,i (A.4)

Δi =CS,i

Ceqi = 1, . . . , L. (A.5)

APPENDIX B

In this appendix, the relation (21) is derived. Plugging (18)and (19) into (17) and exploiting (16), the estimation errors canbe written as

EEi =

−gi/2∫−(ΔQS+Δi)/2

pDRES(Dres|PN = +1)dDres

−gi/2∫

(Δi−ΔQS)/2

pDRES(Dres −Δi|PN = +1)dDres (B.1)

where i = 1, . . . , L+ 1. Using the dummy variable D′ as asubstitute for Dres −Δi in the second integral, the estimationerrors can be represented by

EEi =

−gi/2∫−(ΔQS+Δi)/2


−−Δi+gi/2∫

−(ΔQS+Δi)/2

pDRES(D′|PN = +1)dD′ (B.2)

for i = 1, . . . , L+ 1. In (B.2), the two integrals can be com-bined as follows:

EEi =

−gi/2∫−Δi+gi/2


i = 1, . . . , L+ 1. (B.3)

APPENDIX C

In this appendix, it is verified that the mean value of IEi (i =1, . . . , L+ 1) is identical to EEi. Since sgn(x) = 1 for x ≥ 0and sgn(x) = −1 otherwise, it follows from basic probabilitythat:

P (sgn(x) = +1) =P (0 ≤ x) (C.1)

P (sgn(x) = −1) = 1− P (0 ≤ x). (C.2)

For the mode PN �= m, the operator q(x|PN = m) is disabled;as a consequence, the probability of the event q(x|PN = m) =0 is given by

P (q(x|PN = m) = 0) = P (PN �= m). (C.3)

Moreover, the operator q(x|PN = m) is enabled for the statePN = m; therefore, it follows from (26) and (C.1)–(C.3) that:

P (q(x|PN=m)=+1)=P (PN=m)×P (0≤x|PN=m)(C.4)

P (q(x|PN=m)=−1)=P (PN=m)×[1−P (0≤x|PN=m)].(C.5)

From (24), (C.4), and (C.5), it can be shown that

P (IE+,i = +1) =P (PN = +1)

× P (Dres<−gi/2|PN = +1) (C.6)P (IE+,i = −1) =P (PN = +1)

× [1− P (Dres<−gi/2|PN = +1)] . (C.7)

From (C.6) and (C.7), it can be proved that the expected valueof IE+,i is given by

E[IE+,i] = P (PN = +1)

× {2 · P (Dres < −gi/2|PN = +1)− 1} . (C.8)

In addition, it follows from (25), (C.4), and (C.5) that:

P (IE−,i = +1) =P (PN = −1)

× P (Dres < gi/2|PN = −1) (C.9)P (IE−,i = −1) =P (PN = −1)

× [1− P (Dres < gi/2|PN = −1)] . (C.10)

It follows from (C.9) and (C.10) that the expected value of IE−,i

is expressed as:

E[IE−,i] = P (PN = −1)

× {2 · P (Dres < gi/2|PN = −1)− 1} . (C.11)

Consequently, it follows from the property P (PN = 1) =P (PN = −1) = 0.5, (C.8) and (C.11) that the means of theinstantaneous estimation errors are represented by:

E[IEi] = P (Dres < −gi/2|PN = +1)

− P (Dres < gi/2|PN = −1) (C.12)

for i = 1, . . . , L+ 1. It follows from (C.12) and (17)–(19) thatE[IEi] (i = 1, . . . , L+ 1) are equal to those of EEi.

APPENDIX D

In reality, the presence of SADC offset errors can causethe residue and output voltages to exceed the desired ranges[−ΔQS/2,ΔQS/2] and [−1, 1], respectively. For this reason,the nominal gain of the residue amplifier must be sufficiently re-duced so as to keep the output voltage inside the range [−1, 1].In turn, the output voltage would conceptually be bounded tothe interval [−IOR, IOR], where IOR represents the ideal out-put range, and the remaining range is dedicated to toleratethe SADC offset errors. Accordingly, the maximum magnitudeof the SADC offset errors that can be tolerated is given by(1−IOR)/gA. Furthermore, it is easy to derive that the nominalgain of the residue amplifier, gA, must be equal to 2 IOR/ΔQS(= L IOR) and IOR/ΔQS(= L IOR/2) without and withthe injection of the PN sequence, correspondingly.


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[13] E. Siragusa and I. Galton, “A digitally enhanced 1.8-V 15-bit40-Msample/s CMOS pipelined ADC,” IEEE J. Solid-State Circuits, vol.39, no. 12, pp. 2126–2138, Dec. 2004.

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Hamidreza Mafi received the B.Sc. and M.Sc. de-grees in electrical engineering from Shahid RajaeiUniversity, Iran, in 2007 and Qazvin Azad Univer-sity, Iran, in 2012, respectively. He has served asa reviewer for IEEE TRANSACTIONS ON VERYLARGE SCALE INTEGRATION (VLSI) SYSTEMS

and Circuit, System, and Signal Processing (CSSP).His research interests include data converters, signalprocessing, and mixed-signal circuits and systemswith particular interest in background calibration ofdata converters.

Mohammad Yavari (S’01–M’08) received theB.Sc., M.Sc., and Ph.D. degrees in electrical en-gineering from the University of Tehran, Tehran,Iran, in 1999, 2001, and 2006, respectively. He hasbeen with the Department of Electrical Engineer-ing, Amirkabir University of Technology (TehranPolytechnic), Tehran, since 2006, where is now anAssociate Professor. He founded the Integrated Cir-cuits Design Laboratory in AUT in 2007. He spentseveral research periods with the Institute of Micro-electronics of Seville (IMSE-CNM), Seville, Spain.

He was with Niktek, from May 2004 to April 2005 and October 2006 toMay 2007, as a Principal Design Engineer, where he was involved in thedesign of high-resolution A/D and D/A converters for professional digital audioapplications. He is the author or coauthor of more than 130 peer-reviewedpapers in international and national journals and conference proceedings onanalog integrated circuits. His current research interests include analog andmixed-signal integrated circuits and signal processing, data converters, andCMOS RFIC design for wireless communications. Dr. Yavari was a recipient ofthe Best Student Research Award of the University of Tehran in 2004 and theBest Paper Award of the Iranian Conference on Electrical Engineering in 2014.He has been an Associate Editor of the International Journal of Circuit Theoryand Applications since 2014.

Hossein Shamsi received the B.Sc., M.Sc., andPh.D. degrees in electrical engineering (electronics)from University of Tehran, Iran, in 2000, 2002, and2006 respectively. He has been working as AssistantProfessor with the Faculty of Electrical Engineering,K.N. Toosi University of Technology, Iran, since2007. His current research activities include inte-grated circuits, data converters, RFIC, and RFIDsystems.

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