differential amplifiers - nchu.edu.twcc.ee.nchu.edu.tw/~aiclab/teaching/aic/lect04.pdfdifferential...

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Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Differential Amplifiers

類比電路設計(3349) - 2004

4-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Overview

ReadingB. Razavi Chapter 4.

Introduction

Offering many useful properties, differential operation has become the dominant choice in today’s high-performance analog and mixed-signal circuits. This lecture deals with the analysis and design of CMOS differential amplifiers. It contains:

Review of single-ended and differential operation.Analysis of the large-signal and small-signal behavior.The common-mode rejection.Differential pair with diode-connected and current-source loads as well as differential cascode stages.

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Single-ended and differential operation

Single-ended and differential signals

What are “common-mode” (CM) and “differential mode” (DM)?


Advantages of differential operation

Reduction of coupling

Common-mode rejection occurs with noisy supply voltages

3


Advantages of differential operation (cont’d)

Reduction of coupled noise by differential operation

Increase in maximum achievable voltage swingSimpler biasingHigher linearity


Simple differential circuit

4


Basic differential pair

Schematic –- source-coupled pair

The differential pair employs a current source ISS to make ID1 + ID2 indepentof Vin,CM. Thus, if Vin1 = Vin2, the bias current of each transistor equqls ISS /2and the output common-mode level is VDD − RDISS /2.


Basic differential pair (cont’d)

Qualitative analysis

Input/output characteristics

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Common-mode characteristics

Common-mode schematic

Common-mode input/output characteristics


Common-mode characteristics

Input common-mode range – M1, M2 in saturation

The small-signal differential gain of a differential pair vs. the input CM level

( )

+−≤≤−+ DDTH

SSDDDCMinTHGSGS VVIRVVVVV ,

2min,331

M1, M2 sat.M1, M2 triode

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Output swing of a differential pair

For M1 and M2 to be saturated, each output can go as high as VDD but as low as approximately Vin,CM − VTH. In other words, the higher the input CM level, the smaller the allowable output swings. For this reason, it is desirable to choose a relatively low Vin,CM.

An trade-off exists between the maximum value of Vin,CM and differential gain. Similar to a simple CS stage, the gain of a differential pair is a function is a function of the dc drop across the load resistors. Thus, if RDISS /2 is large, Vin,CM must remain close to ground potential.


Quantitative analysis

Differential pair

Vout1 = VDD − RD1ID1 , Vout2 = VDD − RD2ID2

[RD1 = RD2 = RD] Vout1 − Vout2 = RD2ID2 − RD1ID1 = RD (ID2 − ID1)

Assuming the circuit is symmetric, M1 and M2are saturated, and λ = 0,Vin1 − Vin2 = VGS1 − VGS2

For a square-law device, we have:Therefore,

Recognizing that ID2 + ID1 = ISS, we obtain

LWC

I

LWC

IVVoxn

D

oxn

Dinin

µµ21

2122

−=−

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Quantitative analysis (cont’d)

Squaring the two sides again and 4ID1ID2 = (ID1 + ID2)2 − (ID1 − ID2)2 = ISS2 − (ID1 − ID2)2 ,

we arrive at

Denoting ∆ID = ID1 − ID2 and ∆Vin = Vin1 − Vin2 , we can show that

( ) ( )

( ) 212

21

212

21

221

22

DDSSininoxn

DDSS

oxn

inin

IIIVVL

WC

III

LWC

VV

−=−−

−=−

µ

µ

( ) ( )22121214

21

inin

oxn

SSininoxnDD VV

LWC

IVVL

WCII −−−=−µ

µ

2

2

/4

2/

4

21

inoxn

SS

inoxn

SS

oxnin

D

VLWC

I

VLWC

I

LWC

VI

∆−

∆−=

∆∂∆∂

µ

µµ



Variation of ID and GM vs. ∆Vin

ISS

For ∆Vin = 0,

Since ∆Vout = Vout1 − Vout2 = RD ∆ID = RDGM∆Vin,

the small-signal differential gain is given as

GM = 0 for

=∆∂∆∂

==0inVin

Dm V

IG SSoxn IL

WCµ

== Dmv RGA DSSoxn RIL

WC ⋅µ

LWCIV

oxn

SSin /

2µ

=∆

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For a zero differential input, ID1 = ID2 = ISS /2, and hence

Increasing ∆Vin to make the circuit more linear inevitably increases the overdrive voltage of M1 and M2. For a given ISS, this is only by reducing W/L and hence the gm of the transistors.

( )22,1in

oxn

SSTHGS

V

LWC

IVV ∆==−

µ

ISS



Input/output characteristic

As W/L increases, ∆Vin decreases,narrowing the input range across which both devices are on.

As ISS increases, both the input range and the output current swing increase.

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Differential pair with small-signal inputs

Scheme – M1 and M2 sat., small signals Vin1 and Vin2.

Analysis

Differential pair sensing one input signal.

Circuit viewed as a CS stage degenerated by M2.

Equivalent circuit.

21

1

2

11

/1

mm

D

in

X

mS

gg

RVV

gR

+−=

=


M2 operates as a CG stage, exhibiting a gain equal to

The overall voltage for Vin1 is (VX − VY)|Due to Vin1

which, for gm1 = gm2 = gm reduces to is (VX − VY)|Due to Vin1 = − gmRDVin1.

Similarly, (VX − VY)|Due to Vin2 = − gmRDVin2. Thus, we have

Differential pair with small-signal inputs (cont’d)

Replacing M1 by a Thevenin equivalent

12

111mm

D

in

Y

gg

RVV

+=

1

21

112

in

mm

D V

gg

R

+−=

( )=

−−

21 inin

totYX

VVVV

DmRg−

VT = Vin1

RT = 1/gm1

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Differential and common-mode components

22

222112

2

21211

ininininin

ininininin

VVVVV

VVVVV

++

−=

++

−=


Differential and common-mode components (cont’d)

Superposition for differential and common-mode signals

22

222112

2

21211

ininininin

ininininin

VVVVV

VVVVV

++

−=

++

−=

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Differential and common-mode components (cont’d)

λ ≠ 0Differential-mode operation Common-mode operation

( )

( )

( )oDminin

YX

ininoDmY

ininoDmX

rRgVVVV

VVrRgV

VVrRgV

−=−−

−−=

−−=

21

122

211

2

2If the circuit is fully symmetric and ISS an ideal current source, the current drawn by M1 and M2 from RD1 and RD2 is exactly equal to ISS /2 and independent of Vin,CM . Thus, VX and VY experience no change as Vin,CM varies.


Common-mode response

Differential pair sensing CM input

RSS : the output impedance of current source. SS

m

D

CMin

outCMv

Rg

RVVA

+−==

21

2/

,, ( λ = γ = 0 )

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Common-mode response with mismatch

Resistor mismatch

• Effect of CM noise • CM response with finite tail cap.

A CM change at the input introduces a differential component at the output.

( )DDSSm

mCMinY

DSSm

mCMinX

RRRg

gVV

RRg

gVV

∆++

∆−=∆

+∆−=∆

21

21

,

,


Common-mode response with mismatch (cont’d)

Mismatch between M1 and M2

( ) ( )( ) ( )

( ) CMinDSSmm

mmYX

CMinDSSmm

mDPCMinmY

CMinDSSmm

mDPCMinmX

VRRgg

ggVVVR

RgggRVVgV

VRRgg

gRVVgV,

21

21

,21

2,2

,21

1,1

11

1++

−−=−⇒

++−=−−=

++−=−−=

Thus, the circuit converts input CM variations to a differential error by a factor equal to

( ) 121 ++∆

−=−SSmm

DmDMCM Rgg

RgA

ACM−DM : CM to DM conversion∆gm = gm1 − gm2

( )( )

( )( )( )

( ) CMinSSmm

SSmmP

SSPPCMinmm

PCMinmD

PCMinmD

VRgg

RggV

RVVVgg

VVgIVVgI

,21

21

,21

,22

,11

1

/

+++

=⇒

=−+⇒

−=−=

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Common-mode rejection ratio (CMRR)

Definition

If only gm mismatch is considered

Differential mode (assume Vin1 = −Vin2)

Common-mode to differential-mode conversion

CMRR

DMCM

DM

AACMRR

−

=

[ ]SSmm

m

m

SSmmmm

Rgg

gg

RggggCMRR

21

24 2121

+∆

≈

∆++

=

SSmm

SSmmmmDDM Rgg

RggggRA)(1

42 21

2121

++++

=

( ) 121 ++∆

−=−SSmm

DmDMCM Rgg

RgA SSmS RgR )/1( 2=


Differential pair with MOS loads

Diode-connected load Current-source load

( )

( )( )Pp

Nn

mP

mN

oPoNmPmNv

LWLW

gg

rrggA

//

1

µµ

−=

−≈

−= − ( )oPoNmNv rrgA −=

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Differential pair with MOS loads (cont’d)

Diode-connected + current source loads

Cascode differential pair

])()[( 7551331 oomoommv rrgrrggA ≈

Half circuit


Variable-gain amplifier (VGA)Simple VGA

Two stages providing variable gain

Av = Vout /Vin varies from zero (if ID3 = 0) to a maximum value given by voltage headroom limitations and device dimensions.

VGAs find application in systems where the signal amplitude may experience large variations and hence requires inverse change in the gain.

Consider two differential pairs that amplify the input by opposite gain. We now have Vout1/Vin = −gmRDand , where gm denotes the transconductance of each transistor in equilibrium. If I1 and I2 vary in opposite directions, so do |Vout1/Vin|and |Vout2/Vin|.

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Gilbert cell

Vout = Vout1 + Vout2 = A1Vin + A2Vin

If I1 = 0, then Vout = +gmRDVin.

If I2 = 0, then Vout = −gmRDVin.

For I1 = I2, the gain drops to zero.

Vcont1 and Vcont2 vary I1 and I2 in opposite directions such that the gain of the amplifier changes monotonically. For Vcont1 = Vcont2, the gain is zero.

For M5-6 to operate in saturation, the CM level of Vcont, VCM,cont, must be such that

VCM,cont ≤ VCM,in − VGS1 + VTH5,6.


Gilbert cell (cont’d)

Gilbert cell sensing the input voltage by the bottom differential pair

For very positive Vcont,

Vout = gm5,6RDVin.

For very negative Vcont,

Vout = −gm5,6RDVin.

differential amplifiers - nchu.edu.twcc.ee.nchu.edu.tw/~aiclab/teaching/aic/lect04.pdfdifferential...

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