7/28/2019 dielectric Introduction.pdf

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The success of the semiconductor industry relies on the continuousimprovement of integrated circuit performance. This improvement isachieved by reducing the dimensions of the key component of these circuits:the MOSFET (metaloxidesemiconductor field effect transistor). Indeed,the reduction of device dimensions allows the integration of a higher numberof transistors on a chip, enabling higher speed and reduced costs. The scalingof MOSFETs follows the famous Moores law, which predicts the exponentialincrease in the number of transistors integrated on a chip [1]. This lawis shown in figure 1.1.1, where the number of devices integrated in thedifferent generations of Intels microprocessors is presented as a function ofthe production year of these circuits [2]. For the sake of comparison, the 4004processor, manufactured in 1971, integrated 2250 transistors from the 10 mmtechnology node (channel length of the devices) and was running at 108 kHz.The latest Intel Pentiumw4 processor, introduced in 2002, integrates about53 million transistors from the 0.13 mm technology, and demonstrates a clockfrequency up to 2.8GHz (at the time of writing).One of the key elements that allowed the successful scaling of siliconbasedMOSFETs is certainly the excellent material and electrical propertiesof the gate dielectric so far used in these devices: SiO2. This material indeedpresents several important features that have allowed its use as gate

insulator. First of all, amorphous SiO2 can be thermally grown on siliconwith excellent control in thickness and uniformity, and naturally forms avery stable interface with the silicon substrate, with a low density ofintrinsic interface defects. Besides, one of the most important defects at the3(100)Si/SiO2 interface, the Pb0 centre (trivalent Si dangling bond), can bepassivated very efficiently after post-metallization anneals performed in ahydrogen containing ambient. Secondly, SiO2 presents an excellent thermaland chemical stability, which is required for the fabrication of transistorsthat includes annealing steps at high temperatures (up to 10008C). Last butnot least, the band gap of SiO2 is quite large (about 9 eV), which confersexcellent electrical isolation properties to this material, like its large energyband offsets with the conduction and valence bands of silicon and high

breakdown fields, of the order of 13MVcm21. It should be pointed outthat the use of poly-silicon as gate electrode in a self-aligned CMOStechnology was also a determining factor in the scaling of the transistorstructures.All these superior properties allowed the fabrication of properlyworkingMOSFETs with SiO2 gate layers as thin as 1.5nm [3, 4]. However, aswill be argued below, further scaling of the SiO2 gate layer thickness isproblematic. As illustrated in table 1.1.1, which is extracted from thespecifications of the latest International Technology Roadmap forSemiconductors (ITRS) [5], the next generations of Si-based MOSFETswill require gate dielectrics with thicknesses below 1.5 nm, both for the highperformance logic applications (like microprocessors for personal computersand workstations) and low operating power logic applications (like wireless

applications). From a fundamental point of view, let us recall that the limitfor SiO2 thickness scaling is about 7A [6], below which the full band gap ofthe (bulk) insulator is not formed