DFC on behalf of controls software and electronics groups

Tango meeting March 19th 2007

Status of Alba Controls

DFC 2

DFC 3

Outline• EDMS Project follow up, Naming

• Projects– Timing, EPS, PSS, Fast interlocks– Vacuum, RF,IDs, Power Converters, Linac, Diagnostics, Motors

• Installation. Cabling• Schedule

DFC 4

Project’s follow up

sum(hours) per divisions

Accelerators33%

Computing46%

Engineering2%

Experiments17%

Safety2%

sum(hours). Accelerators Projects

Vacuum control system

5%Timing14%

RF11%

Diagnostics7%

Insertion devices3%Test Bench for

Magnets42%

New Test Bench for IDs

2%

Linac0%

Interlocks equipment protection

2%

Machine simulator2%

Power supplies3%

Low level electronics for RF

9%

DFC 5

EDMS: Technical specs

DFC 6

Timing

• Communication of events.– Events are generated by:

• Internal counters (32 bit)

• External trigger signal or software.

• Optic event fiber: multimode 850 nm.

• 25 ps rms jitter in the output and one event

• ~280 Event receivers

DFC 7

Operators interfacestiming tests:

DFC 8

Fast interlocks and fast data loggers EVG

Timing Fan Out

Timing Fan Out

Timing Fan Out

Timing Fan Out

EVR FIM-1 FIM-1 EVR EVR FIM-1 EVR EVR FIM-1

FIM-2

General Interlock DetectionTTL In

FIM-2 Patch Panel

Patch Panel

TTL Remote Interlock from Timing System

TTL Remote Interlock from Timing System

TTL Remote Interlock from Timing System

150m Optic Duplex Fiber

150m Optic Duplex Fiber

150m Optic Duplex Fiber

FIM-1Input

Output

FIM -4

Inpu

t

Out

put

FIM-2

Input

Output

Output

InputFIM-3

DFC 9

Equipment Protection System

DFC 10

Vacuumracks

DFC 11

PSS

DFC 12

Diagnostics• BLM

– Bergoz + Cosylab• 485

• CCD– Prosilica GigE– Frame grabber + Video

• Euresys + Jai

• Liberas– Server (soleil)– + Python libraries

DFC 13

• Ion Pumps– Varian

double ?• Penning & IMG

– MKS ?

• Valves– Controlled by

PLCs

• GUIs. See presentation by

Vacuum Controls:

DFC 14

RF LAb

• 1 Transmitter• 1 Cavity

– Test of tunning of the plungger• ADLINK DI/DO.

– Test of Analog LLRF regulation• ADLINK AI/AO

– Test of Digital LLRF regulation.• Sundance

• 1 PSS

DFC 15

IcePaP

Microstepping

(8A, 70V, 330W)

Motion test bench

Human interfaces

Motion

Configuration

Icepapcms: Config tool for motors

• System/Crate level– Name of the driver– Status– Current…– Limit switches

• For each driver:– Enable/disable– Double click to configure it.

DFC 16

Power converters

• Digital regulation

• Ethernet connections

• Correctors and Fast Orbit Feed Back– Specification going on

Linac

?

DFC 17

Beamlines

DFC 18

Installation: cable databases

DFC 19

Schedule

RF, Vaccum protos, Diagnostics, etc. Linac

2007

Preinstallation Commissioning

2008Installation

ID inst.

2009Commissioning ID commissioning

DFC 20

Thank you for your attention

P.Readman

D.BeltranR.Butzbach E.Taurel D.Fernández F.Becheri

R.Ranz

S.Rubio

O.Matilla J.V.Gigante T.Coutinho J.Ribas

L.Krause

S.Blanch

R.Suñé

DFC 21

DFC 22

• General components– Crates CPCI (CPU: ADLINK & INOVA)

– ADC/DAC/Counter (NI & ADLINK)

• PLC bench test– Siemens, Wago, Beckhoff, ABB

Hardware

Siemens

Wago Beckhof

ABB

CPCI

Applicationprograms

API

Clients(GUI, Scripts)

Hardware

Dserver(TANGO)

DFC 23

Item Total S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16Diagnostics 13 0 3 0 5 0 0 0 0 1 0 0 0 1 0 3 0eBPM 44 3 6 0 2 3 3 3 2 3 3 3 2 3 3 3 2RF 21 3 0 0 0 0 6 0 0 0 6 0 0 0 6 0 0ID 6 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0FE 9 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0Pulsed Elements 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1Bo Power supplies 7 0 0 0 1 0 0 1 0 0 0 1 0 0 0 4 0 16 corr SR16 quad SR

SR PS 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Vacuum 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Linac 1 1CTRM 1 1Total 146 8 12 2 14 5 11 6 3 9 11 6 5 6 10 12 4 124

20 19 17 12 1724 30 18 22 28

21 16

BL 9 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 0

cPCI 119 167PMC 25 45

281

Fount 30 60EVG 3 9