Device Scaling and Performance Improvement: Advances in Ion Implantationand Annealing Technologies as Enabling Drivers

Yuri Erokhin

Applied Materials - Varian Semiconductor Equipment, 35 Dory Road, Gloucester, MA 01930, USATel: 1-978-282-2704, Fax: 1-978-281-1897, E-mail: yuri_erokhin@amat.com

Abstract

The complexity of ion implant applications in ICfabrication has grown significantly since becoming thepreferred process for doping semiconductors.Aggressive device scaling over the last decade raisedunique challenges. This resulted in the invention ofnovel implant applications to address device scalingdriven issues and the development of new generationsof ion implanters. These newly developed tools arecapable of delivering a wide variety of ion beams oftraditional doping and non-doping species, withmanufacturing worthy beam currents over an energyrange extending from 200 eV to several MeV. Theyare capable of controlling implanted wafer temperaturedown to cryogenic conditions to take full advantage ofnew defect engineering approaches. All theseinnovations resulted in significant growth of ionimplantation steps in advanced IC manufacturing forboth doping and Precision Materials Modification(PMM). In this paper we present an overview of recentadvances in ion implantation technologies andapplications addressing sub-20nm device and processintegration challenges. We illustrate how theseinnovations enable improvement of deviceperformance and expansion of process marginsthrough novel capabilities of ion implantation toolscoupled with innovative materials engineeringapproaches for junction formation and for processmodules beyond of traditional doping applications.

1. Device Scaling Challenges

Scaling of planar bulk silicon devices past32/28/22nm nodes presents major challenges in threekey device performance and yield areas: (i) escalatingdevice leakage, (ii) increased Source/Drain contactresistance and (iii) increased device variability andnarrowed margins of device manufacturing processes.

A. Device leakage

Rapidly escalating device leakage is a criticalissue having its most severe impact on SOC ICstargeting mobile applications. Root causes for

increased leakage in scaled down planar bulk silicondevices are attributed to several scaling factors. First,the inability to scale down Vdd proportionally withdevice channel length (Lg) increased the magnitude ofthe electric field in the SD-halo device regions leadingto rapidly increasing Gate Induced Drain Leakage(GIDL), Band-To-Band-Tunneling (BTBT) and ShortChannel Effects (SCE). Secondly, a requirement tominimize dopant diffusion in scaled down devices andto meet ever higher requirements for SDE junctionabruptness imposes severe limitations on the allowablethermal budget for the post implant anneals. Typically,at the 20nm node peak sRTA temperature have to beset at sub-1000 oC. This results in the inability toadequately anneal implantation induced crystaldamage and further increases device leakage due tocharge traps in the junctions depletion regions relatedto un-annealed crystal defects.

GIDL

Isub

IBTBT Junctionleakage

Ich

Iwell

GIDL

Isub

IBTBT Junctionleakage

Ich

Iwell

Fig. 1. Key leakage path in planar bulk siliconsub-32/28nm devices.

To at least partially mitigate the above effects acombination of process engineering and novel implanttechnology capabilities are deployed at sub-32/28 nmnodes. From a process engineering standpointminimization of leakage is accomplished by carefuloptimization of dopant distributions in the SD/haloregions to provide optimum suppression of SCE whileminimizing the electric field especially in theSDE/Halo device regions. To achieve this, the BF2

halo implants traditionally used in NMOS devices arebeing replaced with In and B with carbon co-implantto further suppress boron diffusion.

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(a) (b)

Fig. 2. TCAD modeling of peak electric field in thedrain/halo NMOS device region with (a) optimizedone-step BF2 halo implant vs. (b) halo formed usingoptimum Indium, Boron and Carbon implant sequence.

As seen in Fig. 2, a multistep halo implantconfines the area of maximum electric field inproximity to the gate edge. This reduces the GIDL andBTBT components of the device leakage currentcompared to a traditional one-step BF2 NMOS haloimplant.

Further leakage reduction is enabled by halo andSDE implants done at cryogenic temperatures. Bychanging from room temperature to cryogenic siliconwafer temperature a significant reduction ofEnd-of-Range (EOR) damage in implants nearamorphization conditions in silicon has beendemonstrated by Suguro et al well over a decade ago[1]. The practical relevance of this approach forresolving critical device scaling challenges reached itscritical mass when the IC industry approached the45/40nm node. A production-worthy implant toolcapable of implanting wafers at cryogenictemperatures down to -100 oC had been firstintroduced by Varian [2]. Theoretically, defectimprovement efficiency could have been even higherat wafer temperatures below -100 oC, but processintegration limitations, specifically those related tophotoresist properties, set the optimum wafertemperature for cryogenic implants at about -100 oC.

The materials science phenomenon responsiblefor EOR reduction enabled by implants at cryogenictemperatures is illustrated in Fig. 3 below. It exploits awell known effect of the temperature dependence ofthe accumulation of implantation-induced crystaldamage in silicon. Under the same implantationconditions (nuclear stopping energy deposition) theaccumulation rate of crystal damage in the silicon

lattice increases with reduction of the wafertemperature. For amorphizing implant conditions thiseffectively results in an increased thickness of theamorphous layer created by the incoming ions, in turnconsuming a significant fraction of the end-of-rangedefects present within the interface region between theamorphous layer and the undamaged Si crystalsubstrate.

EORDefects

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Damage Engineeringusing CryogenicImplant (PTCII)

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EORDefects

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Fig. 3. Schematic illustrating formation of amorphousvs. sub-amorphized (EOR) regions in Si created byamorphizing implants at RT (a) and cryogenic (b)implant conditions.

SDE and halo implants of doping and non-dopingco-implant species at cryogenic wafer temperaturesenable a reduction of those components of deviceleakage that are related to residual, implant induceddefects. Cryogenic implants also reduce devicevariability by minimizing dopant transient enhanceddiffusion that is largely influenced by EOR damage.

(a) RT (b) -20°C (c) -40°C (d) -100°C

Silicon Surface

?/cSurface

Crystalline Silicon

20.4nm16.3nm16.0nm

1.7nm

Partially Amorphous Complete Amorphization

250kx Magnification

5nm

(a) RT (b) -20°C (c) -40°C (d) -100°C

Silicon Surface

?/cSurface

Crystalline Silicon

20.4nm16.3nm16.0nm

1.7nm

(a) RT (b) -20°C (c) -40°C (d) -100°C

Silicon Surface

α/cSurface

Crystalline Silicon

High EOR damage Partially Amorphous Complete Amorphization

250kx Magnification

5nm

250kx Magnification

5nm

Fig. 4. XTEM of Si wafers implanted with 5keVcarbon to a dose of 1015 cm-2 at RT, -20 oC, -40 oC and-100 oC wafer temperature [3].

B. Contact resistance

Achieving a source/drain contact resistance todevice low enough to take full advantage of the highPMOS and NMOS drive currents achieved by mobilityenhancement techniques emerged as significantscaling challenge in sub-32nm devices. Its impact isprojected to be even stronger as devices scale downfurther.

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Fig. 5. Estimated dimensions of key MOS deviceelements for various device nodes.

The reason for contact resistance to emerge as amajor scaling challenge is illustrated in Fig.5. Thisfigure presents scaling trends for various MOS deviceelements from the 90 to the 22 nm nodes. Due to MOSdevice gate length (Lg) and spacer width scalingslower than the 0.7X node-to-node pitch scaling factorthe area available for contact via had to be reducedmore aggressively than the 0.7X pitch scaling resultingin disproportionate growth of contact resistance. Tomitigate this effect significant efforts have been madeto reduce sheet resistivity values of the NiSi SDcontact area with ion implantation playing a crucialrole in already adopted and emerging contactformation processes.

Multiple solutions are being implemented intoleading edge sub-32/28nm process integrationsequences. One of the approaches relies on apre-amorphization implant (PAI) of a thin layer ofsilicon that is designated to be consumed by thesubsequent reaction with the deposited Ni to form theNiSi film. This approach is based on the phenomenonwhere the reaction of Ni with amorphous siliconresulting in formation of the targeted phase of nickelsilicide occurs at temperatures lower than that requiredfor crystalline silicon [4]. Such an approach enablesimprovement of the planarity (morphology) of theinterface between nickel silicide and silicon therebyimproving silicide sheet resistance and widening thetemperature window prior to silicide converting to thehigher resistivity NiSi2 phase [5]. PAI when combinedwith carbon co-implant at -100 oC further improves theinterface morphology since the reduced EOR damageand the additional trapping of remaining siliconinterstitials by carbon further suppressing NiSiagglomeration and formation of NiSi silicide pipingdefects [6].

Wafer Temperature (°C)

Re

sis

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oh

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/sq

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implant

With -100°C

carbon implant

With RT carbonimplant

NiSi formation

200 400 600 800 10000

50

100

150

Fig. 6. Structured wafers results for silicide resistanceusing no implant (red line), and with a 1keV 1e15 cm-2

carbon implant at room temp (green line) or -100°C(blue line) [6].

It has been demonstrated that further improvement ofthe NiSi interface planarity and suppression of pipingdefects can be achieved by replacing the second soakRTA anneal with a laser anneal in a thermal cycle usedto form nickel monosilicide [7].

Fig. 7. Improvement of NiSi interface planarityenabled by replacing second soak RTA anneal withDynamic Laser Anneal (DSA) at elevated wafertemperature and millisecond pulse duration.

Significant opportunity to further reduce contactresistance resides in minimizing the potential barrier(Schottky Barrier Height – SBH) existing betweenNiSi and the device source/drain regions. To somedegree this is achieved by maximizing theconcentration of electrically active dopant at thesilicide/silicon interface. Yet, the realization of theultimate improvement opportunity requiresmetallurgical engineering of the silicide-to-Si interfaceeither by deploying new silicide materials or byincorporation of exotic species at the NiSi/Si interface.Yeo et al investigated silicide film resistivities andSBH values for various silicides types. For NiSi SBHis reduced by incorporating a high concentration ofdopant at the interface between NiSi and silicon and/orby incorporating into the interface region exoticspecies such as Al, Se, S [8,9].

Data in Figures 8 and 9 indicate that there is anopportunity for significant SBH reduction in NMOSby implantation of aluminum into the NiSi/nSi

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interface region. For PMOS SBH could be suppressedby modifying the properties of the NiSi/pSi interfacethrough combination of PAI, carbon co-implants andAl implant.

Fig. 8. Electron barrier height Bn versus film

resistivity for various contact silicides formed onsilicon. The labels “As+”, “S+” and “Se+” refer tosamples in which arsenic, sulphur and seleniumwere implanted prior to silicidation [9].

Fig. 9. Impact of various implants on the effectiveSchottky barrier height. In the absence of Ge PAI andCarbon implant, Al implant reduces the effective holeSBH. In the presence of Ge PAI and C implant, Alimplant reduces the effective electron SBH [10].

Overall, as device pitch continues its 0.7Xnode-to-node scaling beyond sub-20nm nodes, theimpact of contact resistance scaling is expected tobecome only more severe regardless of whether theindustry stays with a planar device architecture or istransitioning to FinFET devices. To address thecontact resistance issue implanters capable ofimplanting novel exotic species and performingimplants at cryogenic conditions are required.

C. Device and Process Variability

Device variability and narrowing processmargins have been identified as another critical scalingissue at the introduction of the 45nm node [11]. Asdevices scale down the device variability inherently

increases both because of fundamental attributes ofplanar bulk silicon devices and due to the increasingvariability of key manufacturing processes.

(a) (b)

Fig. 10. Illustration of stochastic nature of dopant atomplacement in device channel (a). Vth variation (RDFeffects) vs. device channel volume (b) [12].

One source of planar bulk silicon variability isattributed to Random Dopant Fluctuation (RDF)effects [12]. RDF effects arise from the fact that asplanar devices scale down the number of dopant atomsin the device channel region progressively decreases tothe point where sub-32nm devices have only hundredsof dopant atoms in the channel. Even though on amacro scale channel, halo and SDE implants havetypically better than 1% 1 dose uniformity, statisticalvariations of dopant atoms in channel regions ofsub-32nm devices, as illustrated in Figure 10a, couldbe several times higher leading to inherentprogressively increased Vth variability as devices arescaled down, see Fig. 10b [13].

In addition to RDF effects that are stochastic in theirnature and can only be mitigated through devicearchitectural solutions there are also significantsystematic sources of device variability attributable tovarious device manufacturing processes including ionimplantation. Fig. 11 presents a pareto analysis ofTCAD-modeled Ion sensitivities in 32 nm NMOSdevices to a various implant parameters including ionbeam angle setting accuracy [6].

Fig. 12. Pareto analysis of 32nm NMOS devicesensitivity to a variety of process variables.

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Energy purity (zero or near zero energycontamination) has been realized as an importantemerging requirement for both improving deviceIon/Ioff characteristics as well as reducing processvariability especially for ultra-low energy implantswhen the beam is typically extracted at initial energieshigher than that set in the final implant recipe. Anotherrecently emerged contributor to device variations hasbeen linked to run-to-run changes of beam currentdensity. Beam current density effects on processmargins have been attributed to the wide adoption inscaled down device process integration flows ofvarious defect engineering approaches and to thereduction of post implant anneal thermal budgets. A.Lee et al reported [14] that implantation of pSD andnSD doping species and of carbon co-implants atcryogenic wafer temperature results, as shown in Fig.13, in reduced device mismatch (Vt) in DRAM senseamplifiers. It also improves DIBL and GIDL.

Fig. 13. 11% PMOS and 12% NMOS improvement ofVth mismatch in DRAM sense amplifier with pSD andnSD implants performed at cryogenic temperature [14].

D. Implant application for addressing scalingissues and widening process margins innon-doping related process modules.

Materials engineering by ion implantation hasbeen demonstrated to enable widening processmargins and reducing the variability in several devicefabrication modules not related to transistor formationdoping processes. Most notable of those are etch [xxx]and lithography. In the lithography module Line Edgeand Line Width Roughness (LER and LWR) areamong the most significant contributors to systematicprocess variations. One of the recent areas of thedevelopment focus is deployment of PrecisionMaterials Modification (PMM) approaches to expandlithography process margin and to reduce LER andLWR [15]. Ion implantation into photoresist maskingfeatures has been demonstrated to enable reduction ofLER/LWR while having a minimal impact on otherimportant PR feature characteristics – its CriticalDimensions (CD) and Profile [16].

To comprehend the impact of the ion implantedtreatment to the resist material, it is valuable to

examine the Fourier decomposition of the roughnessinto the spectral frequency components. The data inFig.14 shows that ion implantation yields up to 50%improvement in the overall roughness by primarilyimpacting the mid range roughness but also the lowfrequency or long range roughness of the patternedimage. Depending on the design attributes, significantimprovement in mid and low frequency roughness candirectly be tied to improvements in device variability.

Fig. 14. LER spatial frequency in 193i resist maskingfeatures for various implantation treatments. NoteLER reduction in mid-range spatial frequencies thatare most detrimental for Vth variability [16].

E. Advanced Ion Implantation Technology

To take full advantage of the doping and defectengineering approaches described above and ofPrecision Materials Modification opportunities it isnecessary that advanced implant tools for sub-20nmnode incorporate a variety of novel features andcapabilities. These tools must have ability to performimplants into wafers cooled down to cryogenictemperatures, support implant requirements for a widearray of doping, co-implant and exotic species somewith energies down to 200 eV. To expand processmargins and reduce device variability leading edgeimplant tools must have engineered into them beamangle control and correction capabilities to achievebeam angular position accuracy of about 0.1o and haveenergy filters and capabilities for recipe driven beamcurrent density setting. These leading edge tools mustalso meet ever tighter particulate and metalscontamination control requirements. Figure 15contains a schematic of the VIISta Trident HC fromApplied Materials/Varian Semiconductor Equipment,the latest generation of high current implanters.

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Fig. 15. Example of advanced implanter beam-linearchitecture (AMAT/VSE VIISta Trident HC). Thebeam is generated by an ion source and passes throughanalyzing, angle corrector magnets and energy filter toproduce a horizontally uniform ribbon beam forimplanting a vertically scanned 300mm wafer that canbe cooled down to cryogenic temperatures.

3. Conclusions and Summary

Sub-32nm scaling of planar bulk Si devicespresents a set of unique scaling issues. Device leakage,low contact resistance and variability of devicecharacteristics are among the most critical ones. Ionimplantation has emerged as one of the most criticalIC manufacturing processes enabling sub-32nmscaling. It has an unique ability for precise placementof dopants on the nm scale both for depth and lateraldistributions. It provides device designers and processintegration engineers with new junction engineeringand Precision Materials Modification capabilities. Thelatest generation of advanced ion implantationequipment incorporates unique capabilities supportingcurrent and emerging requirements for sub-20nmdevices.

Acknowledgments

I would like to thank Hans-Joachim Gossmannfor performing TCAD simulations giving insight intodevice engineering approaches reviewed in this paper.I also would like to thank Pat Martin and Fareen Khajafor sharing results of their work on novel implantapplications, Thomas Parrill, Ludovic Godet, andTony Renau for valuable technical discussions andProf. Yee-Chia Yeo for fruitful collaborations oncontact resistance reduction and other projects.

References

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[14]. A. Lee, S. Jin, Y. Joo, I. Jang, J. Cha, K. Jeong, H.Kang, C. Cho, J. Jang, S. Hwang, “How to improve sub40nm transistor properties by using ion implantation”,Proceedings of 18th International Conference on IonImplantation Technology (Kyoto, Japan, 2010), P.37

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