device maksimovic

8/19/2019 Device Maksimovic

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ECEN 4827/5827 Supplementary Notes

1. Review: Active Devices in Microelectronic Circuits

c 2005 Dragan MaksimovićDepartment of Electrical and Computer Engineering

University of Colorado, Boulder

The purpose of this part of the notes is to briefly review some of the prerequisite coursematerials related to characteristics of active device in microelectronic circuits. We summarizedc, large-signal and small-signal (incremental) models of two major types of active devices usedin analog, digital and mixed-mode integrated circuits: metal-oxide-semiconductor field-effecttransistors (MOSFET), and bipolar junction transistors (BJT). Several examples are used toillustrate approaches to analysis of DC, and AC (small-signal) properties of electronic circuitsat the device level.

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PMOS

NMOS

(d)(c)(b)(a)

Di

Di

SDv

-

+SGv

-

+

G

D

S

G

D

S

G

B

D

S

G

GSv

DSv G

-

+

-+

S

D

G

S

D

G

S

B

D

G

Figure 1: Symbols currently in use for “enhancement-mode” MOS transistors: (a) symbolsof MOS transistor as 4-terminal devices; (b) symbols of MOS transistors with the substrate(B)shorted to the source (S) terminal; (c) symbols of MOS transistors with implied (default)connections of the substrate (B) terminal; (d) symbols commonly used in digital circuits wheresource (S) and drain (D) terminals are not specified.

1 Metal-oxide-semiconductor field-effect transistor (MOSFET)

Prior to reading this section, it is useful to review suggested reference textbooks on CMOStechnology, and physics of n-channle (NMOS) and p-channel (PMOS) devices.

Various symbols for “enhancement-mode” NMOS and PMOS devices are shown in Fig. 1.On an integrated circuit, MOS transistor is a 4-terminal device, as indicated by the symbol

in Fig. 1(a). In a standard, p-substrate CMOS technology, an n-channel (NMOS) device isbuilt on a p-type substrate (B terminal). The n-type source (S) and drain (D) regions are thedevice “output” terminals. The gate (G) is isolated from the substrate by a thin layer of oxide.A p-channel (PMOS) device is built with p-type source and drain regions in an“n-well,” whichserves as an n-type substrate (B),

Depending on the voltage applied between the gate (G) and source (S) terminals, a con-ducting channel can be established between the drain (D) and the source (S). If the substrateterminal (B) is shorted to the source (S) terminal, the MOS transistor can be considered a3-terminal device, and the symbols in Fig. 1(b) are in use. If the substrate terminal (B) isconnected to a default voltage rail (negative supply rail for p-substrate, positive supply rail

for n-wells), the MOS transistor can be considered a 3-terminal device, and the symbols inFig. 1(c) are in use. Finally, in digital CMOS circuits, where the distinction between the source(S) and drain (D) terminals is not important, the symbols in Fig. 1(d) are commonly used.

1.1 Dc characteristics and operating modes (i.e. operating regions)

Typical DC output-plane iD(vDS ) characteristics for an NMOS device are shown in Fig. 2.These characteristics are obtained by PSpice simulation of the circuit shown in Fig. 2.

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Di

GSv

DSv -

+

-

+

2N6782

2

1

0

-1.0V 0.0V 1.0V 2.0V 3.0V 4.0V 5.0

VDSid(m1)

15mA

10mA

5mA

-0mA

-5mA

K=1.5mA/V^2

Vt=2V

v_DS

i_D

3 2

1

VGS=5V

VGS=4.5V

VGS=4V

VGS=3V

VGS=3.5V

VGS < Vt

MOS output characteristics (2N6782, mos.cir)

Figure 2: Dc characteristics of an n-channel MOS transistor (2N6782), as obtained by PSpicesimulation ( mos.cir). Boundary iD = K v

2DS between saturation (region 2) and triode (region

3) modes is also shown.

Glossary

• Threshold voltage: V tFor an NMOS device, gate-to-substrate voltage greater than the threshold V tn = |V tp| =V t causes formation of an inversion layer of free electrons (conducting channel) in thep-type substrate. The threshold voltage V t is positive for “enhancement-mode” devices ina standard CMOS technology, typically between 0.5V and 1.5V. If the gate-to-substratevoltage at a certain point between source and drain is greater than the threshold voltage,we say that the channel is “on” at that point. Otherwise, the channel is “off”. Notethat for NMOS devices the threshold voltage V tn is positive, while for PMOS device thethreshold voltage V tp is negative.

A “depletion-mode” NMOS device has a built-in conducting n-type layer in the p-substrate between the drain and the source, so that it takes a negative gate-to-substratevoltage to turn the channel “off”. For a depletion-mode n-channel MOSFET, V t is neg-ative, but all other characteristics are the same as for the enhancement-mode devices.

• Conductance parameter: K The conductance parameter K is proportional to the channel width W , inversely pro-portional to the channel length L, and proportional to the gate-to-channel capacitanceper unit area C ox,

K = W

L

µC ox2

, (1)

where µ is the carrier mobility (electron mobility µn for n-channel devices, hole mobility

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3

11

saturation

triode

3

GD

GS

Vt

Vt

|Vt|

|Vt|

saturation

triode

PMOSNMOS

GD

GS DG

SG

SG

DG

cutoffcutoff

22

vv

vv

vv

vv

-

- +

+ -

- +

+

Figure 3: Operating modes of an NMOS and a PMOS transistor.

µ p for p-channel devices).

Summary of dc characteristics

• For vDS > 0 (NMOS devices), or vSD > 0 (PMOS devices), the MOSFET can operatein one of the three main operating modes: cutoff , saturation or triode , depending thewhether the channel is on or off on the source (S) and the drain (D) ends. Fig. 3 showsthe operating modes in the |vGD| vs. |vGS | plane for NMOS and PMOS devices. Thesummary here is for an NMOS device with V tn = V t > 0.

1. cutoff (region 1 in Fig. 2): vGS < V t, vGD < V t, the channel is “off” at both thesource (S) and drain (D) ends. Consequently, iD = 0 and the device is cut off.

2. saturation/active (region 2 in Fig. 2): vGS > V t, vGD < V t, the channel is “on”at the source end, “off” at the drain end. The drain current is nearly independentof the drain-to-source voltage. This operating mode is similar to the active modefor the bipolar transistors.

In the saturation/active mode, the steady-state characteristics of an NMOS tran-sistor are described by:

iD = K (vGS − V t)2(1 + vDS /V A) ≈ K (vGS − V t)2 (2)

The parameter V A is used to model the non-zero slope of the dc characteristics inthe saturation region. In many cases, we can assume that V A → ∞, i.e., that thedrain current iD in the saturation mode is independent of the voltage vDS .

In saturation, if vGS > V t, the drain current has quadratic dependence on the gate-to-source voltage vGS , as shown in Fig. 4. Because the drain (output) current canbe controlled by the gate-to-source (input) voltage the MOS transistor can be usedto build various signal-amplification circuits.

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biased as soon as |vDS | exceeds several tens of a volt. The device characteristic is verysimilar to the characteristic of a PN diode, as shown in the part of the characteristics inFig. 2 for vDS


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3.2V 3.4V 3.6V 3.8V 4.0V

VGSid(m1)

5.0mA

4.0mA

3.0mA

2.0mA

VGS

ID

gm = slope

Qcharacteristic

linearized

characteristic

device

non-linear

point

operating

DC

MOS i_D(v_GS) and gm (2N6782, mos-gm.cir)

Figure 5: Linearization of the MOS iD(vGS ) characteristic to obtain the transconductance gm.

G

S S

D

gs dsgs

-

+

v rvmg

Figure 6: The small-signal model of the MOS transistor operated in the saturation region.The model is exactly the same for both NMOS and PMOS devices.

The parameter gm is called the transconductance and is equal to the slope of the iD(vGS )characteristic at the DC bias point Q, as shown in Fig. 5, which is a blow up of Fig. 4 aroundthe point Q.

Similarly, the incremental output resistance is obtained as:

rds = ro = 1

gds=

∂iD∂vDS

−1

= V AI D

. (8)

Note that two symbols, rds or ro are used interchangeably to represent the device incrementaloutput resistance.

Several general comments about the device small-signal models can be made here:

• Small-signal models are linear , which allows all tools of linear system analysis to beapplied in order to examine and design signal processing electronic circuits. Circuitcharacteristics such as “gain”, “output resistance,” etc. can be obtained using the small-signal analysis.

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• Parameter(s) in the small-signal models depend on the location of the DC operatingpoint, i.e. on the DC bias. For example, see how the MOS transconductance or the MOSincremental output resistance depend on the DC bias current I D in Eqs. 7 and 8.

• To obtain the small-signal model of a circuit, one first needs to solve for the circuit DCvoltages and currents in order to obtain correct parameter values in the device small-signal models. Then, each device in the circuit is simply replaced by its small-signalmodel. The dc voltage sources are short-circuited, while the dc current sources are open-circuited, because the variations (signal components) of dc voltages are equal to zero.Signal sources remain in the small-signal model unaltered, as long as the assumptions of the small-signal modeling remain valid.

• Small-signal modeling involves linearization, i.e. neglecting all higher-order terms in theTaylor expansion of the actual nonlinear characteristics of the device. Therefore, allresults obtained from a small-signal circuit model are approximate. The small-signalmodel is exact only for infinitely small voltage/current variations around the DC oper-ating point.

• How small should the signals around the DC operating point be so that the resultsobtain from the small-signal model are sufficiently accurate ? The answer depends onwhat you mean by “sufficiently accurate”. In the design process, acceptable errors areusually much larger than what one might expect. The device parameters, to start with,are known only within some tolerances. In practice, small-signal models are commonlyapplied even if variations around the DC operating point are comparable to DC values atthe DC operating point, provided that the device does not leave the operating mode where the model is derived. For example, the small-signal MOSFET model cannot be appliedif the vGS voltage variation takes the device from saturation to cutoff or triode, because

the device characteristics change dramatically from one mode to another. As long as theMOSFET stays in the saturation mode, the results obtained from the small-signal modelderived for the saturation mode are meaningful. Once a hand design is completed basedon approximate models, tools such as computer simulation and prototyping are availablefor final performance verification.

2 Bipolar junction transistor (BJT)

Before reading this section, it is a good idea to review the bipolar junction transistor ICtechnology and physics of BJT’s from any of the suggested reference textbooks.

2.1 Dc characteristics and operating modes/regionsThe BJT symbols for the npn and the pnp devices are shown in Fig. 7. Typical dc characteris-tics for the npn device are shown in Fig. 8. The characteristics are shown in the output plane,I C vs. V CE , for a range of base currents I B.

Glossary

• forward current gain: β = iC /iB

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Ci

Bi

Bi

EBv

PNPNPN

CE

BEv

v EC

Ci

vB

C

E

C

E

B

-

+

-

+

-

+

-

+

Figure 7: Symbols for the NPN and PNP bipolar junction transistors.

-

+

Ci

Bi CEBEv

v

-

+

-1.0V 0V 1.0V 2.0V 3.0V 4.0V 5.0

vceic(q1)

10mA

8mA

6mA

4mA

2mA

0mA

VCES

3 2

1IB=0

VCE

IC

IB=10uA

IB=20uA

IB=30uA

IB=40uA

IB=50uA

BJT output characteristics (2N3904, bjt.cir)

Figure 8: Dc characteristics of an npn bipolar transistor (2N3904), as obtained by PSpicesimulation (bjt.cir).

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For integrated npn transistors at room temperature, in a standard bipolar technology,the current gain β in the active mode is typically between 100 and 300. The rangeof dc collector currents where the current gain has the highest value is between about10µA and 1mA for a device with 5µm2 emitter area. A larger device can be designed tomaintain the high current gain at higher collector currents. The current gain increaseswith temperature.

• (common base) current gain: α = iC /iE ,Since α = β β +1 , and β 1, α ≈ 1 in the active mode.

• saturation voltage: V CES When the BJT operates in saturation (region 3 in Fig. 8), the dc characteristics aresteep, and the voltage between the collector C and the emitter E is nearly constant. In asimplified DC model for the saturation mode, vCE ≈ V CES ≈ 0.2V is assumed constant.

• Early voltage: V AThis is the parameter that quantifies the finite slope of the transistor characteristics inthe active mode (region 2 in Fig. 8). V A is 100 − 300V for npn devices in a standardbipolar process.

• Breakdown voltage: BV CEOCollector-to-emitter voltage equal to or higher than BV CEO causes breakdown of thedevice and results in a steep increase in the collector current (not shown in Fig. 8). Thebreakdown voltage is 50V for a standard bipolar process. There is a variety of bipolarprocesses with different breakdown voltages.

Summary of BJT dc characteristicsFor the purpose of hand analysis, it is appropriate to identify the distinct operating modesand the corresponding simplified models of bipolar transistors.

• For vCE > 0 (for npn), (vEC > 0 (for pnp)), the bipolar transistor can operate in one of the three main operating modes, as shown in Figs. 8 and 9:

1. cutoff (region 1 in Fig. 8): both the BE junction and the BC junction are reverse-biased (off);

2. active region (region 2 in Fig. 8): the BE junction is forward-biased, and the BC junction is reverse-biased.

If a BJT operates in the active mode, its characteristics are described by:

iC = I CO (evBE/V T − 1)

1 +

vCE V A

, (9)

iC = βiB

1 +

vCE V A

. (10)

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3

1

3

1

PNP

CB

EBBC CB

EB

NPN

cutoff cutoffactive active

2 2

saturation saturation

BC

BE

v v

v v

BEv v

v v-

-

+

+

-

-+

+

Figure 9: Operating modes of an NPN and a PNP bipolar transistor.

The characteristics in the active mode can be approximated by:

iC = I COevBE/V T , (11)

iC = βiB . (12)

Since the BE junction is forward biased in the active mode, the base-to-emittervoltage can be found using one of the following two approximations:

(a) (accurate, but nonlinear:) vBE ≈ V T ln(iC /I CO ), or

(b) (simple:) vBE ≈ V BE = 0.7V.3. saturation (region 3 in Fig. 8): both the BE junction and the BC junction are

forward-biased.

If a BJT operates in saturation,

V CE ≈ V CES , (13)

iC < βiB . (14)

• In the summary of BJT dc characteristics, everything holds for pnp transistors, exceptthat reference polarities of the device voltages and currents are reversed, as indicated inFigs. 7 and 9

2.2 Small-signal (incremental) model at low frequencies

If the BJT operates in the active mode, at a DC operating point (V CE , I C ), the small-signal(incremental) model is shown in Fig. 10.

The parameters in the model depend on the DC bias operating point as follows:

gm = ∂iC ∂vBE

= I C V T

, (15)

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C

EE

B

-

+

pirbev cerbevmg

Figure 10: Small-signal model of the BJT operating in the active mode.

rπ = 1

gbe=

∂vBE ∂iB

= ∂vBE

∂iC

∂iC ∂iB

= β

gm, (16)

rce = 1

gce=

∂vCE ∂iC

= V AI C

. (17)

The partial derivatives are evaluated at the dc operating point (V CE , I C ).

3 Operating modes: the key to solving microelectronic circuitsat DC

An essential component of electronic circuit design is to ensure that all devices operate in theoperating modes best suited for the application. For example, transistors in amplifier stages areusually biased to operate in the active mode (BJTs) and saturation (MOSFETs). Devices inlogic gates are usually forced to operate in either cut-off (fully off) region or fully on (saturationfor BJTs, triode for FETs). Because the device characteristics are so much different dependingon the operating mode, the first step in understanding any electronic circuit at the device

level is to determine the device operating modes and the corresponding DC bias solution. Asummary of large-signal DC characteristics can be found in Section 1.1 for MOSFETs, andSection 2.1 for bipolar transistors.

Finding correct operating modes is discussed in this section with reference to several exam-ples of circuits with bipolar transistors. These examples are taken from actual circuit diagramsof more complicated integrated circuits.

In the examples of Fig. 11, the objective is to determine the operating modes of all transis-tors and to find the DC bias solution. We assume that all devices have identical characteristics,that V CC >> |V BE |, |V BE | > |V CES |, and β >> 1. The solutions are as follows:

a) The BE junction is forward biased from +V CC through R. Therefore, V B = V BE andI B = (V CC

− V BE )/R. The device Q is either in the active mode or in saturation.

Assume that the device is in saturation. Then, V C = V CES , but this is impossiblebecause V C = V CC . Therefore, Q is in the active mode and I C = βI B .

b) The EB junction is shorted by the resistor R, and therefore reverse biased. I B = 0, andV B = V CC . The CB junction is therefore reverse-biased by V CC , and Q is cutoff, I C = 0.

c) As in a), V B = V BE and I B = (V CC − V BE )/R. Again Q is in the active mode orsaturated. Assume that Q is saturated. Then, V C = V CES , and I C = (V CC − V CES )/R.

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(f)

(e)(d)

(c)(b)(a)

VC

VB

VB

VC

VC2

VC2

VC2=VC4

IC2IR IC2

IR

IC22(IB)

IR

ICIB

IC

IC

IB

R1

R

R1

R

L

L

R

R

R Q4Q3

Q2Q1

Q2Q1

Q2Q1

+VCC+VCC +VCC

+VCC +VCC

+VCC

Q

Q Q

R R R R

Figure 11: Examples of finding correct operating modes of bipolar transistors.

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Since

I C = V CC − V CES

R < β

V CC − V BE R

= βI B , (18)

the device is indeed saturated, i.e., the initial assumption has been verified.

d) The CB junction of Q1 is shorted and the EB junction of Q1 is forward biased from V CC through R. Therefore, Q1 is in the active region. The device with the base shorted tothe collector is said to be diode connected . It behaves as a two-terminal pn diode. TheEB junction of Q2 is forward biased by exactly the same voltage as the EB junction of Q1. Therefore, I B1 = I B2 = I B , and Q2 is either in the active mode or in saturation.The current I R is given by

I R = V CC − |V BE |

R = I C 1 + 2I B . (19)

So, we can solve for the collector current of Q1,

I C 1 = I R

1 + 2/β ≈ I R . (20)

If Q2 is active, I C 2 = β I B = I C 1 ≈ I R, and the voltage across the load RL is RLI C 2 ≈RLI R. As long as the device is active, the load current is constant and set by I R, for anyvalue of the load resistance RL. This is why the configuration (d), known as the current mirror is frequently used in integrated circuits as a current source. The condition for Q2to operate in the active mode is that the CB junction of Q2 is reverse biased, which isthe case for V C 2 up to V CC − |V CES |. So, the current mirror operates as a current sourcefor load resistances up to:

RL < RLmax = V CC − |

V CES |I R (21)

For RL > RLmax, Q2 is saturated, and I C 2 = (V CC − |V CES |)/RL is less than I R.e) This is the current mirror with npn transistors. We have exactly the same conclusions

as in d), except that I C 2 < I R because the voltage drop across R1 in the emitter of Q2reduces the BE forward-bias voltage vBE 2 with respect to vBE 1. To solve for I R we canstill apply the approximation vBE ≈ V BE = 0.7V,

I R = V CC − V BE

R , (22)

but to solve for I C 2, this approximation is inadequate because it would imply that I C 2 =0. Instead, since the solution depends on the difference between two forward-biasedBE junctions, we need to use a more accurate exponential description of the devicecharacteristic. From:

vBE 1 = vBE 2 + R1I C 2 (23)

we have

V T ln I RI CO

= V T ln I C 2I CO

+ R1I C 2 (24)

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or

V T ln I RI C 2

= R1I C 2 , (25)

which can be solved numerically for any given set of parameters. Note that for R1 = 0we get I C 2 = I R as in the current mirror d).

f) This example combines the examples d) and e). Q1 and Q3 are diode-connected devicesin the active mode, with I R = (V CC − 2|V BE |)/R. Assuming that Q4 is active, I C 2 < I R,as found in e). Assuming that Q2 is active, I C 2 = I R, which gives a contradiction.Therefore Q2 must be saturated with I C 2 < I R = βI B2, which confirms the saturationof Q2. Finally, we have: V C 2 = V C 4 = V CC − |V CES |.

You should try solving the examples again if all npn transistors are replaced with NMOSdevices and all pnp transistors are replaced with PMOS devices. Assume that all MOSFETshave the same |V t| < V CC and K .

4 Applications of small-signal (incremental) device models

As discussed in Section 3, the purpose of dc biasing is to ensure that all devices are in thedesired operating modes. The dc solution gives all steady-state dc voltages and currents.It is then of interest to predict the circuit response to time-varying (ac) inputs. This can beaccomplished using the device large-signal nonlinear models. Unfortunately, for design-orientedhand analysis this approach usually yields intractable results, and little useful information.Instead, we simplify the task by linearizing the nonlinear device characteristics around the dcoperating point. See the derivation of small-signal models for MOSFETS in Section 1.2 andBJTs in Section 2.2.

The small-signal analysis can be applied to obtain results such as:• Input-to-output transfer function that shows how the signal propagates through the circuit.

For example, we may want to determine the voltage gain of an operational amplifier inorder to predict how the finite voltage gain affects some op-amp application. As anotherexample, the small-signal analysis can be used to predict noise margins for a logic gate.This example is discussed in Section 4.1.

• Input or output impedance that allows us to predict interactions among various parts of a larger circuit, input sensors, and output loads.

For example, it is of interest to determine how large is the output resistance of a currentsource, i.e., how close the current source is to the ideal infinite output resistance.

In general, the small-signal analysis results show how the quantity of interest (gain, impedance,or something else) depends on:

1. the device parameters, and

2. the dc operating point.

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M1

M2

OIv v

+VDD

0V 1.0V 2.0V 3.0V 4.0V 5.0

Vinv(out)

5.0V

4.0V

3.0V

2.0V

1.0V

0V

VDD=5V

Vtn=-Vtp=1V

VIH

VIL

5

4

3

2

1

(2.48,3.48)

(2.51,1.51)

(4.00,0.00)

(2.875,0.41)

(2.125,4.59)

(1.00,5.00)

CMOS inverter: input-to-output characteristic (cmos.cir)

Figure 12: CMOS inverter and the vO(vI ) input-to-output characteristic. The device parame-ters are: V tn = −V tp = 1V, K n = K p = 30µA/V 2, V A = 50V, V DD = 5V.

As a result of the small-signal analysis, we can modify the design (change components, circuitconfiguration, or dc bias) in order to meet the specifications.

As an introduction to small-signal analysis, we consider the example of finding the noisemargins for a simple CMOS digital logic gate - an inverter.

4.1 Example: using small-signal analysis to determine the noise margins fora CMOS inverter

The CMOS inverter and its large-signal input-to-output characteristic are shown in Fig. 12.Depending on the operating mode of the two devices, the input-to-output characteristic has 5distinct segments.

In segment 1, vI is less than the NMOS threshold voltage, vI < V tn, so that M1 is cutoff.Since vSG2 is greater than the PMOS threshold voltage |V tp|, and since the drain current of M2 is zero, M2 is in the triode mode. The output voltage is vO = V DD.

In segment 2, vI > V tn so that M1 moves from cutoff to saturation. The output voltagestarts to drop as the current through M1 and M2 increases. M2 stays in the triode mode aslong as vDG2 >

|V tp

|, i.e., as long as vO

−vI >

|V tp

|.

In segment 3, both M1 and M2 are in saturation. A small change in the input voltagecauses a large change in the output voltage. In other words, the (negative) small-signal gainof the inverter in this segment is very large. M1 stays in saturation as long as vGD1 < V tn, i.e.,as long as vI − vO < V tn.

In segment 4, M1 is in the triode mode, and M2 is in saturation, as long as V SG2 > |V tp|,i.e., as long as vI < V DD − |V tp|.

In segment 5, M2 is cutoff, M1 is in the triode mode, and vO = 0.

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In the segments 2, 3, and 4, closed-form expressions for vO(vI ) can be obtained by solvingiD1 = iD2 using the device large-signal nonlinear characteristics described in Section 1.1.

Based on the characteristic of Fig. 12, the circuit in Fig. 12 can be used as a logic inverter:a logic LOW input level (close to zero) results in a logic HIGH output level (close to the supplyvoltage V DD), and vice versa.

The maximum input voltage that still corresponds to the logic LOW level is defined asthe input voltage V IL such the slope of the vO(vI ) characteristic at vI = V IL is equal to −1.Similarly, the minimum input voltage that still corresponds to the logic HIGH level is definedas the input voltage V IH such that the slope of the vO(vI ) characteristic at vI = V IH is alsoequal to −1.

Consider a logic gate with the dc voltage vI at the input, and a small noise voltage aroundthis dc value. This logic gate is assumed to be in a chain of other similar logic gates. If vI is inside the allowed ranges, i.e., if vI < V IL , or vI > V IH , the output noise signal due to theinput is smaller in magnitude than the input noise signal. Therefore, as long as vI < V ILor vI > V IH , reliable logic levels can be maintained in the chain of logic gates. If the input

voltage vI is in the forbidden region V IL < vI < V IH , the noise is amplified, which may resultin erroneous logic levels in the subsequent logic gates. This is why V IL and V IH , where thesmall-signal voltage gain of the gate is equal to −1, have been selected as the noise margin limits.

The noise margins for reliable operation of a logic gate show how far an input voltage levelcan be from the nominal output voltage level,

NML = V IL − V OL (26)

NMH = V OH − V IH (27)In the CMOS inverter, the nominal output voltage levels are V OL = 0 (LOW) and V OH = V DD

(HIGH).We can apply small-signal analysis to determine V IL , V IH and therefore the noise margins

for the CMOS gate of Fig. 12. For simplicity, we assume that K n = K p = K and V tn = |V tp| =V t.

Let us first determine V IH in the segment (4) of the vO(vI ) characteristic. Since we knowthat M1 is in the triode mode, we start with the device large-signal device characteristic

iD1 = K

2(vGS 1 − V t)vDS 1 − v2DS 1

, (28)

and derive the device small-signal parameters following the approach described in Section 1.2.We assume that the total drain current iD1 consists of the dc value I D1 and a small ac signalcomponent i

d1,

iD1 = I D1 + id1 . (29)

We are interested in the response for the small ac signal only, which can be obtained byretaining only the first-order terms in the Taylor expansion of the large-signal characteristic:

id1 = ∂iD∂vGS

vgs1 + ∂iD∂vDS

vds1 (30)

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ov

(M2 in saturation)

im2g v

(M1 in triode)

imt1g v

dst1iv r

D1=D2

S1

S2

G1=G2

-

+

-

+

Figure 13: The small-signal model of the CMOS inverter in segment 4 of the vO(vI ) dc char-acteristic.

where the partial derivatives are computed at the dc operating point given by I D1, V GS 1 andV DS 1. The expression for small-signal components can be written in terms of circuit parametersas:

id1 = gmtvgs1 + 1

rdstvds1 (31)

where:

gmt = ∂iD∂vGS

= 2KV DS 1 , (32)

1

rdst = ∂i

D∂vDS = 2K (V

GS 1 − V t − V DS 1) . (33)Note the subscript t used to distinguish the small-signal parameters in the triode mode fromthe small-signal parameters gm and rds derived earlier for the MOS transistor in saturation(Eqs. (7) and (8)). In the segment 4, we know that M2 operates in saturation, and so the modelof Fig. 6 and the parameters in Eqs. (7) and (8) can be applied. With V A → ∞, rds → ∞.

The complete small-signal model of the CMOS inverter in segment 4 of the vO(vI ) charac-teristic is shown in Fig. 13.

From the model, the boundary V IH can be determined from the condition that the small-signal gain is equal to −1:

vovi

= −(gm2 + gmt1)rdst1 = −1 . (34)

We evaluate the small-signal parameters at the point V GS 1 = vI , V SG2 = V DD−vI , V DS 1 = vO,

V DD − vI − V t + vO = vI − V t − vO , (35)

which yields

vO = vI − V DD2

. (36)

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Finally, V IH is found at the intersection of the characteristic vO(vI ) and the straight line givenby Eq. (36):

vO(V IH ) = V IH − V DD2

, (37)

To solve for V IH , we make use of the expression vO(vI ) for the dc transfer function of theinverter in segment 4 of the characteristic. The solution to Eq. (37) is:

V IH = V DD

2 +

V DD − 2V t8

. (38)

Similarly, one can find the expression for V IL in segment 2 of the vO(vI ) characteristic,

V IL = V DD

2 − V DD − 2V t

8 . (39)

For numerical values: V tn = −V tp = 1V, and V DD = 5V, we have V IL = 2.125V, V IH = 2.875V,

NM L = N M H = 2.125V.

4.2 Small-signal analysis techniques

In this section we discuss how the small-signal device models can be applied efficiently sothat the results for more complex circuits can be obtained with minimum of (usually messy)algebra. For now, we assume low-frequency signals so that the low-frequency device modelscan be applied. For efficient small-signal analysis, we rely on the following techniques:

1. prior knowledge of the incremental resistances “seen” looking into the device terminals;

2. prior knowledge of the final results for simple, frequently repeated circuits;

3. approximations based on known parameter relations, and applied before, and during theanalysis, not after messy (and probably wrong) final results are obtained.

4. usual circuit-analysis short-cuts (voltage and current dividers, parallel and series impedancecombinations, Thevenin and Norton equivalents).

The incremental resistances “seen” at the device terminals can be determined just once, andthen used as needed. Consider an arbitrary circuit shown in the left-hand side of Fig. 14. Anarrow is used to indicate the port where we seek the incremental resistance (or impedance ingeneral) seen between the port terminals. In general, the incremental resistance “seen” at agiven circuit port can be determined by the small-signal analysis where a test source (voltagevt or current it) is placed at the port and the response (current it or voltage vt) is found. The

incremental resistance Rx “seen” at the port is then found as Rx = vt/it.

4.3 MOS incremental resistances

Fig. 15 shows the incremental resistances looking into the gate (G), source (S) and drain (D)terminals of a MOS transistor operating in saturation. We assume that the dc bias has beensolved, and that the dc sources have been removed to obtain the small-signal model. Externalresistances RG, RD, RS are equivalent incremental resistances of the circuitry around the MOS

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-

+

Rx = vt/it

=> tv

ti

the circuitmodel of

small-signal

circuit

+VDD

Rx

Figure 14: Finding the resistance Rx “seen” when looking into a circuit port.

transistor. An n-channel device is indicated, but the same results are obtained for a p-channeldevice.

In this section, the symbol rds is used to represent the device incremental output resistance.

Note that the symbol ro is also in common use, ro = rds.The circuits used to solve for the resistances are shown in Fig. 15(a,b,c).

4.3.1 Resistance seen looking into the gate, Rg

From Fig. 15(a),Rg → ∞ (40)

by inspection. At low frequencies, MOS gate is a very high resistance node.

4.3.2 Resistance seen looking into the drain, Rd

To solve for Rd, we put a test current source it and find the voltage vt that the current sourcecreates at the drain, as shown in Fig. 15(b):

vt = RS it + (it − gmvgs)rds . (41)

But,vgs = vg − vs = 0 − RS it , (42)

so that:vt = RS it + it(1 + gmRS )rds , (43)

andRd =

vtit

= rds + (1 + gmrds)RS . (44)

You may try to derive the same result using a voltage test source.

Special cases and approximations

The product gmrds is always much greater than 1, and so a somewhat simpler expression forRd is obtained:

Rd ≈ rds(1 + gmRS ) . (45)

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GG

d s(c) small-signal model to find R(b) small-signal model to find R

S

S S

D

D D

G

G G

t

t

t

-

-

-

+

+

+

ds

dsds

r

rr

gs

gs gs

m

m m

g v

g v g v

g(a) small-signal model to find R

G

g

S S

S

s

d

DD

D

R

R

R

RR

R

R

R

R

R

RR

t

t

t

v

v

v

i

i

i

Figure 15: Incremental resistances seen when looking into the gate (a), drain (b), and source(c) of a MOS transistor.

21


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If, in addition, gmRS >> 1, Rd becomes:

Rd ≈ gmrdsRS (46)Note that for RS > 0, Rd can be much greater than either RS or rds.

If RS = 0, i.e., if the source is at ac ground, the resistance seen looking into the devicedrain is just the device output resistance rds,

Rd = rds = V AI D

. (47)

In the last expression, rds is shown as a function of the device parameter V A and the device dcoperating current I D.

In any case, even for RS = 0, the resistance Rd is relatively large. In other words, when thedevice operates in saturation, the drain current is almost independent of the drain-to-sourcevoltage.

4.3.3 Resistance seen looking into the source, Rs

To solve for Rs, we put a test voltage source vt and find the resulting current it, as shown inFig. 15(c):

it = −gmvgs + vt − vdrds

. (48)

Usingvd = RDit , (49)

andvgs = −vt , (50)

we obtain:

it = gmvt + vt − RDit

rds, (51)

which can be solved for Rs,

Rs = vtit

= rds + RD1 + gmrds

. (52)

You may try to derive the same result using a test current source.

Special cases and approximations

As for Rd, we can use the fact that gmrds >> 1 for the device, so that Rs becomes:

Rs ≈ rds + RDgmrds

= 1

gm+

RDgmrds

. (53)

The device output resistance rds

is frequently much larger than the resistance RD

seen in thedrain of the device. If rds >> RD, we have the simplest result for Rs,

Rs ≈ 1gm

= 1

2K (V GS − V t) = 1

2√

KI D, (54)

which can be used in most applications. In the last expression, we explicitly use the fact thatgm depends on the device parameters, K and V t, and the dc operating current I D.

Whenever RD < rds, the resistance seen looking into the source is in the order of 1/gm,which is relatively low.

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b

c

e

E

B

C

R

RR

R

R

R

Figure 16: Incremental resistances of the BJT.

4.4 BJT incremental resistances

As for the MOS devices, we can determine the incremental resistances for the BJT. You maytry to derive the results that are listed here with reference to Fig. 16. In this section, thesymbol rce is used to represent the device incremental output resistance. Note that the symbol

ro is also in common use, ro = rce.Using gmrce >> 1, we obtain the resistance Rb seen looking into the base:

Rb = rπ + (1 + β )RE ≈ rπ + βRE . (55)If RE = 0, Rb = rπ.

The resistance Rc seen looking into the collector is:

Rc = rce

1 +

βRE RE + rπ + RB

. (56)

If RE >> rπ and RE >> RB ,Rc ≈ βrce . (57)

If RE = 0, Rc = rce = V A/I C . In any case, Rc is relatively high.Using gmrce >> 1, we obtain the resistance Re seen looking into the emitter:

Re = RB + rπ

1 + β . (58)

If RB


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In general, Re is relatively small.Small-signal analysis of more complex structures will make frequent use of the incremental

device resistances derived in this section.

5 A Design Example

The device-level design example in this section illustrates how basic single-transistor amplifierstages can be combined together to meet a set of design specifications. We make use of theMOSFET large-signal and small-signal characteristics summarized in Section 1, and the small-signal analysis techniques discussed in Section 4. For discussion about configurations andproperties of the basic single-transistor amplifier stages (common source, common-drain, andcommon-gate), refer to the suggested reference textbooks.

Design Specifications

A magnetic pick-up can be represented as an ac voltage source |vg| < 10mV in series with aRg = 100kΩ resistance. It is desired to design a CMOS amplifier for the pick-up according tothe following specifications:

1. the DC output voltage is V O = 0V;

2. the small-signal voltage gain is Ao = vo/vg = 10;

3. the DC bias current through vg must be equal to zero.

4. the amplifier output resistance is Rout ≤ 1kΩ;To design the amplifier, the following components are available:

1. 2 discrete resistors, and 1 large capacitor (C → ∞);2. n- and p-channel enhancement-mode MOS devices;

3. two dc voltage sources, V DD = V SS = 10V, connected in series to obtain the ±10V supplyaround the ground.

All transistors have the same parameters: V tn = −V tp = V t = 1V, V A = 100V, and K n = K p =K = 20µA/V 2 for W/L = 1. The device conductance parameter K is directly proportionalto the channel width W to length L ratio. For each device, the ratio W/L can be selected toscale K . It is not necessary that all devices have the same K .

A solution consists of finding a suitable circuit configuration, and finding all device param-

eters (W/L of all MOSFETs, and resistances of all resistors) to meet the specifications.

Solution

The first step in the design is to choose a circuit configuration based on the design specifications.Since the required gain is |Ao| > 1, the amplifier should include at least one common-source(CS) stage. Since the gain of a CS stage is negative, two CS stages can be used to obtain theoverall gain Ao > 0. The capacitor can be used either for injecting the ac signal to the input of

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20uA

0.5mA

-VSS = -10V

+VDD = 10V

(W/L)4,6 = 25

(W/L)1 = 6.25

(W/L)2,3,5,7 = 1

900k

20uA

IRVG

V2

V1

I1

I3

I3

I2

I1C

R2 R1

Vo

-

+

Q7Q6

Q5

Q4Q3

Q2

Q1

Rg

Vg

Figure 17: One possible solution to the design problem.

the amplifier without disturbing the dc bias at the input, or to boost the gain of a CS stage byshorting the source to ac ground. Since both positive and negative supplies are available, theinput can easily be dc biased at 0 volts, so that the pick-up can be connected directly to theinput, without the capacitor in series. Instead, the available capacitor can be used to boost

the gain of a CS stage by shorting the source to ac ground.The second CS stage can also be designed to satisfy the output-resistance specification.

Alternatively, we may use a common-drain (CD, or source-follower) stage at the output, to meetthe specified output-resistance, and also to obtain the zero output dc bias without additionaldiscrete resistors. The amplifier stages can be biased using current mirrors.

Based on the above considerations, a possible amplifier circuit is shown in Fig. 17. Theinput side of the current mirrors, Q7, is dc biased from the dc supplies through R1. Thecurrent-mirror outputs, Q5 and Q6, serve as current sources to dc bias the input CS stagebuilt around Q1, and the output CD stage built around Q4. Q6 is also the active load for Q4.R2 is the load for the first CS stage. The output v1 of the first CS stage is the input to thesecond CS stage consisting of Q2 and Q3. The source-to-gate of Q2 is dc biased by the voltage

drop R2I 1 across R2. The diode-connected device Q3 is the load for Q2, and at the same timeit provides the dc bias V 2 at the gate of Q4 so that the output dc voltage V O can be adjustedto zero by selecting V GS 3 = V GS 4.

In the paper design, it is convenient to neglect the effects of finite V A on the dc biassolution, and on the small-signal results. Once the design is completed, the approximationscan be verified. Also, we assume that all devices are biased to operate in saturation, whichshould be verified once the design is completed.

A set of dc bias relations, and small-signal results can now be written for the circuit of

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Fig. 17:

R1 = V DD + V SS − V GS 7

I R, (60)

I 1 = K 5K 7 I

R , (61)

I 3 = K 6K 7

I R , (62)

I 2 = K 2 (R2I 1 − V t)2 , (63)

V 2 =

I 2K 3

+ V t , (64)

vO = V 2 − V GS 4 =

I 2K 3

−

I 3K 4

, (65)

The small-signal voltage gain can be found as:

Ao = vovg

=

v1vg

v2v1

vov2

≈ (−gm1R2)

−gm2

gm3

(+1) , (66)

while the output resistance is:

Rout ≈ 1gm4

. (67)

For all devices the transconductance:

gm = 2K (V GS − V t) = 2

KI D (68)

is evaluated at the appropriate dc operating point.Once the circuit configuration has been decided, and the necessary analytical results have

been determined, we proceed to determine the parameter values in order to meet the designspecifications. The set of design specifications is not sufficient to uniquely determine all pa-rameter values. Additional design considerations, depending on the application, may include:

1. minimization of the total device area; for a given channel length L, we attempt to mini-mize the ratios W/L for the devices;

2. minimization of the quiescent power consumption; we attempt to minimize dc bias cur-rents;

3. ability to handle large-amplitude ac signals without distortion; we attempt to dc biasthe amplifier so that the dc operating point is as far away from the operating-modeboundaries (triode or cut-off) as possible;

4. frequency-response and transient-response specifications.

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None of these additional constraints have been specified in this design problem, so that wehave some freedom in selecting the values.

Consider first the output-resistance requirement. From Eqs. (67) and (68), we have:

Rout = 12√

K 4I 3= 1kΩ . (69)

Select I 3 = 0.5mA, as a compromise between large power consumption and large device size.As a result, K 4 = 500µA/V

2, and

(W/L)4 = K 4

K = 25 . (70)

Note how a relatively large device and a relatively large dc bias current are needed to meetthe small output resistance requirement.

For Q2, Q3, Q5 and Q7, we select the minimum-size devices, (W/L)2,3,5,7 = 1, biased at

I R = I 1 = I 2 = I 3K

K 4=

0.5mA

25 = 20µA . (71)

To get I 3 = 0.5mA, we also select K 6 = K 4, i.e., (W/L)6 = (W/L)4 = 25.The dc gate-to-source voltage for all devices above is:

|V GS |2,3,4,5,6,7 = V t +

I RK

= V t +

I 3K 4

= 2V . (72)

From Eq. (60), we have R1 = 900kΩ, and from Eq. (63), we have R2 = 100kΩ. Also, V O =V GS 3 − V GS 4 = 0V, as required.

Since K 2 = K 3 = K , and Q2, Q3 have the same dc bias current I 2 = I R = 20µA, thesmall-signal gain from v1 to v2 is v2/v1 = −gm2/gm3 = −1. Therefore, the gain requirementfrom Eq. 66 becomes

Ao = gm1R2 = 10 , (73)

which yields:Ao = 2

K 1I 1R2 = 10 , (74)

K 1 =

Ao2R2

2 1I 1

= 125µA/V 2 . (75)

Therefore,

(W/L)1 = K 1

K = 6.25. (76)

To verify the assumption that rds is sufficiently large, we have (rds)1,2,3,5,7 = V A/20µA =5M Ω >> R2 = 100kΩ > 1/gm, and (rds)4,6 = V A/0.5mA = 200kΩ >> 1/gm = 1kΩ. Some

loss in the gain because of the finite rds can be easily compensated for by rounding (W/L)1up.

We proceed to confirm that that all devices are in saturation at the dc bias operating point.For the specified amplitude of the input signal, |vg| ≤ 10mV, it is also easy to confirm thatall devices remain in saturation for all time when the ac input is applied to the input. The acvoltages at v1, v2 and vo are within ±100mV around the dc bias.

As an excercise, run PSpice simulations of the circuit in Fig. 17 to verify that it meets alldesign specifications.

device maksimovic

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