development process of rhbd cell libraries for advanced socs tuvia liran [[email protected] ]...

Ramon Ramon ChipsChips

Development process of RHBD cell libraries for advanced SOCs

Tuvia Liran [[email protected] ]Ran Ginosar [[email protected] ]

Dov Alon [[email protected] ]Ramon-Chips Ltd., Israel

Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003

Ramon Chips


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About Ramon Chips• Private company• Based in Haifa; Israel• Incorporated in 2004• Developed the RadSafeTM technology• Accomplished and delivered several space

grade components to customers• Focused on advanced IC design for space


Latest SOC products

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JPIC -JPEG2000 encoder

GR712RC -Dual core LEON3FT processor


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Outline• Concepts of RadSafeTM technology• RadSafeTM libraries • Design considerations• Development vehicles used• RadSafeTM 0.13µ technology


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RadSafeTM concepts• Radiation Hardening is achieved only by design• Same technology for all space applications• Based on standard CMOS technology • Radiation hardening guaranteed by similarity to

previously qualified products/test chips• All IPs fully developed and owned by Ramon

Chips• Proven immunity on Tower Semi 0.18µ

technology• Complementary methodologies:

Design For Reliability Flow for SEU/SET mitigation Design for testability Electrical screening Class S screening flow


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Radiation & Reliability effects mitigated by RadSafeTM

• Radiation effects: TID SEL SEU/SET in flip-flops SEU in SRAMs SEFI caused by PLL/DLLs

• Reliability effects: Electro-migration Thermal cycling Chemical effects Mechanical (shock & vibration)


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Mitigating TID effects• Advanced CMOS process – ≤0.18µ with

STI

• Fixed geometry of transistors – fixed geometry of parasitic devices; insensitive to placement

• ~30% area penalty – much less than ELT

• TID immunity - >300Krad(Si)

INA

INB

OUT


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Performance under TID stress

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 0.25 0.5 0.75 1 1.25 1.5 1.07 2Vds(V)

Id(A

)

0.0000010

0.0000100

0.0001000

0.0010000

0.0100000

0.1000000

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vgs(V)

Id(A

)

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0 -0.3 -0.6 -0.9 -1.2 -1.5 -1.8

Vds(V)

Id(A

)

m

0.0000100

0.0001000

0.0010000

0.0100000

0.1000000

0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 -1.07 -2

Vgs(V)

Id(A

)

NMOS

PMOS

TID stress up to 250Krad(Si)


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TID effect on ring oscillator frequency

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12.2

12.4

12.6

12.8

13

13.2

13.40 50 100 150 200 250 300 350

TID(krad)

fre

q.

(MH

z) Dev #1Dev #2Dev #3Dev #4Dev #5

Ageing AnnealingBefore Irrad.

-481 stages of inverters with FO = 4- Maximum variation in frequency is <0.5%


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Mitigating SEU in flip-flops• Proprietary circuit• Optimized for area and power• LET threshold - ≥ 38MeV/cm2/mg• SET mitigation by glitch filtering of

data • SET Filter for clock by several

techniques • Restricting the use of async Set/Reset• All flip-flops on chip accessed by SCAN


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Comparing FF alternativesArea

Power

TvalidCLK->out

LETThresholdMeV*cm2/mg

Errors/bit/day [@LEO]

(*)

Un-protected

1 1 1 2.94 5E-7

TMR 4.01 2.6 2.5 - -

DMR 2.48 2.2 2.5 - -

DMR+ 2.34 2.1 2.5 38.2 4E-14

SEP 1.8 1.6 1.2 38.2 4E-12

SER (**) 1.75 1.5 1.2 - -

• Relative values• Refers to standard FF, with scan, same output drive(*) Refers to 37o inclination, quite solar(**) Designed for 0.13u only


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I/O cell libraries• Two libraries:

For 1.8V core voltage For 3.3V core voltage

• Special rad-hard ESD cells• Special cells:

LVDS (>400MHz) SSTL, HSTL, AGP 5V tolerance Cold spare

• Proven on several chips


Special design rules for I/O cells

• RH mitigation: ≥2 guard rings All NMOS transistors ringed by P+/GND Special ESD considerations

• Other considerations for space ICs: Large pitch/size pads – enables thick Al bond

wires

Relaxed layout rules – reduced thermo-mechanical stress

Dual slope transition – reduced ringing

Double supply pads – reduced inductance & density

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RadSafe SRAM cellBL BLB

WL

Conventional SRAM cell

BL BLB

WLB

RadSafeTM SRAM cell

Many NMOS devices connected to bit-

lines

Only PMOS devices connected to bit-

lines


Examples of SRAM cores

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SRAM cell libraries• Variable sizes, up to 2Kx40• Two types of SRAM cores:

Single / dual port (>250MHz / >120MHz)

• Two operation voltages: 1.8V, 3.3V• DPRAM performs read & write access per cycle• Integrated EDAC & BIST in each core• Very low power; zero standby power• Protected from all radiation effects:

MBU is eliminated LET threshold 3 MeV·cm2/mg (before EDAC correction) In tests, all errors corrected by EDAC

• Testability features: Complementary BIST logic Speed control Weak write Iddq compatibility


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All-digital DLL cores• Three DLL cores for 3 frequency

ranges• Locking guaranteed & fast• Immediate re-locking• 0.05 mm2/core• 8 mW/core @0.18u• Highly protected from radiation

effects• Can be placed anywhere in the core• Powered by core supply lines


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Technology development chips

RADIC2•1.8/3.3V transistors•1.8/3.3V std. cells•1.8/3.3V ring oscillators•1.8/3.3V shift registers•4Kbit SRAM•ADDLL•FPGA converted chip

RADIC3•1.8V transistors•1.8V std. cells•1.8V ring oscillators•1.8V shift registers

•Several FF types•256Kbit DPRAM•ADDLL•LVDS I/O buffers

GR702RC•LEON3FT core by GR•Fully automatic flow•2 SpW ports w LVDS•2 ADDLL•10 SRAM cores


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RadSafe™ 0.13µ technology

• Density: Logic - >120Kgates/mm2 (40K at 0.18) SRAMs - >200Kbit/mm2 (80K at

0.18)

• Power - <40% of 0.18µ• Speed - >200MHz [for large chips]

• Special IPs: 10 bit, 1Msps, 1mW SAR ADC

• Status: Test chip ready for production


RADIC4 – Test chip for RadSafe_013 technology

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NMOS/PMOSXtors

3 delay lines/

SET monitor

3 shift registers

10b RH ADC(1Msps,1m

W)

4Kx72 RH SRAM

4Kx72 RH SRAMWith

processenhanceme

nt


10b Analog to Digital Converter

• Resolution: 10 bit• Sampling rate: 0.5Msps• Power: <1.5mW• Area: ~0.03mm2

• TID: >300Krad (target)

• Process: 0.13µ• Voltage: 3.3/1.2V

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Summary• RadSafe™ by Ramon Chips

Using standard process Using standard EDA tools & flow Proven Rad-Hard-by-design on several chips Optimized for performance, power &

reliability RH considerations applies to all levels of

design flow 0.13µ process provides significant

performance advantages

development process of rhbd cell libraries for advanced socs tuvia liran [[email protected] ]...

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