FEATURE

14

In order to share 8K Super Hi-Vision programs in broad-casting stations, we have been developing a transmission system using Ethernet technology. In this paper, we propose a clock recovery and control method for 8K signals as part of an uncompressed 8K signal transmission system over 100 Gigabit Ethernet with effective usage of transmission capacity as well as low jitter and low latency. We report the results of an examination using a test bed implement-ing the proposed method, in which the latency was 459 μs, frequency deviation was ±1ppm or less, and which satisfied the standard value of jitter specifications.

1. Introduction8K Super Hi-Vision featuring 33 megapixel video (16

times as many pixels as the current HD) is a system that provides a strong sense of reality to viewers, through the combination of ultrahigh-definition images with approxi-mately 4,000 scanning lines and a 22.2 multichannel sound system1) 2).

In today’s HD TV program productions, uncompressed video signals are used to transmit high-quality and low-latency images between cameras, monitors, editing tools, and other kinds of broadcast equipment. Therefore, when introducing 8K Super Hi-Vision in broadcasting stations in the future, a broadcast system designed for transmitting uncompressed 8K signals must be installed. Uncompressed HD signals were previously transmitted over a dedicated network that is different from an Ethernet network aimed at transmitting file-type data. In recent years, however, in order to promote efficient facility investment and broadcasting, uncompressed HD signal transmission based on 10 Gigabit Ethernet3) (10GE) has been introduced in broadcasting sta-tions4) 5). Furthermore, thanks to the standardization of 100 Gigabit Ethernet6) (100GE) by the Institute of Electrical and Electronic Engineers (IEEE), faster Ethernet-based data transmission is starting to be put to practical use, and its popularization is expected to lower the costs of communica-tion devices. Under such circumstances, it is considered ef-fective to introduce a 100GE-based system for transmitting uncompressed 8K signals in broadcasting stations in order to build more efficient and economical broadcasting equip-ment in the future.

For a video transmission system to recover video signals in a stable manner, the clocks on the receiving side should be synchronized with those on the transmitting side. When using a nonsynchronous data transmission network such

as Ethernet, clocks for video signals need to be recovered with a high degree of accuracy on the receiving side. A ma-jor example of clock recovery via a nonsynchronous net-work is the adaptive clock method7), which is suitable for simplifying the circuit architecture. This method controls clocks so that data accumulation at the reception buffer, where received data are temporarily accumulated, is kept constant. Until now, some clock recovery and control meth-ods, such as the Proportional-Integral-Differential Control-ler (PID Controller)8) *1 and the average data accumulation method9) *2, have been proposed within the adaptive clock method. Meanwhile, when it comes to accommodating un-compressed 8K signals in an Ethernet signal, there is one report10) of a method that recommends accepting only ef-fective data in an Ethernet signal after removing redundant parts in input signals. As a result, the signal transmission speed varies over time. If a conventional clock recovery and control method based on a fixed data speed is employed, the accumulation of data used for control information in the clock recovery and control cycle is likely to fluctuate, causing the jitter of recovered clocks to increase. In order to reduce such jitter, it is effective to increase the data accu-mulation in the reception buffer so that it can be kept at the same level throughout the clock recovery and control cycle.

Meanwhile, as data accumulation increases, data trans-mission latency also increases owing to possible data reten-tion in the buffer. This impairs the merit of uncompressed signal transmission. Therefore, we would like to propose a new clock recovery and control method based on the adap-tive clock method, when video signals with effective data are transmitted after their redundant parts are eliminated. Furthermore, we have developed a prototype for transmit-ting uncompressed 8K signals over 100GE and achieved low-latency and low-jitter performances. The results are explained in the following sections.

2. System requirementsRequirements for the system that transmits and receives

uncompressed 8K signals over 100GE are described as fol-lows.

First requirement: For stable video transmission, the jit-

Development of Uncompressed 8K Super Hi-Vision Signal Transmission over 100 GigabitEthernetJunichiro Kawamoto, Tsuyoshi Nakatogawa and Takuya Kurakake

*1 A method of controlling clocks by combining the time propor-tional value, the time integration value, and the time differen-tiation value of data accumulation in the reception buffer

*2 A clock control method based on the average of accumulated data in the reception buffer

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ter of video clocks recovered on the receiving side should be equal to or less than the standard value (the lower the better).

Second requirement: In order to take advantage of un-compressed signal transmission, latency between input and output signals should be as low as possible.

Third requirement: In order to transmit uncompressed HD signals and file data along with uncompressed 8K sig-nals within the 100GE bandwidth, Ethernet transmission bandwidth for uncompressed 8K signals should be as nar-row as possible.

Under these requirements, the functions and performanc-es required for the system are determined as follows.

With regard to the 1st requirement, video clocks recov-ered on the receiving side should meet the measurement standard for the jitter of uncompressed HD video signals (timing jitter*3: 1.0 UI or less*4; alignment jitter*5: 0.2 UI or less). As for the 2nd requirement, latency between input and output signals should be equal to or less than 1 video frame, which is 16.7 ms if the video frame frequency is set at 60 Hz (the lower the better).

A video frame in transmission signals consists of picture lines that include effective pixels, audio, auxiliary data, and redundant data (redundant parts where prefixed values are assigned) and nonpicture lines that include auxiliary data and redundant data (redundant parts). As a response to the 3rd requirement, effective data alone should be absorbed in Ethernet signals after removing their redundant parts in video and nonvideo lines on the transmission side. The re-dundant parts are to be recovered on the receiving side for video signals to be delivered.

3. Structure of developed equipment3.1. Flowchart of the whole system

A flowchart of the test equipment is shown in Figure 1. 8K signals enter into the transmission device in the form of

thirty-two 3Gb/s Serial Digital Interface (3G-SDI) signals.First, at each of the eight 10GE multiplexers, redundant

parts in picture and nonpicture lines are removed from the four 3G-SDI signals and only effective data are extracted. Then at each multiplexer, the four signals are converted to one 10GE signal, making eight 10GE signals in total. This process will be explained in detail in the following section. Next, at the 10GE-100GE converter, one 100GE signal is generated from the eight 10GE signals and sent to the re-ceiving device via Ethernet. The 10GE-100GE converter is a common Ethernet switch*6.

At the receiving device, the 100GE signal received via Ethernet is converted to eight 10GE signals. Next, each 10GE signal is sent to the 10GE demultiplexer, where four 3G-SDI signals are separated and recovered from one 10GE signal using video clocks generated at the clock recovery section inside the 10 GE demultiplexer. Finally, the 3G-SDI signals are reunited with the redundant parts in the picture and nonpicture lines, and delivered as 8K signals.

3.2. Multiplexing video signals on Ethernet packetsIn this section, we will explain how to multiplex four 3G-

SDI signals into one 10GE signal10). One video frame of the 3G-SDI signal consists of 1,125 picture or nonpicture lines. A picture line is composed of EAV (End of Active Video), LN (Line Number), CRCC (Cyclic Redundancy Check Code), HANC (Horizontal Ancillary), SAV (Start of Active Video), and effective pixels.11) Meanwhile, a nonpic-ture line consists of EAV-SAV*7 and VANC (Vertical An-cillary). As for the relationships between line numbers and picture or nonpicture lines, line numbers 1-20 are related to nonpicture lines; 21-560 to picture lines; 561-583 to non-picture lines; 584-1,123 to picture lines; and 1,124-1,125 to nonpicture lines. The number of successive picture lines is defined as Vline (= 540).

After removing the redundant parts, the amounts of effec-

Figure 1: Flowchart of test equipment

Transmission device

Receiving device

Ethernet

Recovered video clock

3G-SDI×32 3G-SDI×32

10GE×8

10GE-100GE

converter

10GE multiplexer#8

10GE-100GE

converter

10GE demultiplexer#1

10GE demultiplexer#8

Clock recovery section

10GE multiplexer#1

*3 Jitter whose frequency components range from 10 Hz to 148.5 MHz

*4 Unit Interval: duration of one clock cycle (one clock cycle =1 UI)*5 Jitter whose frequency components range from 100 kHz to

148.5 MHz

*6 A device that transfers Ethernet signals to an adequate output part, in reference to the delivery address inside the input Eth-ernet signal

*7 A combination of EAV, LN, CRCC, HANC and SAV

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tive data in a picture line stand at 735 bytes for EAV-SAV and 34,560 bytes for effective pixels. The increase in the amount of buffer data per picture line is defined as BS bits (=282 kbit). For nonpicture lines, the effective amounts of data for EAV-SAV and VANC stand at 735 bytes and 5,760 bytes, respectively.

The next step is to multiplex these data on an Ethernet packet12). Figure 2 shows how an Ethernet packet is com-posed. MAC (Media Access Control) client data*8 in the Ethernet packet should be Q-tagged frames (1,504 bytes at maximum)*9. Its components are a VLAN tag*10, an IP (In-ternet Protocol) header, a UDP (User Datagram Protocol) header, a RTP (Real-time Transport Protocol) header, and a RTP payload. The RTP payload consists of a RTP payload header (20 bytes) and the media payload13), and effective data of both picture and nonpicture lines are multiplexed on the media payload. The data volume of the media payload is set at 735 bytes when transmitting EAV-SAV. Furthermore, a MAC header indicating addresses and class information is added to MAC client data. A FSC (Frame Check Sequence) for detecting errors in the MAC header and MAC client data is also added. A MAC frame is composed of a MAC header, MAC client data, and FCS. Finally, an Ethernet packet is completed by adding preamble for signal synchronization and a SFD (Start Frame Delimiter) that indicates the start

of a MAC frame. Meanwhile, as effective pixels and VANC cannot be held

in one MAC frame, they are divided into multiple MAC frames and transmitted. The amount of data in the media payload is set at 1,440 bytes. Components other than the media payload, as shown in Figure 2, occupy 90 bytes, so the length of an Ethernet packet is estimated to be 825 bytes when transmitting EAV-SAV and 1,530 bytes when trans-mitting effective pixels and VANC. The number of Ether-net packets generated from one picture or nonpicture line stands at one from each EAV-SAV, 24 from effective pixels, and 4 from VANC. The transmission band after the Ether-net-packet multiplexing is indicated in Table 1.

3.3 10GE multiplexers and demultiplexersFigures 3 and 4 show the processes of the 10GE multi-

plexer and demultiplexer, respectively. At each 10GE mul-tiplexer on the transmission side, four 3G-SDI signals (2.97 Gbps x 4) are entered into the phase-difference adjustment buffer, from where four latency-adjusted signals are deliv-ered. Considering the signals’ fluctuations, the buffer capac-ity is determined to accommodate 2.1-line’s worth of data. For signal latencies to be adjusted before being delivered, their differences should not be more than one line. In other words, one-line latency is always added to the signals deliv-ered from the phase-difference adjustment buffer.

At the effective-data extraction section, in order to ac-commodate four 3G-SDI signals in a 10GE packet, redun-dant parts in picture and nonpicture lines are eliminated and effective data are extracted. Then the effective data on each

Figure 2: Structure of Ethernet packet

MAC client data

Prea

mbl

e

SFD

MA

C h

eade

r

VLA

N t

ag

IP h

eade

r

UD

P he

ader

RTP

head

er

RTP

payl

oad

head

er

Med

ia p

aylo

ad

FCS

7 1 14 204 8 12 20 735 or 1,440 4 （bytes）

MAC frame

Ethernet packet

Table 1: Transmission band for 10GE/100GE signals

Number of Ethernet packets per line

Number of lines per video frame

10GE signals（Gbps）

100GE signals（Gbps）

Picture lineEAV-SAV

Effective pixels

EAV-SAV

VANC

Total

Nonpicture line

ITU-T standardization

1

24

1

4

1,080

45

1,125

9.47

0.39

9.86

75.8

3.1

78.9

*8 An ensemble of variable-length data inside an Ethernet signal*9 Data structure for using VLAN (Virtual Local Area Network)

technology for building a virtual network*10 Information about segment numbers of virtual networks

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line are accumulated in the picture line buffer (13.7-line ca-pacity) or nonpicture line buffer (13.7-line capacity). Next, at the Ethernet converter, the Ethernet packet described in the previous section is generated, and then a 10GE signal is delivered after the light-to-electricity conversion process. To the UDP header inside a 10GE signal, different UDP port numbers are assigned according to four lines of 3G-SDI sig-nals. On the RTP header, the types of signals (picture line or non-picture line) that are included in the RTP payload inside a 10GE output signal are described.

Meanwhile, at the 10GE demultiplexer on the receiving side, received 10GE signals are processed by light-to-elec-tricity conversion and MAC client data are separated at the Ethernet reconversion section. Furthermore, on the basis of the UDP port numbers described in the UDP header, 3G-SDI signals stored in a 10GE signal are separated so that each of them will be delivered from the same lineage as in the transmission device. Also, on the basis of the signal-type information on the RTP header, these signals are sepa-rated to the picture-line buffer (13.7-line capacity) and the nonpicture-line buffer (13.7-line capacity). At the noneffec-tive data recovery and error detection section, the redundant parts eliminated in the transmission process are recovered to reconstruct the video signals. By checking whether there is an error in the recovered video signals by using the re-ceived CRCC, it can be determined if video signals are suc-cessfully received10). At the phase-difference adjustment buffer (2.1-line capacity), the phase differences among sig-nals are adjusted as they are in the transmission device, and four latency-adjusted 3G-SDI signals are delivered. At the clock recovery section, adequate video signal clocks are de-

livered by controlling the VCXO (Voltage Controlled Xtal Oscillator) stored in this section, using a video-clock con-trol method, which will be explained in the next section. 3G-SDI signals are recovered using these clocks.　

4. Method of controlling recovered video clocksRegarding a video signal delivered from the picture-line

buffer on the receiving side, when its video-frame number stands at f and its picture-line number at l, the reception-buffer accumulation*11 expressed by buff (l) is formulated as the following equation.

= − − −buf ltt

V l V B( ) (1 )( ( 1)% )fSr

EWline line S ........ (1)

In this equation, tEW indicates the Ethernet signal write time per picture line at the reception buffer. It is calculated from the Ethernet signal clock that is actually used in the system, and includes variations such as jitter and frequency deviation. In the same manner, tSr represents readout time per picture line of video clocks recovered on the receiving side. It can vary in accordance with cyclic controls of the VCXO that generates the video clocks. As noted before, Vline indicates the number of successive picture lines (=540) and BS represents the increment in buffer data amount per picture line (=282 kbit). % shows the modulo calculation. Equation (1) shows that the amount of accumulated data in the reception buffer decreases as the picture line number increases and that it reaches a minimum value when the

2.97

Gbp

s ×４

10GE signal3G

-SD

I rec

eptio

n

Phas

e di

ffere

nce

adju

stm

ent

buffe

r

Effe

ctiv

e da

ta

extr

actio

n se

ctio

n

Pict

ure-

line

buffe

r

Ethe

rnet

con

vert

er

Ligh

t-to

-ele

ctric

ity c

onve

rsio

n

Non

pict

ure-

line

buf

fer

Figure 3: Process chart of the 10GE multiplexer

*11 The amount of data accumulated in the picture-line buffer indicated in Figure 4

Figure 4: Process chart of the 10GE demultiplexer

2.97

Gbp

s ×４

10GE signal

VCXO

Ligh

t-to

-ele

ctric

ity

conv

ersi

on

Ethe

rnet

re

conv

ersi

on

sect

ion

Pict

ure-

line

buffe

r

Non

pict

ure-

line

buffe

r

Non

effe

ctiv

e da

ta

reco

very

and

err

or

dete

ctio

n se

ctio

n

Phas

e di

ffere

nce

adju

stm

ent

buffe

r

3G-S

DI t

rans

mis

sion

Clock recovery section

Recovered video clock

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picture line number stands at 540 and 1,080. Next, using the VCXO’s control cycle expressed by CNTperiod (CNTperiod = tn-tn-1 if the n-th control time after the start of control is defined as tn), clock frequency f(tn), which is controlled in accordance with the VCXO’s input voltage, can be deter-mined under the following condition.

Here, Fadj represents the frequency change that varies de-pending on each control cycle. It is defined as a fixed value. Clock frequencies are controlled toward lower values under condition A and toward higher values under condition B. In the commonly used adaptive clock method, conditions A and B are described as follows if the target value of the reception buffer accumulation is defined as tgt(l).

> +tgt l buf l W( ) ( )f

< −tgt l buf l W( ) ( )f

Condition A:Condition B:

........ (3)

........ (4)

W indicates a predetermined constant value. By keeping clock frequencies unchanged when the gap between the ac-tual accumulation and its target value is less than ±W, their fluctuations can be avoided within a short cycle. If con-trolled under these conditions, current accumulation, which is an instantaneous value, varies over time depending on fluctuations in data writing speed on the reception buffer. As a result, recovered clock jitter is generated. Therefore, in this system, conditions A and B are defined as follows:

Condition A:

Condition B: { } { }< − > −tgt l buf l W buf l buf l( ) ( ) & ( ) ( )f f f 1

{ } { }> + < −tgt l buf l W buf l buf l( ) ( ) & ( ) ( )f f f 1 ... (5)

... (6)

Compared with conditions (3) and (4) employed in the general adaptive clock method, conditions (5) and (6) con-tain an additional control that includes a relation condition between the reception buffer accumulation buff (l) at pic-ture line number l of video frame number f and the accu-mulation buff-1(l) in a preceding video frame. This measure takes advantages of the fact that in equation (1), the ac-cumulation buff (l) is independent of frame number and re-mains the same for the same line number. With this control method, the reception buffer’s variation trend obtained by comparison between past and present accumulations can be reflected in the clock control, which leads to the reduction of jitter resulting from fluctuations of the control voltage at the VCXO. On the basis of the results from the prior simu-lations, clock control parameters for this system are set at the following values: Fadj=0.1 ppm, CNTperiod=125 lines, and W=700 bits.

5. Experiment with test equipmentIn this section, we will explain the experiment using

test equipment. In Figure 1, the transmission and receiv-

ing devices are directly connected by a one-meter-long sin-gle-mode optical fiber, which bridges 100GBASE-LR4*12 transceivers compliant with CFP MSA (C Form-factor Pluggable Multi-Source Agreement) 14) *13. In addition, on the assumption that uncompressed HD and other signals in the form of 100GE signals are transmitted along with un-compressed 8K signals, two lines of data traffic (combined transmission band: 18.0 Gbps) derived from the 10GE sig-nal generator are added to the uncompressed 8K signals in order to conduct performance evaluation at the 10GE-100GE converter.

First, the time variability of the video clock frequency recovered at the receiving device is indicated in Figure 5. The convergence time after the start of control is about two seconds. The frequency deviation of the recovered video signal clock remains at ±0.34 ppm after 45 s from the start of control.

Next, TJ (Timing Jitter) and AJ (Alignment Jitter) in the test equipment are measured. The 8K-signal indicator (vid-eo monitor) connected to the receiving device conducts par-allel processing, converting 3G-SDI signals to High Defini-tion-Serial Digital Interface (HD-SDI) signals. In order to check whether appropriate image reproduction is achieved, the 3G-SDI signals should be evaluated as HD-SDI signals. Therefore, TJ and AJ are measured after 3G-SDI signals delivered from the reception device are converted to HD-SDI signals. Figures 6 and 7 show the characteristics of TJ and AJ, respectively. They also indicate TJ and AJ char-acteristics at the transmission signal source. The results show that both TJ and AJ are significantly lower than the standard values11) (TJ: 1.0 UI or less; AJ: 0.2 UI or less), which means both types of jitter have similar characteristics to those at the transmission signal source.

As for the 3G-SDI signals delivered from the receiving device, 24-hour error detection is conducted using CRCC. At the same time, the received 8K images undergo visual examination for one hour. The results show that no CRCC errors are detected and transmitted images are correctly re-ceived.

In addition, the 8K image transmission delay time be-tween the transmission and receiving devices stands at 459 μs.

Finally, bit error rates of the two lines of data traffic pro-duced at the 10GE signal generator, which are transmitted along with uncompressed 8K signals, are measured by the 10GE analyzer set at the 100GE-10GE converter, shown in Figure 1. After a one-hour examination, it is confirmed that data transmission is carried out without any bit errors.

This experiment was conducted after a proper bandwidth was secured for uncompressed 8K signals. In practice, mul-tiple 8K signals and other data are supposed to be trans-

*12 Interface standard for long-distance transmission of 100 GE signals

*13 Standard for product specifications jointly established by makers of light transceiver modules

=

−

−

f t

f t F

( )

( ) when A

when B

otherwise

n

n adj1

+−f t F( )n adj1 ......... (2)

FEATURE

0 20 40 60 80 100-50

0

Starting point of signal transmission

Time elapsed（seconds）

Freq

uenc

y de

viat

ion

(ppm

)

50

100

150

200

250

(Receiving side) Frequency of recovered video clock(Transmitting side) Frequency of video clock

Figure 5: Time variation characteristics of recovered video clocks

mitted on Ethernet, which is used as a common data trans-mission network. In that case, delays and fluctuations of Ethernet packets caused by buffering at the Ethernet switch or their disappearance caused by buffer overflows are like-ly to cause problems. When these problems are taken into account in proposing a method, examinations of the clock control characteristics will be an issue.

6. Summary In this paper, we proposed a method of controlling video

clocks recovered on the receiving side of the transmission system that transmits and receives uncompressed 8K sig-nals over 100GE. In this system, an Ethernet transmission channel is effectively used in order to recover video signals

with low jitter and low latency. A transmission experiment using test equipment shows that the convergence time of clock frequencies stands at about 2 s and the frequency de-viation after the convergence stands at ±0.34 ppm. Both TJ and AJ meet the jitter standards, and stable images with no errors are received with 459μs latency. These results con-firm the effectiveness of the proposed method.

This paper is a revised version of the following paper that appeared in the Journal of The Institute of Electronics, Information and Communication Engineers:

J. Kawamoto, T. Nakatogawa and K. Oyamada. “Clock Recovery and Control Method for 8K Super Hi-Vision Signal Transmission over 100 Gigabit Ethernet,” IEICE trans on Commun JPN Edition (in Japanese), Vol. J98-B, No. 10, pp. 1127-1136, 2015.

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0 20 40 60 80 1000

0.2

0.4

0.6

0.8 Standard value（1.0 UI）

Cumulative occurrence rate (%)

Uni

t in

terv

al（U

I）

1

TJ（recovery）TJ（transmission）

Figure 6: Timing Jitter characteristics

0 20 40 60 80 1000

Standard value（0.2 UI）

Cumulative occurrence rate (%)

Uni

t in

terv

al（U

I）

0.2

0.15

0.1

0.05

AJ（recovery）AJ（transmission）

Figure 7: Alignment Jitter characteristics