development of cold cots adc for sbnd tpc readout · 2018-05-16 · chn1 chn2 chn3 relay ctrl a b0...

H. CHEN ON BEHALF OF SBND COLD ELECTRONICS TEAM

BROOKHAVEN NATIONAL LABORATORY

MAY 16TH, 2018

Development of Cold COTS ADC for SBND TPC Readout

§ Introduction

§ COTS ADC Lifetime Study§ Development of Test Stand§ Exploratory Phase§ Validation Phase§ Lifetime Projection

§ Development of COTS ADC Option§ FEMB with COTS ADC§ Integration Test with 40% APA

§ Summary

Outline

2018/05/16 H. Chen - DUNE Collaboration Meeting 2

§ Front End Electronics System§ 704 FE ASICs/11,264 ADC

channels/88 Cold FPGAs

§ 88 Front End Mother Board assemblies

§ 4 sets of cold cable bundles, 4 sets of signal feed-throughs

§ ~28 boards in WI electronics crate

SBND TPC Electronics


Cold Electronics

Warm Interface Electronics

TPC Readout Electronics

Signal Feed-through

Cold Cable

Back End Electronics

Front End Electronics

NSF

DOE

§ The COTS ADC work benefits the future program, which serves as a backup for DUNE far detector§ COTS ADC lifetime study procedure was developed

in summer 2017§ Cold qualification techniques are useful for future

Dark Matter and Neutrino experiments

§ Lifetime study of COTS ADC took place in two different phases (SBN DocDB #3071)§ Before that, we will need to prepare the test stand to

make it suitable for lifetime study, which is Preparation phase

§ The first phase is Exploratory phase§ The second phase is Validation phase

§ COTS ADC candidates with 100% cold yield identified§ TI ADS7049-Q1: 180nm CMOS TI foundry§ TI ADS7883: 500nm CMOS TI foundry§ ADI AD7274: 350nm CMOS TSMC foundry

§ AD7274 is the main focus of lifetime study§ Preparation phase completed in September 2017§ uA scale current monitoring and 0.25 LSB scale DNL

measurement achieved

SBND COTS ADC Option

2018/05/16 4H. Chen - DUNE Collaboration Meeting

§ The test stand shown in previous slide has been used in exploratory phase to study COTS ADC lifetime from September to December 2017§ It took some effort to develop and

optimize the test stand for COTS ADC lifetime study

§ A new COTS ADC test board has been designed for ADC lifetime study in validation phase§ Analog switch: NLASB3157 (used on FM)§ Clock fan-out: CDCV304 (used on AM)§ Add series termination resistors for ADC

SPI signals § Support stress voltages up to 6V with

level translator qualified for cold operation

§ Fully automatic data taking with only manual intervention of LN2 filling

§ New COTS ADC test boards are used to study ADC lifetime in validation phase at both BNL and Manchester

Development of Test Stand


Generator

FPGAFPGA

Relay Drive Circuit

A

B0 B1

RELAY

A

B0 B1

RELAY

Vref VCC

COTSADC

SMU

ADM7151Regulator(1.8V)

ADM7151Regulator(2.5V)

CHN1 CHN2 CHN3

RelayCtrlA

B0 B1

RELAY

SDO

VccB0

B1A

CSAnalogSwitch

StressVoltageforVcc

6.0V

StressVoltageforVref

Power distribution with relay circuit

New COTS ADC test board with FM

LN2 Re-filling

01/08/18 16:10Power supply crashed

and shut down for 21 hours

Slightly drop (<0.5%)

§ Exploratory Phase with old COTS ADC test board

§ Current variation of VCC and VREF (5.25V) < 10% § Current drop caused by LN2 filling has been understood§ Note: the time on x-axis is the operation time of COTS ADC at LN2, which is longer than

the stress time

§ Sigma of DNL compared to the initial value§ Sigma of DNL is increased by ~70% for 2Msps§ DNL is still within +/- 0.5 LSB

AD7274#002 Stressed at 5.25V for 768 Hours


Time of duration in LN2

§ Validation Phase with new COTS ADC test board

§ Current of VCC decreases ~1.1%

§ Variation of DNL is smaller than 0.15 LSB§ Full scale input ramp waveform applied§ Every bit has 50% with logic high and 50% with logic low§ A more comprehensive COTS ADC stress test program



102%

98%


Power supply for FM crashed for 6 hoursADC was still under stressed with 5.5V but without conversion operation

§ Validation Phase with new COTS ADC test board

§ Current of VCC decreases ~1.5%

§ Variation of DNL is smaller than 0.15 LSB§ Full scale input ramp waveform is applied§ Every bit has 50% with logic high and 50% with logic low§ A more comprehensive COTS ADC stress test program



102%

98%


Preliminary Summary


ADC Sample ADCteststand Inputwaveformduringstress

StressVoltage

HoursUnderStress/h

CurrentVariationofVCC SigmaofDNL(2MSPS)

AD7274 001 Old(withanalogswitch)#1 DC,0.9V 5.5V 722 / é~90%(<0.15LSB)

AD7274 002 Old(withanalogswitch)#2 DC,0.9V 5.25V 768 / é~70%(<0.15LSB)

AD7274 003 Old(withanalogswitch)#3 DC,0.9V VCC=2.5V

Vref=1.8V 870 / <3%(<0.15LSB)

AD7274 005 Old(withanalogswitch)#2

Ramp,0.1V-1.1V,1Hz 5.25V 718 ê~1.00% ~30%(<0.15LSB)

AD7274 007 Old(withanalogswitch)#1

Ramp,0.1V-1.1V,1Hz 5.5V 535 ê~1.50% ~30%(<0.15LSB)

AD7274 012 New(withleveltranslator)#2 Ramp,0-5.5V,1Hz 5.5V 517 ê~1.10% ~30%(<0.15LSB)

AD7274 016 New(withleveltranslator)#1 Ramp,0-6.0V,1Hz 6.0V 205 ê~1.40% ~40%(<0.15LSB)

AD7274 017 New(withleveltranslator)#2

Ramp,0-5.75V,1Hz 5.75V 100 ê~0.90% ~50%(<0.1LSB)

§ Current of VCC decreases during the stress test as expected§ #001 & #002 have current drop issue caused by VREF and DC input, which is

understood§ Variation of IVCC will be used to assess the lifetime of COTS ADC§ ADC lifetime projection will be extrapolated from the slope of lifetime vs 1/Vds

§ Sigma of DNL indicates the ADC performance is stable during the stress test

§ Stress test data of 6 ADC chips§ #009 (Manchester) and #012 (BNL) overlap quite well

ADC Lifetime Study During Validation Phase


005 (5.25V) : Old ADC test stand

009 (5.5V) : Manchester

Estimate to ~800 hours

016 (6.0V) : New ADC test stand

012 (5.5V) : BNL

ADC Lifetime Projection


(005) 5.25V, 800 hours is estimated

IVCC drops 1% as degradation criteria

§ COTS ADC lifetime study has been documented in a tech note (SBN DocDB #5334) and reviewed by SBND tech board§ 3.6V CMOS 350 nm CMOS, to be operated

at 2.5V, where HCE should be negligible, verified by stressing to 5.5V

§ Decision was made on March 14th to proceed with COTS ADC

§ It is planned to continue the COTS ADC lifetime study at BNL and Manchester, with aim to publish this study in summer

§ Final design of SBN TPC readout electronics system is progressing well§ Recommendation from November

Director’s Review: design and test 128 channel FEMB with COTS ADC

§ FEMB with COTS ADC has been tested with Toy TPC and 40% APA successfully

§ ENC ~ 500 e- @ 1us tp and 150pF CD

§ Plan for integration test with Nevis next week, then move to Fermilab for VST with LArIAT in early June

FEMB with COTS ADC


FEMB with COTS ADCENC with 150pF Toy TPC in LN2

§ 8 SBND COTS AMs passed cold screening test§ LArIAT wire mapping is applied

to prepare for VST at Fermilab§ 1024 (128*8) ADC chips passed

cold test, no failure, 100% yield§ There were additional > 100 chips

verified by ADC test board last year (100% yield)

§ 40% APA integration test has been carried out at BNL§ 4 SBND FEMBs with COTS ADC

are installed on the 40% APA§ Test with cold box tilted and also

with 40% APA fully submerged in LN2

Integration Test with 40% (DUNE)APA


At RTFEMB submerged in LN2

X wire (2.8m) capacitance: ~50pFU wire (4.0m) capacitance: ~70pFV wire (4.0m) capacitance: ~70pF

40% APA in Tilted Cold Box


Feed-through + WIEC

§ Induction Planes: ENC ~ 380 e- @ tp = 1us

§ Collection Plane: ENC ~ 300 e- @ tp = 1us

Cold Box Tilted – FEMBs + part of 40% APA in LN2


40% APA Fully Submerged in LN2


Cold box with 40% APA

Feed-through + WIEC

§ Induction Planes: ENC ~ 400 e- @ tp = 1us

§ Collection Plane: ENC ~ 330 e- @ tp = 1us

40% APA Fully Submerged in LN2


ENC during the 40% APA Integration Test

2018/05/16 18

FEMBs + 40% APA fully submerged in LN2

FEMBs above LN2X wires above LN2

U/V wires partly in LN2

All above LN2Warm up

Warm up: FEMBs get wet if there is no LN2 remains in cold boxH. Chen - DUNE Collaboration Meeting

§ 4 FEMBs and 40% APA fully submerged in LN2§ FEMB (fully submerged in LN2) with inputs floating: 180 +/- 10 e-

§ Gain = 25 mV/fC; Tp = 1 us§ Dielectric constant: GN2 = 1.00 , LN2 = 1.43§ The noise ratio matches the dielectric constant of LN2

quite well

Cross Check Dielectric Constant of LN2

2018/05/16 19

Raw data(25mV/fC,Tp =1.0us)

Pre-filteringMeasured(total)\ e-

InputFloating(noinput)\ e-

Noisecontributedbywirecapacitance\ e- Noise(LN2)/Noise(Gas)

XwiressubmergedinLN2 328 180 274 1.43XwiresaboveLN2 263 180 192

VwiressubmergedinLN2 395 180 352 1.44VwiresaboveLN2 304 180 245

UwiressubmergedinLN2 412 180 371 1.45UwiresaboveLN2 312 180 255

H. Chen - DUNE Collaboration Meeting

§ SBND collaboration has been studying the COTS ADC option§ Development of test stand enables the COTS ADC lifetime study§ Preparation, exploratory and validation phases have been carried out for

COTS ADC lifetime study§ Preliminary lifetime projection of COTS ADC is ~5.8 x 106 years§ This means the HCE (hot carrier effect) will be negligible for COTS ADC used

in SBND (and DUNE), and we’ll be stay out of HCE during the detector operation

§ COTS lifetime study continues, with aim to publish this study

§ SBND collaboration has made decision to use COTS ADC§ Prototype FEMB with COTS ADC has been developed and tested with 150pF

Toy TPC, shows good noise performance§ Integration test with 40% APA has been performed at BNL, with

demonstration of satisfactory ENC performance§ Integration test at Nevis and VST at Fermilab will take place in coming month

§ SBND FEMB with COTS ADC is compatible with ProtoDUNE FEMB design§ It will be available for the system integration tests at Fermilab and CERN

Summary


Backup Slides

§ A study of hot-electron effects on the device lifetime has been performed for the TSMC NMOS 180nm technology node at 300K and 77K. Two different measurements were used: accelerated lifetime measurement under severe electric field stress by the drain-source voltage (Vds), and a separate measurement of the substrate current (Isub) as a function of 1/Vds. The former verifies the canonical very steep slope of the inverse relation between the lifetime and the substrate current, , and the latter confirms that below a certain value of Vds a lifetime margin of several orders of magnitude can be achieved for the cold electronics TPC readout. The low power ASIC design for MicroBooNE and DUNE falls naturally into this domain, where hot-electron effects are negligible.

§ The slope of lifetime vs 1/Vds is independent of the technology node (from 180, 130 to 65 nm) and of the foundry (TSMC, Global ...). For all three nodes the lifetime is extended by an order of magnitude if Vdd(Vds) is reduced by ~6%. This may be related also to the two basic underlying parameters, electron energy for impact ionization and forcreation of an interface state, as well as their ratio.

CMOS Lifetime Study – Principle Findings


-3subτ Iµ

q = electron chargeλ = electron mean free pathEm = electric field

Ids= drain-source currentW= channel width

C1, C2 - constants

§ In deep submicron NMOS (L<0.25µm) electrons can become “hot” at any temperature, by attaining energy E > kT.

§ Some hot electrons exceed the energy required to create an electron-hole pair, resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current,

(1)

§ A very small fraction of hot electrons exceeds the energy required to create an interface state (e.g., an acceptor-like trap), in the Si-SiO2 interface,

for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic gain).

§ The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by ~10%) is defined as the device lifetime. It can be calculated as,

(2)

23

1.3i eVj @

3.7it eVj ³

1i mq E

sub dsI C I e j l-=

2it mq E

ds

WC eI

j lt =

2018/05/16 H. Chen - DUNE Collaboration Meeting

Basics on Hot-electron effects (HEC) and NMOS lifetime

§ Lifetime depends on the drain current density and the product of λEm

§ Devices at cryogenic temperature have shorter lifetime because the phonon scattering decreases at low temperature, resulting in a longer mean free path thus a higher λEm, which means a higher amount of hot carriers, which leads to more severe HCE and shorter lifetime

§ Devices with shorter length have shorter lifetime because the shorter length devices have higher maximum electric field under the same operating condition, thus a higher λEm, which means a higher proportion of hot carriers, which leads to a more severe hot carrier effect and shorter lifetime. We use the minimal length device to represent the lifetime of the technology.


Measurement condition Vds = 1V

2it mq E

ds

WC eI

j lt =

77K

300K

180nm

270nm

Different T: Lower T, higher λ, lower τ Different L: Shorter L, higher Em, lower τ

Lifetime vs substrate current (normalized to channel width and current): Slope test for TSMC L=180 and L=270 nm

H. Chen - DUNE Collaboration Meeting

3it ia j j= »

The slope is largely independent of the channel length and temperature.

For constant Isub/Ids, the lifetime increases with channel length.

Each stress point is a new (“fresh”) device sample (two different L devices, 13 samples in this plot).

2018/05/16 25

§ It has been long established (1994) that ac and dc hot-carrier induced degradation is the same if the effective stress time is taken into account. This quasi-static model, confirmed recently (2006) considers the ac stress as a series of short dc stresses strung together

§ The lifetime of a logic circuit driven at a clock frequency can be related to the lifetime of the NMOS transistor under continuous ac operation in terms of the ratio of the effective stress time during a change of state and the clock period. Thus the Lifetime of digital circuits (ac operation) is extended by the inverse duty factor compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequencies needed for TPC readout.

§ Design guidelines for digital circuits and FPGAs: Keep the inverse duty factor high. As an additional conservative measure, reduce Vds by 10%, adding an order of magnitude margin to the lifetime.

CMOS in AC operation: Logic circuits and FPGAs

26

( )clock rise4 f t


Effective Stress Time is a small fraction of the Clock Cycle:

Hot-carrier induced degradation occurs only when the substrate current is high, i.e., nominal Vds and high Ids.

( )4

clock risestress time f tstress ti e

acdc mé ù

»ê úë û

Lifetime of digital circuits (ac operation) is extended by the inverse duty factor compared to dc operation. This factor is large (>100) for COTS ADC with fclock > 32 MHz and trise < 500 ps.


Accelerated Lifetime Measurement of 3.3 V node: very steep dependence on Vds


2.9 V

~100

SBND Front End Electronics Prototypes


To APA wires

LVpower

SBND coldCable to flange SFP socket

and JTAG

Cable strain relief bars

Compression Plate

Flange PCB

8x SHV ConnectorsIndium seal

Power & Timing Backplane (PTB)

Power & Timing Card (PTC)

Warm InterfaceBoards (WIB)

14” CF flange

Purging Port

Warm Interface Electronics Crate (WIEC)

Flange BoardFEMB WIB

Signal Feed-through + WIE Assembly

MBB

PTBCold Cable

§ Note: Normal operation voltages§ VCC = 2.5V, VREF = 1.8V

§ Similar test stand as AD7274#001 & #002, except§ No SMU for continuous current monitoring§ No relay circuit board for power distribution

§ AD7274#002 & AD7274#003 share the same dewar

AD7274#003 Cold TestCompleted after 870 hours


§ Sigma of DNL compared to the initial value§ Started on 12/28/2017, has been tested for ~870 hours with Normal

operation voltages (VCC=2.5V, VREF=1.8V) at LN2 § Sigma of DNL has very small (< 3%) for 2Msps§ This confirms the observation of DNL change was caused by stress

test for sample #001 & #002

Exploratory Phase

2018/05/16 31H. Chen - DUNE Collaboration Meeting

Vcc=2.5V

LN2 Re-filling

01/08/18 16:10Power supply crashed

and shut down for 21 hours

no wire Y

U

V

U+82pF

V+82pFY+150pF

U+150pF

V+150pF

Y+82pF

××

ProtoDUNE-SPCollection Plane ~500 e-

ProtoDUNE-SPInduction Plane ~600e-

OO

SBNDInduction Plane ~500e-

SBNDCollection Plane ~400e-

ENC Projection for SBND/ProtoDUNE-SP

32

§ SBND APA§ U/V wire (max): 5.77m§ Y: 4.0m

§ ProtoDUNE APA§ U/V wire: 7.39m§ Y wire: 6.0m

§ 40% APA§ U/V wire: 4.0 m§ Y wire: 2.8m

§ DUNE Far Detector§ Threshold: 1,100 e-

§ Goal: 700 e-


development of cold cots adc for sbnd tpc readout · 2018-05-16 · chn1 chn2 chn3 relay ctrl a b0...

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