RESEARCH POSTER PRESENTATION DESIGN © 2012

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Two designs of CMOS pixel sensor with in-pixel analog-to-digital conversion have been

prototyped in a 0.18µm CIS process. The first design integrates a discriminator into each pixel within an area of 22×33µm²

in order to meet the requirements of the ALICE-ITS upgrade. The second design features 3-bit charge encoding inside a 35×35µm²

pixel which is motivated by the

specification of the outer layers of the ILD vertex detector. This work aims to validate the concept of in-pixel digitization which offers higher readout speed, lower power consumption and less

peripheral surface of active area compared to column-level charge encoding.

ABSTRACT

INTRODUCTION

[1] S. Senyukov

et al., Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm

process with a high resistivity epitaxial layer (arXiv:1301.0515) [2] J. Baudot

et al, First Test Results Of MIMOSA-26, A Fast CMOS Sensor With Integrated Zero Suppression and Digitized Output, 2009 IEEE Nuclear Science Symposium Conference Record[3] L.Zhang

et al., Power and area efficient 4-bit column-level ADC in a CMOS pixel sensor for the ILD vertex detector, Topical Workshop on Electronics for Particle Physics 2012

CMOS pixel sensors fabricated in the 0.18μm CIS technology can provide satisfactory sensing performance and at the same time have greater radiation hardness

compared with the 0.35μm OPTO technology[1]. Moreover, the N-well embedded in deep P-well allows implementing PMOS transistors inside a pixel without deteriorating the charge collection. Together with smaller feature size and more metal layers, this technology offers the opportunity to develop smarter pixels with more integrated features.

In this work, we describe two prototype chips based on the

0.18μm technology featuring in-pixel analog-to-digital conversion. With in-pixel digitization, the output analog buffer driving the column line is no longer needed. Thus, the power consumption can be reduced considerably and also the readout speed can be increased.

Institut

Pluridisciplinaire

Hubert Curien

Development of CMOS Pixel Sensor with digital pixels dedicated 

to future particle physics experiments

Chip design

discriminator

Self –biased with feedback loop

Validated performance in previous chips

C-V gain: ~66µV/e-

Noise floor: ~

18-22 e-

CONCLUSION

REFERENCE

Sensing and pre-amplification

Six matrices of pixel including two separate

matrices for latch calibration purpose are

implemented and can be selected individually.

Array readout in rolling shutter mode at a

nominal speed of 100ns/shutter

Both single row readout (matrix of 32×36) and double row readout (matrix of 16×18) are

realized

Four columns (two columns for double row readout scheme) with pre-amplifier analog

outputs for sensing calibration purpose

(a)

Single row readout               (b) double row readout

Figure 4 Pixel layout ( four pixel as a group, the red arrow indicates 

the control line routing )

Tianyang

Wang, Wei ZHAO, Pham Thanh

Hung, Andrei Dorokhov, 

Christine Hu‐Guo, Yann Hu

Two amplifying stages + dynamic latch

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

Sensing

Pre‐amp+

1.

Binary charge encoding => AROM0The first prototype chip, called AROM0, is developed with the purpose of validating the concept of in-pixel discrimination. The pixel developed in AROM0 has a pitch of 22×33µm2

mainly driven by the specification of ALICE-ITS upgrade and it is composed of two parts. The first part consists of the sensing diode and the preamplifier. The second part is a high precision discriminator with CDS.

Figure 1 Sensing diode and preamplifier

Figure 2 Schematic

2.

3-bit charge encoding => MIMADCMIMADC, as a prototype chip, is designed to evaluate the feasibility to integrate a pixel-level ADC within the 35 µm pixel for the ILD vertex detector. The in-pixel functionalities include a particle sensing diode with pre-amplification, a sample-hold amplifier, and a 3-bit Successive Approximation Register (SAR) ADC.

Figure 3 Timing diagram

Layout design

Preliminary test results

⇛ Avoiding the presence of circuitry alongside the matrix

No dead area in between when multiple chips are aligned side by side through chip stitching to form a

larger sensor

Elongated pixel with staggered diodes

Sequencer placed at the bottom of the matrix

The double row readout scheme employs the schematic of version 2

Chip description

Figure 5 Chip layout

Measured “S”

curves for Version 1 is shown in figure 6

Discriminator input noise ~ 1mV

Similar noise performance for different versions

The latch contributes negligible noise: ~3mV

Main noise sources located in the discriminators

Figure 6 “S”

curves for Version 1

⇛ Version 1: KT/C noise from “vclp”

and “vth”

switches

⇛ Version 2: Amplifiers noise

Sensor Architecture

A 16x16 pixel array with 3-bit pixel-level SAR ADCs

Within a pixel of 35 x 35 μm2, a sensing

diode, a pre-amplifier, and a SAR ADC

(except SAR logic) are implemented

Column-level SAR logics are implemented at the bottom of the matrix

One column pixels share one column-level

SAR logic

A parallel to serial converter is used to serialize the digitalized results from ADCs

Pixel Circuits

The self-biased diode with the pre-amplifier senses impinging charged particles ( the same schematic as that used in AROM0 )

The closed-loop amplifier samples the signal from the sensing diode. The gain setting by the ratio of two capacitors C1

and C2

, is ~4.

The comparator consists of two amplifier stages followed by a high speed dynamic latch. OOS (Output Offset

Suppression) scheme in the comparator removes the offset and low

frequency noise of the amplifiers.

The DAC generates the reference signal according to the output control signals from the SAR logic, for comparing with particle signal. In common, the DAC is composed of a capacitor array. In pixel-level SAR ADC, the DAC is implemented with a multiplexer to select one of the seven references for its merit of less chip area.

Column Circuits

The SAR logic reads the result from the comparator and feeds back the signals to control the actions of the DAC in a pixel. The SAR logics are at the end of a column pixels and shared by them.

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Matrix is readout in row by row following rolling shutter scheme

LSB (Least Significant Bit) of ADCs is ~1 mV (correspond to

the pixel pre-amplification output noise). The digitalized results are serialized, and then transmitted by LVDS drivers,

For a SAR ADC structure with 3-

bit resolution, 3 comparisons are needed for one conversion

The conversion time is about 160 ns with a clock cycle of 10 ns

The dead time is ~110 ns

By utilizing the 0,18µm CIS technology, two designs with pixel level digitization have

been fabricated. These designs are anticipated to elevate the potential of CMOS pixel sensors in respects of power consumption, speed and ratio of active surface compared with column level digitization ( refer to [2],[3] for column level digitization)

Figure 7. Architecture of Sensor

Figure 8. Schematics of Pixel and Column Block

Figure 9. Timing diagram Figure 10. Chip Layout

Three different versions to study how the circuit

implementation will influence the performance.

Same timing is used for the three versions

Threshold voltage = vth

-

vclp

⇛ Amplifying gain: 25 ~ 30

⇛ Latch offset: < 5mV

AROM0: ALICE-ITS upgrade

Binary charge encoding

Speed: 100ns/shutter

Power dissipation: 45~90µW/pixel (can be further reduced to

20µW/pixel in AROM1 )

Discriminator noise: ~1mV (expected to be lowered by 2-3x in AROM1)

Measurement results validate the full functionality of in-pixel

discriminator architecture.

Next prototype: AROM1 (two submissions in Aug & Oct 2013)=> larger array (64×64) with reduction of noise and power consumption pixel

MIMADC: Outer layers of the ILD vertex detector

3-bit charge encoding:

Speed: 160ns/shutter

Power dissipation: 140µW/pixel

Simulated ADC noise < 1mV

The test is planning for Oct 2013