1 | P a g e DevBhoomi Institute of Technology DEPARTMENT OFELECTRONICS & COMMUNICATION ENGINEERING HANDBOOK Course : B.TECH Semester : 6th Mentor Name:LalitTyagi

2 | P a g e TEC-603TELECOMMUNICATION SWITCHING SYSTEMS UNIT 1INTRODUCTION: Message switching, circuits switching, functions of a switching system, register-translator-senders, distribution frames, crossbar switch, a general trunking. Transmission Systems, FDM Multiplexing and modulation, Time Division Multiplexing, Digital Transmission and Multiplexing: Pulse Transmission, Line Coding, Binary N-Zero Substitution, Digital Bi-phase, Differential Encoding, Time Division Multiplexing (T1 carrier system CCIT and DS lines) Time Division Multiplex Loops and Rings. UNIT 2DIGITAL SWITCHING: Switching functions, space division switching, multiple stage switching, non-blocking switches, blocking Probabilities DCS hierarchy, integrated cross connect equipment, digital switching in environment, zero loss switching. UNIT 3TELECOM TRAFFIC ENGINEERING: Network traffic load and parameters, grade of service andblocking probability, Traffic Characterization: Arrival Distributions, Holding Time Distributions, Loss Systems, Network Blocking Probabilities: End-to-End Blocking Probabilities, Overflow Traffic, Delay Systems: Exponential service Times, Constant Service Times, Finite Queues. UNIT 4NETWORK SYNCHRONIZATION CONTROL AND MANAGEMENT: Timing Recovery, Phase-LockedLoop, Clock Instability, Jitter Measurements, Systematic Jitter. Timing Inaccuracies: Slips, Asynchronous Multiplexing, Network Synchronization, U.S. Network Synchronization, Network Control, Network Management. UNIT 5DIGITAL SUBSCRIBER ACCESS: ISDN Basic Rate Access Architecture, ISDN U Interface, ISDN DChannel Protocol. HD-Rate Digital Subscriber Loops: Asymmetric Digital Subscriber Line, VDSL. Digital Loop Carrier Systems: Universal Digital Loop Carrier Systems, Integrated Digital Loop Carrier Systems, Next-Generation Digital Loop Carrier, Fiber in the Loop, Hybrid Fiber Coax Systems, Voice band Modems: PCM Modems, Local Microwave Distribution Service, Digital Satellite Services. DSL Technology: ADSL, Cable Modem, Traditional Cable Networks, HFC Networks, Sharing, CM & CMTS and DOCSIS. SONET: Devices, Frame, Frame Transmission, Synchronous Transport Signals, STS I, Virtual Tributaries and Higher rate of service.

3 | P a g e SEMESTER/YEAR: 6th/3rdDEPARTMENT: ECE COURSE:TELECOMMUNICATION SWITCHING SYSTEM S. No. Topic Name 1. INTRODUCTION 2. Message switching, circuits switching3. functions of a switching system4. register translator-senders 5. distribution frames 6. crossbar switch, a general trunking7. Transmission Systems 8. FDM Multiplexing and modulation9. Time Division Multiplexing 10. Digital Transmission and Multiplexing11. Pulse Transmission, Line Coding,12 Binary N-Zero Substitution Digital Biphase, Differential Encoding 13. Time Division Multiplexing (T1 carrier system CCIT and DS lines) 14. Time Division Multiplex Loops and DBIT DEHRADUN LESSON PLAN DEPARTMENT: ECE TELECOMMUNICATION SWITCHING SYSTEM Reference/ Text Book/ Web (R/T/W) No. Of Lectures T4 1 Message switching, circuits switching T4 1 functions of a switching system T4 1 T4 2 T4 2 crossbar switch, a general trunking T4 2 T4 1 FDM Multiplexing and modulation T4/R1 1 T4/R1 1 Digital Transmission and Multiplexing T4/R1 1 Pulse Transmission, Line Coding, T3/R1 1 Zero Substitution Digital Bi- T3/R1 2 Time Division Multiplexing (T1 carrier T3/R1 1 Time Division Multiplex Loops and T3/R1 1 TELECOMMUNICATION SWITCHING SYSTEM CODE: TEC-603 Delivery Method Remarks Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk

4 | P a g e Rings 15. DIGITAL SWITCHING: Switching functions T2 1 Chalk & Talk 16. space division switching T2 1 Chalk & Talk 17. multiple stage switching T2 1 Chalk & Talk 18. Nonblocking switches, blocking Probabilities T2 2 Chalk & Talk 19. DCS hierarchy, integrated cross connect equipment T2 1 Chalk & Talk 20. digital switching in environment T2 1 Chalk & Talk 21. zero loss switching T2 1 Chalk & Talk 22. Network traffic load T1 1 Chalk & Talk 23. Network traffic parameters T1 1 Chalk & Talk 24. grade of service and blocking probability T1 1 Chalk & Talk 25. Traffic Characterization: Arrival Distributions, Holding Time Distributions T1 1 Chalk & Talk 26. Loss Systems T1 2 Chalk & Talk 27. Network Blocking Probabilities: End-to-End Blocking Probabilities T1 2 Chalk & Talk 28. Overflow Traffic,Delay Systems T1 1 Chalk & Talk 29. Exponential service Times T1 1 Chalk & Talk 30. Constant Service Times, Finite Queues T1 2 Chalk & Talk 31. NETWORK SYNCHRONIZATION T2 1 Chalk & Talk

5 | P a g e CONTROL AND MANAGEMENT 32. Timing Recovery T2 1 Chalk & Talk 33. Phase-Locked Loop T2 1 Chalk & Talk 34. Clock Instability, Jitter Measurements T2 1 Chalk & Talk 35. Systematic Jitter T2 1 Chalk & Talk 36. Timing Inaccuracies: Slips T2 1 Chalk & Talk 37. Asynchronous Multiplexing T2 1 Chalk & Talk 38. Network Synchronization T2 1 Chalk & Talk 39. U.S. Network Synchronization T2 1 Chalk & Talk 40. Network Control, Network Management. T2 1 Chalk & Talk 41. ISDN Basic Rate Access Architecture T1/T3 3 Chalk & Talk 42. Digital Loop Carrier Systems T1/T3 1 Chalk & Talk 43. Fiber in the Loop, Hybrid Fiber Coax T1/T3 1 Chalk & Talk 44. Voice band Modems: PCM Modems T1/T3 1 Chalk & Talk 45. Satellite Services T1/T3 1 Chalk & Talk 46. DSL Technology: ADSL, Cable Modem T1/T3 1 Chalk & Talk 47. SONET T1/T3 3 Chalk & Talk Total Lectures: 56 TEXT BOOKS: [T1] Tele communication switching system and networks - ThyagarajanViswanath, PHI, 2000. [T2] Digital telephony - J. Bellamy, John Wiley, 2nd edition, 2001. [T3] Data Communications & Networks - Achyut. S.Godbole, TMH, 2004. [T4]Telecommunication switching, Traffic and Networks - J E Flood, Pearson Education, 2002

6 | P a g e REFERENCE BOOKS:[R1] Principles of Communication Systems – H. Taub& D. Schilling , TMH, 2nd Edition, 2003. 1. Give the classifications of switching systems. Compare manual exchange and automatic exchange. 2. Draw the elements of a switching system and trunking diagram and explain its function 3. List six events that may occur in a telephone system and the corresponding actions that may have to be taken by the common control system. 4. Draw the trunking diagram of 1000-line exchange. 5. Describe the working of a rotary switch. Differentiate between forward and reverse acting. 6. Explain the various function of switching system. 7. What do you mean by stored and forward Delay? Derive the expression for data transmission delay 8. Classified switching techniques. Make a comparison between circuit and message switching. 9. Explain Register Translator sender. 10. Explain digital Bi - phase differential encoding. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Telecommunication switching system Assignment No. 1 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch: ECE Semester: VI Unit/Title: 1/ INTRODUCTION: Date of Issue: Date of Submission:

7 | P a g e 1. What do you understand by blocking and non-blocking model of telephone traffic? Draw N X N three stage switching network. 2. With the help of neat diagram explain the operation of TSI. Compare TSI with space Switching. 3. What are Re-arrange able networks? Explain partial connection multi-stage networks? 4. Discuss Zero loss switching. 5. List the various advantages & Disadvantages of Digital switching over analog switching. 6. Explain non-blocking switches. 7. Explain DCS Hierarchy integrated cross connects equipment’s. 8. A crossbar exchange is required to set-up 5000 calls in the busy hour. The marker holding times may be assumed to be exponentially distributed with an average holding time of 0.5 sec. find the number of markers required 9. Find the delay in sending an X bit massage over a K hop path in a circuit switched network. The circuit setup is ‘S’ second, the propagation delay is D sec. per hop, the packet size is P bits and the data rate is B bps. 10. Compare the switching Technique used in PSTN. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Telecommunication switching system Assignment No. 2 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch: ECE Semester: VI Unit/Title: II/ DIGITAL SWITCHING: Date of Issue: Date of Submission:

8 | P a g e 1. Discuss the incoming traffic and service time characteristics. 2. What is meant by call congestion in telephone network? 3. Define the term Busy Hour and Grade of service by giving an example. 4. Explain traffic characterization, arrival distribution and holding time distribution. 5. Explain Birth death process in detail. 6. Calculate traffic Erlang B formula 7. Explain kindle’s six parameter notation . 8. Explain CCR,BHCA.,BHCR 9. Explain traffic intensity and all the units of traffic intensity. 10. Difference between LCC,LCH, LCD traffic model. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Telecommunication switching system Assignment No. 3 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch: ECE Semester: VI Unit/Title: III/ TELECOM TRAFFICENGINEERING Date of Issue: Date of Submission:

9 | P a g e 1. List out the main sources of clock instability in a network 2. Why LPF not used in PLL? 3. What are the elements and advantages of elastic store? 4. Explain the following: a. Time Recovery b. Clock instability 5. List out the six basic approaches of synchronizing digital network. 6. What is meant by master-slave synchronization? 7. List out the features of pulse stuffing. 8. Explain the concepts of Slips. 9. Explain in detail about Asynchronous multiplexing. 10. Explain the concepts of network control? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Telecommunication switching system Assignment No. 4 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch: ECE Semester: VI Unit/Title: IV/ Date of Issue: Date of Submission:

10 | P a g e 1. Explain main attraction of PCM modems. 2. How to standardize the ISDN network? 3. List out the features of ISDN B channel. 4. Define NT1. 5. What is meant by ping-pong transmission? 6. Explain the concepts of digital loop carrier system. 7. Describe the conceptual view of hybrid fiber coax systems. 8. Explain SONET in Detail. 9. Define D channel protocol. 10. . Describe the conceptual view of high data rate digital subscriber loops. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Telecommunication switching system Assignment No. 5 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch: ECE Semester: VI Unit/Title: V/ DIGITAL SUBSCRIBER ACCESS Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

11 | P a g e Q1: Describe the working of a rotary switch. Differentiate between forward and reverse acting. Q2: A busy tone does not imply that the called party is actually engaged in a conversation . Q3: Show that the harmonic frequencies of any two adjacent base frequencies in DTMF telephone cannot match within the first 15 harmonics Q4: If the transmitted power of low band frequency signal from a DTMF Telephone is 1 mW, what should be power in mW of the high band frequencies? Q5: In what way is stored program control superior to hard-wired control? TUTORIAL SHEET Course Name: TELECOMMUNICATION SWITCHING SYSTEMS Tutorial Sheet No. 1 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch:ECE Semester: VI Unit/Title: II/ DIGITAL SWITCHING: Date of Discussion:

12 | P a g e Q1: A crossbar exchange is required to set-up 5000 calls in the busy hour. The marker holding times may be assumed to be exponentially distributed with an average holding time of 0.5 sec. find the number of markers required. Q2 Find the delay in sending an X bit massage over a K hop path in a circuit switched network. The circuit setup is ‘S’ second, the propagation delay is D sec. per hop, the packet size is P bits and the data rate is B bps. Q3 Consider 3 stage crossbar switch system with 1000 input and 1000 output lines. It is nonblocking. For an optimum design, what is the total number of cross points required? How many array are needed for each stage? Q4: For a TST switch with a single stage space switch determine the number of cross points and the total number of memory bits required if the number of lines is 32, number of channel per frame is 30 and time expansion is 2. Q5: Since bit of storage are much cheaper then cross points , an approximate measure that has been proposed for comparing the relative costs of networks is the complexity defined as : Complexity= Nc+Nb/100 When Nc = no. of space stages cross points. Nb= No. of bits of memory. Compare the complaxities of the S-T-S network with T-S-T network DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: TELECOMMUNICATION SWITCHING SYSTEMS Tutorial Sheet No. 2 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch:ECE Semester: VI Unit/Title: II/ DIGITAL SWITCHING: Date of Discussion:

13 | P a g e Q1: A group of 20 trunks was found to have ten trunks engaged at 10 am, 15 at 10.10 am and 16 at 10.20 am and 11 at 10.30 am. Calculate the average traffic intensity during this period. Q2: 10 E of traffic is offered to switches that hunt sequentially over a group of trunks .estimate the traffic carried by each of the first three trunks Q3 A PABX provides queuing and automatic call back facility for outgoing calls.If these are 20 outgoing calls request per hour and if average call duration is 3 minutes, how many trunks are needed to ensure delay less than 30 minutes for 90% of request. Q4: During a 2 hour busy period,2400 calls arrive at an exchange. Average holding time per call is two minutes. What is the traffic load in erlangs and in CCS? Q5: Compare Lost Calls Held System (LCHS), against delay systems. A Time Assigned Speech Interpolation (TASI) System has 10 channels and 20 sources connect to it . What is the clipping probability if the activity factor for each source is .4? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name:TELECOMMUNICATION SWITCHING SYSTEMS Tutorial Sheet No. 3 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch:ECE Semester: VI Unit/Title: III/ TELECOM TRAFFIC ENGINEERING Date of Discussion:

14 | P a g e Q1: Explain the concepts of network management. Q2: What is meant by waiting time jitter? Q3: what network synchronization control and management Q4 Draw the diagram of M12 multiplexer? Q5: Explain main purpose of state transition diagram? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: TELECOMMUNICATION SWITCHING SYSTEMS Tutorial Sheet No. 4 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch:ECE Semester: VI Unit/Title: IV/ NETWORK SYNCHRONIZATION CONTROL AND MANAGEMENT Date of Discussion:

15 | P a g e Q1 In a TS switch M=128,N=16 and the number of subscribers connected to the system in 0.1MN. Determine the blocking probability of the switch if all the subscribers are active at the same time. Q2: A telephone company is required to give connections to a few subscribers located at a distance of 15 km from its nearest exchange. Discuss the various design options. Q3: Draw the diagram of downstream V.90 modem concept Q4: . Explain the concepts of Integrated Services Digital Network. Q5: List out advantage and disadvantage of TCM transmission. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name:TELECOMMUNICATION SWITCHING SYSTEMS Tutorial Sheet No. 5 Course Code:TEC-603 Faculty :Mr. Sunny Verma Branch:ECE Semester: VI Unit/Title: V/ DIGITAL SUBSCRIBER ACCESS Date of Discussion:

16 | P a g e Question Bank of Telecommunication switching system Unit-1 1. Give the classifications of switching systems. Compare manual exchange and automatic exchange. 2. In what way is stored program control superior to hard-wired control? 3. Draw the elements of a switching system and trunking diagram and explain its function. 4. In Strowger exchanges a call may be blocked even though an appropriate path through the Switch Exists, Explain how can this happen? 5. With the help of suitable diagram describe the working of a Crossbar Exchange. 6. Describe the working of a rotary switch. Differentiate between forward and reverse acting. 7. State the design parameters for designing strowger switching system. 8. Draw the trunking diagram of 1000-line exchange. 9. Draw the block diagram showing the organization of crossbar exchange and briefly explain the operation. 10. Why is Electronic Exchange alone suitable for digital Telephony? Explain. 11. Compare the switching Technique used in PSTN. 12. List six events that may occur in a telephone system and the corresponding actions that may have to be taken by the common control system. 13. A busy tone does not imply that the called party is actually engaged in a conversation .Explain. 14. Show that the harmonic frequencies of any two adjacent base frequencies in DTMF telephone cannot match within the first 15 harmonics. 15. If the transmitted power of low band frequency signal from a DTMF Telephone is 1 mW, what should be power in mW of the high band frequencies? 16. What do you understand by blocking and non-blocking model of telephone traffic? Draw N X N three stage switching network. 17. Find the delay in sending an X bit massage over a K hop path in a circuit switched network. The circuit setup is ‘S’ second, the propagation delay is D sec. per hop, the packet size is P bits and the data rate is B bps. 18. A crossbar exchange is required to set-up 5000 calls in the busy hour. The marker holding times may be assumed to be exponentially distributed with an average holding time of 0.5 sec. find the number of markers required. UTU(2009-10)

17 | P a g e 19. For local calls , a telephone exchange operates the calling customer’s meter once,when the called customer answers. There is fee of one unit (u) for all local calls. The average duration h of a local call is 3 minutes. It can be assumed that the probability of duration of a call. T exceeding time t is given by P(T≥t)=e^-t/h. if auto-ticketing is introduced then call charges are proportional to its duration. What should be the fee per minute to get the same local call revenue as with periodic–pulse metering? . UTU(2009-10) 20. Write about the synchronous digital transmission in detail. . UTU(2009-10) Unit -2 1. With the help of neat diagram explain the operation of TSI.Compare TSI with space Switching. 2. Consider 3 stage crossbar switch system with 1000 input and 1000 output lines. It is nonblocking. For an optimum design, what is the total number of cross points required? How many array are needed for each stage? 3. For a TST switch with a single stage space switch determine the number of cross points and the total number of memory bits required if the number of lines is 32, number of channel per frame is 30 and time expansion is 2. 4. How many times slot interchange modules are need for an STS switch with 128 primary TDM signals of 30 voice channels per input? Assume blocking to be less than .002and the loading is .2 Erlang per channel and determine the complexity of the switch. 5. What are Re-arrangeablenetworks ? Explain partial connection multi-stage networks? 6. Draw and explain the full connection multistage network. 7. Design a 2-stage network .using switch modules of size 10×10,suitable for connecting 200 incoming trunks to 200 outgoing trunks . the outgoing trunks serve ten routes with 20 trunks on each route. How many switch modules are needed? 8. Since bit of storage are much cheaper then cross points , an approximate measure that has been proposed for comparing the relative costs of networks is the complexity defined as : Complexity= Nc+Nb/100 When Nc = no. of space stages cross points. Nb= No. of bits of memory. Compare the complaxities of the S-T-S network with T-S-T network

18 | P a g e Unit -3 1. A group of 20 trunks was found to have ten trunks engaged at 10 am, 15 at 10.10 am and 16 at 10.20 am and 11 at 10.30 am. Calculate the average traffic intensity during this period. 2. 10 E of traffic is offered to switches that hunt sequentially over a group of trunks .estimate the traffic carried by each of the first three trunks. 3. Sketch a fully inter-connected 3 stage network for the same number of incoming and outgoing Trunks , using 3×4 switches in the primary stage and 4×4 switches in the tertiary stage. How many cross points are neededWhat do you understand by blocking and non blocking model of a telephone traffic? In a group of 100 poisson sources, each one generates message at the rate of one in every 20 second to a single line. If the line rate is 1200bits/second and average message length is 200bits. find the probability of message entering the queue. 4. A PABX provides queuing and automatic call back facility for outgoing calls.If these are 20 outgoing calls request per hour and if average call duration is 3 minutes, how many trunks are needed to ensure delay less than 30 minutes for 90% of request. 5. During a 2 hour busy period,2400 calls arrive at an exchange. Average holding time per call is two minutes. What is the traffic load in erlangs and in CCS? 6. Compare Lost Calls Held System (LCHS), against delay systems. A Time Assigned Speech Interpolation (TASI) System has 10 channels and 20 sources connect to it . What is the clipping probability if the activity factor for each source is .4? 7. An exchange serves 2000 subscribers. If the average BHCA is 10,000 and the CCR is 60%, calculate the busy hour calling rate? 8. A PABX which is designed to be nonblocking internally serves 100 extensions and has four trunk lines. Busy hour calling rate is two. Thirty per cent of the total traffic is external. Average call duration is three minutes, how many trunks are needed to ensure delays less than 30 minutes for 90 percent of the requests? 9. A public call office is installed in a busy part of a town .150 persons use the booth everyday. The average holding time for a call is 1.5 minutes. There is a suggestion from the public that another PCO is required in the same locality as the wait times are unduly long

19 | P a g e .Analyse the situation using M/M/1 queue and determined if the suggestion deserves serious consideration. Unit -4 NETWORK SYNCHRONIZATION CONTROL AND MANAGEMENT 1. List out the main sources of clock instability in a network. 2. Why LPF not used in PLL? 3. What are the elements and advantages of elastic store? 4. How to produce systematic jitter? 5. Define slips. 6. How to control the uncontrolled slips? 7. Define pulse stuffing. 8. Define the term asynchronous. 9. List out the features of pulse stuffing. 10. Draw the diagram of M12 multiplexer? 11. What is meant by waiting time jitter? 12. List out the six basic approaches of synchronizing digital network. 13. What is meant by master-slave synchronization? 14. Explain main purpose of state transition diagram? 15. Define protocol. 16. Explain the following: a. Time Recovery b. Clock instability 17. Explain the concepts of Elastic stores. 18. Explain the concepts of Slips. 19. Explain in detail about Asynchronous multiplexing. 20. Write short notes on network Synchronization? 21. Explain the concepts of network control? 22. Explain the concepts of network management. Unit -5

20 | P a g e DIGITAL SUBSCRIBER ACCESS 1. How to standardize the ISDN network? 2. List out the features of ISDN B channel. 3. List out the features of ISDN D channel. 4. Define NT1. 5. Define NT2. 6. What is meant by ping-pong transmission? 7. List out advantage and disadvantage of TCM transmission. 8. Define D channel protocol. 9. Give short notes on PRS source. 10. Write short notes on clock recovery. 11. What are the disadvantages of LMDS? 12. Draw the diagram of down stream V.90 modem concept. 13. Explain main attraction of PCM modems. 14. Write short notes on digital satellite services. 15. Explain the concepts of Integrated Services Digital Network. 16. Describe the conceptual view of high data rate digital subscriber loops. 17. Explain the concepts of digital loop carrier system. 18. Describe the conceptual view of hybrid fiber coax systems. 19. Explain the concepts of PCM modems. 20. Write notes on a) Address structure of ISDN . b) ISDN service characterization 21. A telephone company is required to give connections to a few subscribers located at a distance of 15 km from its nearest exchange. Discuss the various design options . 22. In a TS switch M=128,N=16 and the number of subscribers connected to the system in 0.1MN. Determine the blocking probability of the switch if all the subscribers are active at the same time.

21 | P a g e TEC-602 VLSI CIRCUIT DESIGN UNIT 1 REVIEW: Current conduction in MOSFET, Electrical Properties of MOS and BiCMOS, The PassTransistor, CMOS. UNIT 2 CMOS Inverter: Static CMOS inverter, layout, switching threshold and noise margin concepts andtheir evaluation, dynamic behavior, power consumption. NMOS MOS pass transistor inverter. COMBINATIONAL LOGIC: Static CMOS design, rationed logic, pass transistor logic, dynamic logic,cascading dynamic gates, CMOS transmission gate logic. UNIT 3 SEQUENTIAL LOGIC: Static latches and registers, bi- stability principle, MUX based latches, staticSR flip-flops, master-slave edge-triggered register, dynamic latches and registers, concept of pipelining,Timing issues. UNIT 4 MEMORY AND ARRAY STRUCTURE: ROM, RAM, peripheral circuitry, memory reliability and yield, SRAM and DRAM design, flash memory, PLA,PAL, FPGA. UNIT 5 DESIGN FOR TESTABILITY: Logic Testing, sequential Logic Testing, Guidelines to be adopted inDesign for Test, Scan Designing Techniques, Built-In self Test (BIST)Techniques. SUGGESTEDBOOKS: 1. Basic VLSI Design by D.A. Pucknell&Eshraghian (PHI) 2. Modern VLSI Design Systems on Silicon by Wayne Wolf (Pearson Pub.) 3. R. K. Singh «VLSI DESIGN (With VHDL), Kataria& Sons », 2nd Edition, 2010.

22 | P a g e SEMESTER/YEAR: 6TH/3RD ECE COURSE: VLSI Design S. No. Topic Name1. Current conduction in MOSFET, 2. Electrical Properties of MOS 3. Electrical Properties of BiCMOS 4. The PassTransistor 5. CMOS 6. CMOS Inverter:Static CMOS inverter7. layout, switching threshold and noise margin concepts andtheir evaluation 8. Dynamic behavior, power consumption9 NMOS MOS pass transistor inverter. 10. COMBINATIONAL LOGIC:Static CMOS rationed logic, , 11. Pass transistor logic, dynamic logic 12 Cascading dynamic gates, CMOS transmission gate logic.13. Sequential Logic:Static latches and registers DBIT DEHRADUN LESSON PLAN VLSI Design Topic Name Reference/ Text Book/ Web (R/T/W) No. Of Lectures T1,R1 3 T1,R1 3 T1,T2 2 T1,R1 2 T1,R1 3 Static CMOS inverter T1,T2 3 layout, switching threshold and noise margin concepts T1,R1 2 Dynamic behavior, power consumption T1,R1 2 NMOS MOS pass transistor inverter. T1,R1 2 Static CMOS design, T1,R1 1 T1,R1 2 Cascading dynamic gates, CMOS transmission gate logic. T1,R1 2 Static latches and registers T1,R1 3 DEPARTMENT: VLSI Design CODE: TEC-602 No. Of Lecture Delivery Method Remarks Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk

23 | P a g e 14. Bi- stability principle, MUX based latches T1,T2 2 Chalk & Talk 15. StaticSR flip-flops, master-slave edge-triggered register T1,R1 2 Chalk & Talk 16 Dynamic latches and registers T1 2 17 Concept of pipelining,Timing issues. T1 1 18 Memory And Array Structure: ROM, RAM, peripheral circuitry T1 3 19. Memory reliability and yield T1,R1 2 Chalk & Talk 20. SRAM and DRAM design T1,R1 3 Chalk & Talk 21. Flash memory, PLA,PAL, FPGA T1,R1 2 Chalk & Talk 22. Design For Testability: Logic Testing T2,R1 2 Chalk & Talk 23. Sequential Logic Testing, Guidelines to be adopted inDesign for Test T2 2 Chalk & Talk 24. Scan Designing Techniques, Built-In self Test (BIST) Techniques T2,R1 2 Chalk & Talk Total Lectures: 53 TEXT BOOKS: [T1] Digital integrated circuit design using CMOS by Yusuf & Kang [T2] Digital circuit design by NEAL WASTE. REFERENCE BOOKS: [R1] . Basic VLSI Design by D.A. Pucknell&Eshraghian (PHI) [R2]. Modern VLSI Design Systems on Silicon by Wayne Wolf (Pearson Pub.) [R3]. R. K. Singh « VLSI DESIGN (With VHDL), Kataria& Sons » , 2nd Edition, 2010. [R4]. S. Gandhi / VLSI Fabrication Principles / 2nd ED. John Willey 1994.

24 | P a g e Question bank of VLSI Design: Unit-1 Q1. What is body affect? Discuss different parameters on which threshold voltage depends? a) Determine Zpu to Zpd ratio for nMOS inverter driven through one or more pass transistor? b) Discuss the gate source and gate drain capacitance of an N-Channel FET. c) Calculate the gate capacitance of an nFET with following parameter. W = 8µm, L= 0.5µm, Cox = 3.45 × 10−7F/cm2. d) Clearly explain the body effect of a MOS FET. e) Clearly explain channel length modulation of a MOS FET. f) With neat sketches, explain the transfer characteristic of a CMOS inverter. g) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. Explain Accumulation, Depletion layers in MOs with Energy band diagram. Q.2. Derive an expression for Depletion depth and Max Depletion depth in MOS structure. Q.3. what do you mean by Scaling and small geometry effects in VLSI design for MOS? Find all the basic parameters of a MOS after constant Electric field scaling and constant voltage scaling. Q.4. Derive an expression for drain current in linear region, saturation region through gradual channel approximation and Channel length modulation. Q.5. what are physical limitations and parasitic effects in miniaturizing the circuits? Explain each in detail. Q.6. Describe the structure and operation of MOSFET with its characteristics. Q.7. Explain how computer aided design technology helps us to design VLSI circuits. Q.8. Write a Short note on spice for circuit simulation. Explain the VLSI Design flow diagram? Q.9. Explain and Draw the V-I characteristics of N-Depletion type-MOSFET (D-MOS). Explain and Draw the V-I characteristics of P-Enhancement type-MOSFET (E-MOS). Q.10 Explain and Draw the V-I characteristics of P -Depletion type-MOSFET (D-MOS). Explain and Draw the V-I characteristics of N -Enhancement type-MOSFET (E-MOS).

25 | P a g e Q.11. what are the basic components of Threshold voltage (VTO or VTH)? Derive an expression for the same with and without body or substrate effect. Q.12. Explain non-ideal I - V effects in MOS. Q.13. Discuss Gate capacitance model and diffusion capacitance model of MOS. Q.14. Consider the MOS transistor with following parameters: tOX = 200Ao, ФGC = - 0.85V, NA = 2 x 1015 cm - 3, QOX = q x 2 x 1011 C / cm2.Determine (a) the threshold voltage VTH under zero body bias at room temperature (T = 300Ko ) given that εOX = 3.97 ε0 and εSi = 11.7 ε0 (b) Determine the type of MOS transistor (N – Type or P – Type ) and amount channel Implant in N / cm required to change the threshold voltage to 0.8 V. Q.15. Derive Drain current equations of MOS transistors (Enhancement N-Type or P- Type) using Gradual Channel approximation theory or model operating in the following regions (i) Linear (ii) Saturation (iii) Cutoff Q.16. Derive Drain current equations of MOS transistors (Enhancement N-Type or P- Type) using Channel length modulation theory or model operating in the following regions (i) Linear (ii) Saturation (iii) Cutoff Q.17. Explain how and when an N channel MOSFET (Enhancement N- MOSFET) conduct current? Q.18. Explain how and when an P channel MOSFET (Enhancement P- MOSFET) conduct current? Q.19. Explain how a channel in MOSFET work for small values of VDS? Q.20. How much we will expect the static power dissipation of gate to be, if we set the inputs of a particular CMOS gate to voltages that correspond to valid logic levels? Q.21. Explain why the threshold voltage of Enhancement N-channel MOSFET is Positive quantity whereas the threshold voltage of Enhancement P-channel MOSFET is Negative quantity? Q.22. Consider the following N- channel MOS process, substrate doped NA = 1016 cm - 3, poly-silicon gate density; NA = 2x1020 cm - 3 , gate oxide thickness tOX = 500Ao, and oxide-interface fixed charge density NOX = 4 x 1010 cm-2.Determine (a) the threshold voltage VTH under zero body bias at room temperature (T = 300Ko ) given that εOX = 3.97 ε0 and εSi = 11.7 ε0 (b) Determine the type of MOS transistor (N – Type or P – Type ) and amount channel Implant in N / cm required to change the threshold to 1V. Assume ФF (gate ) = 0.55V.

26 | P a g e Q.23. Explain why we required BiCMOS circuits to derive large capacitive load (ON-chip loads and OFF chip loads)? Q.24. Explain the static behavior of basic BiCMOS inverter with resistive base pull-down. Also explain the Conventional BiCMOS inverter circuit with active base pull-down. Q.25. Compare the BiCMOS and CMOS with respect to basic designing parameters. What are the applications in complex logic circuits? Q.26 Design and implement the two input NAND and NOR gates Q.26. Explain the circuit operation of CMOS transmission gate (Pass gate). Q.27. Design and implement two input X-OR gate by using (i) Six transistor CMOS transmission gate (ii) Eight transistor CMOS transmission gate. Q.28. Explain why and how the effects that arise when the channel is taken SHORT in MOS structure (Devices)? Q.29. Explain why and how the effects that arise when the channel is taken NARROW in MOS structure (Devices)? Q.30. Compare voltage levels and noise margin for bipolar and CMOS logic family. Q.31. what is body affect? Discuss different parameters on which threshold voltage depends Q.32. Discuss the gate source and gate drain capacitance of a MOSFET.. Q.33.Calculate the gate capacitance of a MOSFET with following parameter. W = 8 µm, L = 0.5 µm, Cox = 3.45 × 10 −7 F/cm 2. Q.34. A CMOS inverter is built in a process where k’n = 100 µA / V 2, Vtn= +0.7V, k'p = 42 µA/ V2 , Vtp =-0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and (W/L)p = 14. Q.35.Find g m for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; µn Cox = 92 µA/V 2. Q.36. A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, µnCox =95µA/V2. Find its drain current and drain source resistance.

27 | P a g e Q.37. Explain Accumulation, Depletion layers in MOs with Energy band diagram. Q.38. Derive an expression for Depletion depth and Max Depletion depth in MOS structure. Q.39. Describe the structure and operation of MOSFET with its characteristics. Q.40. Explain the static behavior of basic BiCMOS inverter with resistive base pull-down. Also Q.41. explain the Conventional BiCMOS inverter circuit with active base pull-down. Q.42. A PMOS transistor is operated in triode region with the following parameters. VGS = - 4.5V, Vtp = -1V; VDS=-2.2 V, (W/L) =95, µn.Cox =95µA/V2. Find its drain current and drain source resistance. Q.43. Explain and Draw the V-I characteristics of P - Depletion type-MOSFET (D-MOS). Explain and Draw the V-I characteristics of N - Enhancement type-MOSFET (E-MOS). (a) Explain how inversion or channel is created in MOs with Energy band diagram. (b) Derive an expression for offset Depletion depth and Max Depletion depth in MOS structure. (c) Describe the structure and operation of Enhancement N- MOSFET with its characteristics. (d) A NMOS transistor is operated in triode region with the following parameters. VGS= 4.5V, Vtp = 1V; VDS=2.2 V, (W/L) =95, µn.Cox =95µA/V2. Find its drain current and drain source resistance. (e) Explain and Draw the V-I characteristics of N - Depletion type-MOSFET (D-MOS). Explain and Draw the V-I characteristics of N - Enhancement type-MOSFET (E-MOS). (f) Explain why we required BiCMOS circuits to derive large capacitive load (ON-chip loads and OFF chip loads)? (g) Explain and Draw the V-I characteristics of P - Depletion type-MOSFET (D-MOS). Explain and Draw the V-I characteristics of P - Enhancement type-MOSFET (E-MOS). (h) Calculate the gate capacitance of a MOSFET with following parameter. W = 10 µm, L = 1 µm, Cox = 3 × 10 −8 F/cm 2. (i) Findgm for an p-channel transistor with Vgs= -1.2V: Vtn = - 0.8V; (W/L) = 10; µn Cox = 90 µA/V 2. (j) What are the basic components of Threshold voltage (VTO or VTH)? Derive an expression for the same with and without body or substrate effect. (k) Explain how much short & narrow channel threshold voltage changes? (l) Calculate and explain

28 | P a g e (m) Design and implement two inputs dynamic CMOS transmission X-OR gate (n) Explain the charging and discharging time and voltage across the parasitic capacitance (o) Implement the followings using N-MOS dynamic logic function (i) Z = ( AB + CD + E )’ (ii) Z = {(D +E + A)(B + C)}’ (p) Implement the followings using C-MOS dynamic logic function and (i) Z = ( AB + CD + E )’ (ii) Z= {(D +E + A)(B + C)}’ (q) Draw the mask-layout diagram of two input NAND and NOR using CMOS. Draw the stick diagram of two input NAND and NOR using CMOS. (r) Calculate junction capacitance with and without side walls between drain and substrate. (s) What do you mean by Scaling and small geometry effects in VLSI design for MOS? What are advantages and disadvantages of constant Electric field scaling over constant voltage scaling. (t) Derive an expression for drain current in linear region, saturation region through gradual channel approximation and Channel length modulation for NMOS. Unit – 2 Q.1. Explain the VTC (Voltage transfer characteristics) of NMOS Inverter with (i) resistive load (ii) Active loads. Also calculate VIL , VIH , VOL , VOH , VTH ,also analyze Power consumption, Chip area, Noise margins. Q.2. Design and implement 1-bit full adder logic circuit using C - MOS. Q.3. Short note on spice for circuit simulation. Explain the VLSI Design flow diagram? Q.4. Draw layout and stick diagram of the logic functions: (i)Z = ( AB + CD + E )’ (ii) {(D +E + A)(B + C)}’ using CMOS. Q.5. Implement and explain two inputs NOR & NAND gate using N-MOS with resistive and active load. Q.6. Explain the static and dynamic behavior of CMOS Inverter. Also calculate VIL , VIH , VOL , VOH , VTH ,also analyze Power consumption, Chip area, Noise margins. What is the criteria for threshold voltage for high level and low level in inverter characteristicss?

29 | P a g e Q.7. Implement the circuit diagram and the corresponding layout and stick diagram of a two inputs NOR & NAND gate using C-MOS technology. Q.8. Design and Implement the following with C-MOS transmission gate (i) Two input multiplexer circuit i.e. F = AS’ + BS (ii) Two input XOR gate i.e. F = AB’ +A’B (iii) F = AB + A’C’ + AB’C Q.9. Explain the logical operation to transfer logic 0 or 1 though dynamic MOS logic. And Explain the concept of charge leakage and storage through the dynamic MOS logic. Also explain why we do require the voltage bootstrapping in dynamic MOS logic? Q.10. Differentiate between ratioed and ratioless dynamic logic explain with example. Q.11. Write a note on spice for VLSI circuits simulation. Q.12. Design and implement half adder logic circuit using C - MOS. Q.13. Explain CMOS inverter layout plan along with its cross-sectional diagram. What is a stick diagram? What do you mean by Lemda based design rule? Q.14. Explain the operation of CMOS inverter when Vin = Vth . Q.15. Explain What is the propagation delay limitations in the CMOS digital integrated circuits? Q.16. Implement and draw the circuit schematic of a (2 x 1)- multiplexer using CMOS transmission gates. Q.17. With the help of a neat circuit diagram show the implementation of the logic function: . Y = A + (B + C) . (D +E) using Ratioed CMOS logic. Q.18. Design a circuit described by the function Y = A . (B + C) . (D + E) using CMOS logic. Also find the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that (W /L)P = 5for all P - MOS transistors and (W /L)N = 2for all N - MOS transistors and Q.19. Derive and calculate the switching threshold voltage Vth of two-input CMOS NOR gate with the following parameters: (W /L)P = 4for all P-MOS transistors and(W /L)N = 1for all N - MOS transistors, (VTO) for N = 0.7V, (VTO) for P =- 0.7V, µn COX = 40 µA/ V2 , µp COX = 20 µA/ V2 , VDD = 5V. Q.20. Discuss how the charge sharing problem can be overcome in dynamic CMOS logic?

30 | P a g e Q.21. Calculate the values of VOH, VOL , VIH , VIL and noise margin NML for a saturated Enhancement load N-MOS inverter circuit. Given VDD = 5V, VT = VTO = 0.8V and kdriver / kload =10. Q.22. Determine Z pu to Z pd ratio for N-MOS inverter driven through one or more pass transistor. Q.23. Consider the MOS transistor with following parameters: tOX = 250Ao, ФGC = -0.95V, ND = 3 x 1015 cm - 3, QOX = 4 x 1011 C / cm2.Determine (a) the threshold voltage VTH under zero body bias at room temperature (T = 300Ko ) given that εOX = 3.97 ε0 and εSi = 11.7 ε0 (b) Determine the type of MOS transistor (N – Type or P – Type ) and amount channel Implant in N / cm required to change the threshold voltage to -1.5 V. Q.24. Explain the VTC (Voltage transfer characteristics) of CMOS Inverter. Also calculate VIL , VIH , VOL , VOH , VTH , for N-MOS with depletion load. Also analyze Power consumption, Chip area, Noise margins. Q.25. Design and implement the following using NMOS, CMOS (i)Z = ( AB + CD + E )’ (ii) Z = {(D +E + A)(B + C)}’ (iii)Z = ( AB + CD + E ) (iv) Z = {(D +E + A)(B + C)}’ Unit-3 Q.1. Design and implement clocked (positive edge trigger) J-K, S-R, T, D flip-flops sequential logic circuit using C – MOS with timing diagrams. Q.2.Explain the design of standard cells for VLSI circuits. What are the design considerations for digital ICs? Q.3. Design and implement clocked (negative edge trigger) J-K, S-R, T, D flip-flops sequential logic circuit using C – MOS with timing diagrams. Q.4. what do you understand by the term excitation table? Show the excitation tables for SR, JK, T, D flip-flops. Q.5. explain the time and phase behavior of a CMOS bistable element with circuit diagram. Q.6 Explain the operation of two input NOR and NAND based SR, JK, D, T latch using CMOS. Q.7. Explain the operation of two input NOR and NAND based SR, JK, D, T latch using NMOS with depletion load. Q.8.Design and implement JK latch using CMOS.

31 | P a g e Q.9.Design and implement Master-slave FF consisting NAND based JK latches with output timing waveforms. Q.10 Explain the CMOS D latch that showing the setup time and hold time. Q.11 Design and implement the schematic of CMOS negative (falling) edge triggered master slave based on D FF. Q.12. Design and implement three input NAND based positive (rising) edge triggered D FF with timing diagram of input and outputs. Q.13 Design and implement Enhancement-load dynamic shift register (ratioed logic). Q.14 Design and implement Enhancement-load dynamic shift register (ratioless logic). Q.15. Explain the operation of basic building block of a CMOS transmission gate dynamic shift register Q.16. Design and implement the following function using dynamic CMOS logic gate: F = (A.B.C + D.E)’. Unit-4 Q.1. Classify the memories on the basis of technology. Explain the read and write operation of Static RAM ( SRAM ) with schematic circuit diagram. How 1 bit cell is used for bigger memory systems Q.2. Discuss the architecture of CPLD in detail. State the advantages of FPGA and CPLD design methods. Q.3. Explain the ASIC design flow and different types of ASIC. Also explain the programmable structures for PLA. Q.4. Design and implement a BCD to Gray code convertor circuit using PAL. Q.5. Explain SRAM, DRAM, FLASH memories on the basis of technology. Explain the read and write operation of Dynamic RAM ( DRAM ). Q.6. Discuss the architecture of FPGA in Detail. Also differentiate between FPGA and CPLD. Q.7. Explain the function of CPLD with each block in detail.

32 | P a g e Q.8. Design and implement a circuit using PAL for the following functions: F1 = X.Y.Z + X’.Y’ F2 = W’.F’ + W.X.Y’.Z Also explain the programmable structures for PAL. Q.9. Using an FPGA discuss the programming required for the implementation of following cases: (i) 2 input NOR gate (ii) 2 input NAND gate (iii) 2 input AND gate (iv) 2 input OR gate Q.10. With help of suitable diagram explain a typical CLB available in the FPGAs. Q.11. Explain the Read/write operation and equivalent circuits of following memory cells (i)DRAM (ii)SRAM (iii) Mask (fuse) ROM (iv) EPROM (v) EEPROM (vi) flash RAM Q.12. Explain RAM array memory organization with complete block diagram. Q.13 Explain the concept of leakage currents in DRAM. How DRAM are refreshed? Q.14 Explain the concept of leakage currents in SRAM. How SRAM are refreshed? Q.15. What are data programming and erasing technologies in flash memory? Q.16.Design and implement NAND and NOR based flash memory cell. Q.17. what is the basis for standard-cell? What are basic classes of circuits for Library cells? Q.18. Explain the methods of programming of PAL CMOS device. Draw and explain the architecture of an FPGA. Q.19. What are different classes of Programmable CMOS devices? Explain them briefly. Q.20. What are the advantages and disadvantages of the reconfiguration. Q.21. Mention different advantages of Anti fuse Technology. Q.22. Using PLA Implement Full-adder circuit. Q.23. Compare the Antifuse and Vialink programmable interconnections for PAL devices. Q.24. What are different typically available SSI Standard-cell types and compare them. Q.25. Draw the diagram of programmed I/O pad and explain how the antifuses are used in this.

33 | P a g e Q.26.Draw and explain the AND/OR representation of PLA. Q.27. what are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? Q.28. Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic. Q.29. Draw the typical architecture of PAL and explain the operation of it. Q.30. what is CPLD? Draw its basic structure and give its applications. Q.31. Draw and explain the Antifuse Structure for programming the PAL device. Q.32. Explain how the I/O pad is programmed in FPGA. Q.33. what are different classes of Programmable CMOS devices? Explain them briefly. Q.34. Draw the typical standard-cell structure showing regular-power cell and explain it. Q.35. What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. Q.36.Explain any one chip architecture that used the antifuse and give its advantage. Q.37. Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: (a) PLA (b) PAL (c) FPGA (d) CPLD Q.38. Draw the typical standard-cell structure showing low-power cell and explain it. Q.39. Sketch a diagram for two inputs XOR using PLA and explain its operation with the help of truth table. Unit-5 Q.1. What is need of VLSI testing at various levels? Explain the design strategies for VLSI testing with block diagram for various logic. Q. 2. Discuss in details testing and verification of VLSI circuits. Q.3. what do you mean by silicon debug principles? Explain briefly test benches and hardness. Q.5. Boundary scan test techniques are grouped by the IEEE standards organisation into standard access port and boundary scan architecture. Write down atleast four advantages of boundary scan test. Q.6. Explain in detail Built-in self test (BIST) for circuit testing in VLSI. Q.7 Explain the various Fault types and Fault models in VLSI circuits.

34 | P a g e Q.8 what do you mean by electric logical stuck-at-0 and stuck-at-1 faults, explain with suitable example. Q.9. Define the terms Controllability and Observability for VLSI circuits testing with example. Q.10. Explain Ad-Hoc testing techniques for VLSI circuits testing with example. Q.11. Explain Scan-Based techniques for VLSI circuits testing with example. Q.12. Explain Current monitoring IDDQ techniques for VLSI circuits testing with example. Q.13. Which testing techniques are used for sequential logic circuits. Explain with example Q.14. Explain how function of system can be tested. Q.15.Why the chip testing is needed? At what levels testing a chip can occur? Q.16. What is the drawback of serial scan ? How to overcome this? Q.17. A sequential circuit with in? inputs and ‘m’ storage devices. To test this circuit how many test vectors are require? Q.18. Explain the ATPG with respect to CMOS based chip testing: Q.19. Explain how the cost of chip can effect with the testing levels, Q.20. How the Iterative Logic Array Testing can be reduced number of tests. Q.21. What type of defects are tested in manufacturing testing methods? Q.22. Explain the manufacturing test of a chip with suitable examples. Q.23. Explain how an Ad-hoc test technique used to test long counters? Q.24.Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout.

35 | P a g e 1. A CMOS inverter is built in a process where k’n = 100µA/V2, Vtn= +0.7V, k'p = 42 µA/V2, Vtp=-0.8V, and a power supply of VDD = 3.33V is used .Find midpoint voltage VM if (W/L)n =10 and (W/L)p= 14. 2. Discuss the CMOS invertors transfer characteristics. 3. Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10µn Cox = 92µA/V2. 4. Define the term threshold voltage of MOSFET and explain its significance. 5. Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region. 6. A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; VDS= -2.2 V, (W/L) = 95, µnCox = 95µA/V2. Find its drain current and drain source resistance. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN Tutorial No. 1

36 | P a g e Calculate the gate capacitance of an nFET with following parameter. W = 8µm, L= 0.5µm, Cox = 3.45 × 10−7F/cm2. 1. Design a stick diagram and layout diagram for the CMOS logic shown below Y = (A + B) (C + D). 2. What is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. 3. are the effects of scaling on VT? 4. What are design rules? Why is metal- metal spacing larger than poly -poly spacing. 5. What is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: 1 Date of Issue: Date of Submission:

37 | P a g e 1. Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic. 2. Draw the typical architecture of PAL and explain the operation of it. 3. What is CPLD? Draw its basic structure and give its applications. 4. Draw and explain the Antifuse Structure for programming the PAL device. 5. Explain how the I/O pad is programmed in FPGA. 6. What are different classes of Programmable CMOS devices? Explain them briefly. 7. What is the basis for standard-cell? What are basic classes of circuits for Library cells? 8. Draw the typical standard-cell structure showing regular-power cell and explain it. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN Tutorial No. 2 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: 1I Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN Tutorial No. 3 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: 1II Date of Issue: Date of Submission:

38 | P a g e Explain the gate level and function level of testing. 1. A sequential circuit with n inputs and ‘m’ storage devices. To test this circuit how many test vectors are required? 2. What is sequential fault grading? Explain how it is analyzed. 3. Explain how the cost of chip can effect with the testing levels, 4. Explain how observability is used to test the output of a gate within a larger circuit. 5. How the Iterative Logic Array Testing can be reduced number of tests. 6. Explain how the cost of chip can effect with the testing levels, DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name: VLSI CIRCUIT DESIGN Tutorial No. 4 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: 1V Date of Issue: Date of Submission:

39 | P a g e 1. Explain how an Ad-hoc test technique used to test long counters. November 2008 set4 2. Explain the gate level and function level of testing. 3. A sequential circuit with n inputs and ‘m’ storage devices. To test this circuit how many test vectors are required? 4. What is sequential fault grading? Explain how it is analyzed. 5. Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout. 6. Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level diagrams of its implementation. 7. Explain how function of system can be tested. 8. Explain any one of the method of testing bridge faults. 9. What type of faults can be reduced by improving layout design? 10. Explain the functionality test of a chip with suitable examples. 11. What are the categories of Design for testability? Explain them briefly DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET

Course Name: VLSI CIRCUIT DESIGN Tutorial No. 5 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: V Date of Issue: Date of Submission:

40 | P a g e 1. What is body affect? Discuss different parameters on which threshold voltage depends? 2. Determine Zpu to Zpd ratio for nMOS inverter driven through one or more pass transistor? 3. Discuss the gate source and gate drain capacitance of an N-Channel FET. 4. Clearly explain the y effect of a MOS FET. 5. Clearly explain channel lengbodth modulation of a MOS FET. 6. With neat sketches, explain the transfer characteristic of a CMOS inverter. 7. Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. 8. Explain the operation of BiCMOS inverter? Clearly specify its characteristics. 9. Explain how the BiCMOS inverter performance can be improved. 10. Derive an equation for Ids of an n channel enhancement MOSFET operating in saturation region. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

41 | P a g e 1. Design a stick diagram for two input n-MOS NAND and NOR gates. 2. What is a stick diagram and explain about different symbols used for components in stick diagram. 3. Draw the stick diagram and layout for a) NMOS inverter. b). P-Well CMOS inverter. 4. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. 5. Draw the following transistors using lambda based design rules (a) . NMOS enhancement (b) . NMOS depletion (c) PMOS enhancement. 6. Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules. 7. What are design rules? Why is metal- metal spacing larger than poly –poly spacing. 9 ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 1 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: I Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 2 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: I Date of Issue: Date of Submission:

42 | P a g e 1. what are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? 2. Draw and explain the pseudo-nMOS PLA schematic for full adder and what are the advantages and disadvantages of it. 3. What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. 4. Explain any one chip architecture that used the antifuse and give its advantages 5. Draw a self timed dynamic PLA and what are the advantages of it compared to footed dynamic PLA. 6. Explain the tradeoffs between using a transmission gate or a tristate buffer to implement an FPGA routing block. 7. Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: (a) PLA (b) PAL (c) FPGA (d) CPLD DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 3 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: I Date of Issue: Date of Submission:

43 | P a g e 1. Draw the typical standard-cell structure showing low-power cell and explain it 2. Sketch a diagram for two input XOR using PLA and explain its operation with the help of truth table. Explain different fault models in detail. 3. Explain how function of system can be tested. 4. Explain any one of the method of testing bridge faults. 5. What type of faults can be reduced by improving layout design? 6. Why the chip testing is needed? At what levels testing a chip can occur? 7. What is the drawback of serial scan ? How to overcome this? 8. . What is the percentage fault coverage? How it is calculated. 9. Explain the following with respect to CMOS testing: (a) ATPG (b) Fault simulation (c) Statistical Fault Analysis (d) Fault Sampling. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 4 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: I Date of Issue: Date of Submission:

44 | P a g e 1. Explain the gate level and function level of testing. 2. A sequential circuit with in? inputs and ‘m’ storage devices. To test this circuit how many test vectors are required. 3. What is sequential fault grading? Explain how it is analyzed. 4. Explain how the cost of chip can effect with the testing levels, 5. . Explain how observability is used to test the output of a gate within a larger circuit. 6. How the Iterative Logic Array Testing can be reduced number of tests 7. What type of defects is tested in manufacturing testing methods? 8. What is the Design for Autonomous Test and what is the basic device used in this? 9. What type of tests is used to check the noise margin for CMOS gates? 10. Explain the manufacturing test of a chip with suitable examples. 11. Explain the gate level and function level of testing. 12. A sequential circuit with n inputs and ‘m’ storage devices. To test this circuit how many test vectors are required? 13. What is sequential fault grading? Explain how it is analyzed DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: VLSI CIRCUIT DESIGN ASSIGNMENT No. 5 Course Code:TEC-602 Faculty : K.C. Tyagi Branch: ECE Semester: 6TH Unit/Title: I Date of Issue: Date of Submission:

45 | P a g e DevBhoomi Group of Institutions, DehradunIInd Sessional Examination May,2015Subject: VLSI DESIGN1. All questions are compulsory and equal marks.2. Use of non-programmable calculator is allowed. 3. Assume suitably in case of missing data.4. Roll No. to be filled in your Answer Book.Q.1. Attempt any four parts of the following: [4 *5 = 20 ]a) Consider logic gate for the Boolean function: Design and implement using CMOS Technology: Z = (V.W.X + Y.Z) b) Explain the threshold voltage of a MOS device and explain its significance. c) A MOS transistor has threshold voltage (Vthreshold voltage for VSB = 5 V and 2φd) Describe the channel length modulation in MOSFET. e) Consider an ideal n-channel MOSFET with parameters: L = 2.25 µm, µF/cm2, and VT,n= 0.75 V. Design the channel width W such that If) Explain the CMOS inverter static or DC voltage transfer characteristics.Q.2. Attempt any four parts of the following: [4 *5 = 20]a) Calculate the noise margin of CMOS inverter with VV2. b) What are the advantages of Bi CMOS technology over the CMOS technology? c) Design 2x1 multiplexer circuit using CMOS transmission gate. d) Explain the parasitic capacitances in MOSFET. How can you minimize the parasitic effects occurring in MOSFETs? e) Explain short channel & narrow channel effects.f) Draw the layout diagram of 2-input NAND gate.Q.3. Attempt any two parts of the folloa) Design, implement and explain JK flip flop using CMOS. Also design D flip flop using minimum number of transistors. DevBhoomi Group of Institutions, DehradunSessional Examination May,2015 Subject: VLSI DESIGN All questions are compulsory and equal marks. programmable calculator is allowed. in case of missing data. Roll No. to be filled in your Answer Book. Q.1. Attempt any four parts of the following: [4 *5 = 20 ]a) Consider logic gate for the Boolean function: Design and implement using CMOS Technology: Z = of a MOS device and explain its significance. c) A MOS transistor has threshold voltage (VTO) of 0.80. If the body effect coefficient’γ’ = 0.69. Calculate the = 5 V and 2φF = -0.60 V. take εo = 8.86 x 10 -14 F/cm, εsi = 11.7 εd) Describe the channel length modulation in MOSFET. channel MOSFET with parameters: L = 2.25 µm, µn= 750 cm5 V. Design the channel width W such that ID(sat) = 5 mA for VGS f) Explain the CMOS inverter static or DC voltage transfer characteristics. Q.2. Attempt any four parts of the following: [4 *5 = 20]lculate the noise margin of CMOS inverter with VDD = 5 V, VTO,N= 2 V, VTO,P= b) What are the advantages of Bi CMOS technology over the CMOS technology? c) Design 2x1 multiplexer circuit using CMOS transmission gate. d) Explain the parasitic capacitances in MOSFET. How can you minimize the parasitic effects occurring in e) Explain short channel & narrow channel effects. input NAND gate. Q.3. Attempt any two parts of the following: [2 *10 = 20]a) Design, implement and explain JK flip flop using CMOS. Also design D flip flop using minimum number DevBhoomi Group of Institutions, Dehradun Branch: ECE/EEE Semester/Year: VI/III Course Code:TEC-602 Session: 2014-15 Total Marks: 100 Duration: 3Hrs Q.1. Attempt any four parts of the following: [4 *5 = 20 ] a) Consider logic gate for the Boolean function: Design and implement using CMOS Technology: Z = ) of 0.80. If the body effect coefficient’γ’ = 0.69. Calculate the = 11.7 εo F/cm. = 750 cm2/ V.s, COX= 5.9 x 10-8 = 4 V. Q.2. Attempt any four parts of the following: [4 *5 = 20] = - 2 V, kn= kp = 250 µA/ d) Explain the parasitic capacitances in MOSFET. How can you minimize the parasitic effects occurring in wing: [2 *10 = 20] a) Design, implement and explain JK flip flop using CMOS. Also design D flip flop using minimum number

46 | P a g e b) Explain dynamic logic design techniques for multi-stage combinational logic circuits. Explain pre-recharge and evaluate dynamic logic technique in detail. c) Draw the block diagram of memory organization. Design and explain the read & write operation of single bit DRAM & SRAM using CMOS. Q.4. Attempt any two parts of the following: [2 *10 = 20] a) What is PLA? What are the different types of structures? Design & implement single bit full adder. b) Design & implement the following combinational functions using PAL: Y = A.B.C.D’ + A’.B.C’.D + B.C.D’ + A.B’.D’. Z = A’BCD’ + ABCD + AB’C’D’ + A’B’C’ +BC’D’ c) Discuss the different applications and advantages of FPGA. What are different components of a simple Xillinx FPGA? Q.5. Attempt any two parts of the following: [2 *10 = 20] a. What is need of VLSI testing at various levels? Explain the design strategies for VLSI testing with block diagram. Explain the various Fault types and Fault models in VLSI circuits. b. (i) Define the terms Controllability and Observability for VLSI circuits testing with example. (ii) What do you mean by electric logical stuck-at-0 and stuck-at-1 faults, explain with suitable example. c. (i) Explain in detail Built-in self test (BIST) for circuit testing in VLSI. (ii) Explain scan based testing design technique for testability.

47 | P a g e DevBhoomi Group of Institutions, Dehradun Course /Branch: ECE Year/Semester: - 3RD /VITH Subject (With Code):- VLSI Circuit Design (TEC 602) First internal Exam Session: 2015 -2016 Max Marks: 50 Max. Time: 2Hr’s Roll No Note: 1. All Questions are compulsory; 2. No student can leave the examination hall before completion of the time. Question No: (1) Attempt any four Questions: - [Marks 4 X 2.5 = 10] (a). Design the circuit shown in figure to obtain a current ID of 80 mA. Find the value required for R, and find the dc voltage VD. Let the NMOS transistor have Vt = 0.6 V, NCOX = 200 µA/V2, W/L = 5. Neglect the channel length modulation effect. (b). With the help of diagrams explain MOS system under external bias. (c). If an NMOS has NCOX = 10 µA/V2, W/L = 10. Find ID if (a) VDS = 0.6 V (b) VDS = 0.9 V. it is given that VGS = 1.5 V and VT0 = 0.7 V. (d). Differentiate between enhancement type and depletion type MOSFET. Also draw their symbols. (e). Sketch the cross-section and explain the operation of an n channel depletion type MOS transistor. Draw the drain characteristics and its transfer curve.

48 | P a g e (f). Question No: (2) Attempt any four Questions: - [Marks 4 X5 = 20] (a). Find depletion layer width xd, depletion layer charge QB0, threshold voltage VT0, and body effect coefficient ɣ. Given that tOX = 500 A. NOX = 1.45 x 1016 cm-3, ND = 1018 cm-3 and NOX = 5 x 1010 cm-2. (b). Explain channel length modulation with neat sketch. (c). What is body effect? Explain. (d). What are different short channel effects in MOSFET? (e). What do you mean by strong inversion of MOSFET? Question No: (3) Attempt Any Two Questions: - [Marks 2 * 10 =20] (a). Calculate the threshold voltage VT0 at VSB = 0, for a polysilicon gate n channel MOS transistor with the following parameters, substrate doping density NA = 1016 cm-3, polysilicon gate doping density ND = 2 x 1020 cm-3, gate oxide thickness tOX = 500 A and oxide fixed charge density NOX = 4 x 1010 cm-2. (b). Explain gradual channel approximation with neat sketch and find voltage current characteristics of MOSFET. (c). A MOS transistor has threshold voltage of 0.85 V. The body effect coefficient γ = 0.64. Calculate the threshold voltage for VSB = 4V and 2φF = -0.58 V.

49 | P a g e DevBhoomi Group of Institutions, Dehradun (Ist internal exam March-2016) Subject Code: TEC 602 Name of the Subject: VLSI design Class: ECE/EEE-6thsem Maximum Marks: 50 Time Allowed: 2:00 Hour 1) All Questions are compulsory; 2) As choices are more no change in the question paper is allowed. Question No: (1) Attempt Any Four Questions: - [Marks 4 * 2.5 =10] (u) Explain Accumulation, Depletion layers in MOs with Energy band diagram. (v) Derive an expression for Depletion depth and Max Depletion depth in MOS structure. (w) Describe the structure and operation of Enhancement N-channel MOSFET with its characteristics. (x) A PMOS transistor is operated in triode region with the following parameters. VGS = - 4.5V, Vtp = -1V; VDS=-2.2 V, (W/L) =95, µn.Cox =95µA/V2. Find its drain current and drain source resistance. Question No: (2) Attempt Any Four Questions: - [Marks 4 * 5 =20] (a) What are the basic components of Threshold voltage (VTO or VTH)? Derive an expression for the same with and without body or substrate effect. (b) Describe the channel length modulation in MOSFET. Consider an ideal n-channel MOSFET with parameters: L = 1.25 µm, µn= 650 cm2/ V.s, COX= 6.9 x 10-8 F/cm2, and VT,n= 0.65 V. Design the channel width W such that ID(sat) = 4 mA for VGS = 5 V. (c) Explain the threshold voltage of a MOS device and explain its significance. A MOS transistor has threshold voltage (VTO) of 0.85. If the body effect coefficient ’γ’ = 0.64. Calculate the threshold voltage for VSB = 4 V and 2φF = -0.58 V. take εo = 8.86 x 10 -14 F/cm, εsi = 11.7 εo (d) Explain short & narrow channel and their effects in MOS. (e) Draw layout diagram of 2 input-NOR gate. Question No: (3) Attempt any two Questions: - [Marks 2 * 10 =20] a) (i) Explain the MOSFET capacitances in details. (ii) Consider a logic gate for the Boolean function: Design and implement using CMOS Technology: Z = (A.B.C + D.E)’ b) Explain the CMOS inverter static or DC voltage transfer characteristics. Calculate the noise margin of CMOS inverter with VDD = 5 V, VTO,N= 1 V, VTO,P= - 1 V, kn= kp = 210 µA/ V2 .

50 | P a g e c) Design half adder and 4x1 multiplexer circuit using CMOS transmission gate.

51 | P a g e DevBhoomi Group of Institutions, Dehradun Course /Branch: ECE Year/Semester: - 3RD /6TH Subject (With Code):- VLSI Circuit Design (TEC 602) Second internal Exam-April-2016 Session: 2015 -2016 Max Marks: 50 Max. Time: 2Hr’s Roll No Note: 1. All Questions are compulsory; 2. No student can leave the examination hall before completion of the time. Question No: (1) Attempt any four Questions: - [Marks 4 X 2.5 = 10] a) Explain behavior of Bistable elements. b) Explain the CMOS D latch that showing the setup time and hold time. c) Discuss how the charge sharing problem can be overcome in dynamic CMOS logic design. d) Explain the concept of N-MOS pass transistor in synchronous dynamic logic design. e) Why we require refreshing cycle in DRAM. Discuss various leakage currents in RAMs Question No: (2) Attempt any four Questions: - [Marks 4 X5 = 20] a) What is SR Latch? Explain basic principle of CMOS SR latch. b) Design, implement and explain JK flip flop using CMOS. c) Design and implement the following function using dynamic CMOS logic gate: F = (A.B.C + D.E)’. d) Explain the Read/write operation and equivalent circuit of 1 bit flash memory cell. e) What do you understand by the term excitation table? Show the excitation tables for SR, JK, T, D flip-flops. f) Design and implement a 4bit x 4bit NOR based ROM Array

52 | P a g e a) Explain dynamic logic design techniques for multi-stag a) Consider logic gate for the Boolean function: Design and implement using CMOS Technology: Z = (V.W.X + Y.Z) b) Explain the threshold voltage of a MOS device and explain its significance. c) A MOS transistor has threshold voltage (VTO) of 0.80. If the body effect coefficient’γ’ = 0.69. Calculate the threshold voltage for VSB = 5 V and 2φF = -0.60 V. take εo = 8.86 x 10 -14 F/cm, εsi = 11.7 εo F/cm. d) Describe the channel length modulation in MOSFET. e) Consider an ideal n-channel MOSFET with parameters: L = 2.25 µm, µn= 750 cm2/ V.s, COX= 5.9 x 10-8 F/cm2, and VT,n= 0.75 V. Design the channel width W such that ID(sat) = 5 mA for VGS = 4 V. f) Explain the CMOS inverter static or DC voltage transfer. g) A PMOS transistor is operated in triode region with the following parameters. VGS = - 4.5V, Vtp = -1V; VDS=-2.2 V, (W/L) =95, µn.Cox =95µA/V2. Find its drain current and drain source resistance. d) A MOS transistor has threshold voltage of 0.85 V. The body effect coefficient γ = 0.64. Calculate the threshold voltage for VSB = 4V and 2φF = -0.58 V.

53 | P a g e TEC-601 MICROWAVE TECHNIQUES UNIT 1 ELEMENTS OF MICROWAVE/MILLIMETER WAVE INTEGRATED CIRCUITS: classification ofTransmission lines: Planar, quasi- planar and 3D structure and their properties, field distribution and range of application, Transverse transmission the techniques for multi-dielectric planar structure, Analysis of discontinuities in planar and non-planar transition line. UNIT 2 PROPAGATION THROUGH WAVEGUIDES: Rectangular and circular waveguides solution of waveequation for TE & TM modes, degenerate and dominant modes, power transmission power loss, Excitation of wave guides , Non existence of TEM mode in waveguide, Introduction to stripline and Microstrip-line. UNIT 3 MICROWAVE CAVITY RESONATORS: Rectangular and cylindrical cavities, Quality factor andExcitation of cavities. Microwave Components: Waveguide couplings, bends and tourists, Design and circuit realization of filters, couplers, phase shifters, E-plane, H-plane and hybrid Tees, Hybrid ring wave meters: Isolators and circulators, tunable detectors, slotted line carriage, VSWR meter. UNIT 4 MICROWAVE MEASUREMENTS: measurement of frequency, wave length, VSWR, impedance,Attenuation Low and high power radiation patterns. Limitation of Conventional active devices at microwave frequency. UNIT 5 MICROWAVE TUBES: Klystron, Reflex klystron,magnetron, TWT, BWO: principle of operation andits performance characteristic and application. SUGGESTEDBOOKS: 1. Pozar « Microwave Engineering » 3rd edition, John Wiley (India). 2. Microwave Engg. , Radhakrishna, BSP Publication 3. Collin, R.E. Foundations for Microwave Engineering; TMH 2ndEd. 4. Rizzi, Microwave Engineering: Passive Circuits; PHI.

54 | P a g e MICROWAVE ENGINEERING QUESTION BANK Q1 Compare the multi-cavity klystron, reflex klystron, magnetron and Traveling wavetube onthe basis of their a) Basic construction ,b) Operation, c) Applications Q2 Explain how the oscillations are sustained in cavity magnetron with suitablesketchesassuming that the _ mode oscillations already exist. Q3 What are the various UHF limitations of vacuum tubes which limit their use at highfrequencies? Describe each of these in detail and suggest remedial measures. Q4 Distinguish between velocity modulation and current modulation. Q5 what is Hull cut off field? Q6 What is phase focusing effect in magnetron? Q7 What is a slow wave structure and why is it required? Q8 What are reentrant cavities? Q9 What is the purpose of strapping in magnetron? Q10 What is electron bunching? How does it occur? Why is it also called intensitymodulation? Q11 Explain the construction and working of a multicavity klystron. Q12 Describe the _-mode of operation of magnetron. Discuss bunching phenomenonas well.Draw neat diagram s wherever required. Q13 Elaborate the concept of velocity modulation, current modulation and bunching withreference to klystron (two cavity) Q14 What is Hull-voltage in a magnetron? Q15 In what type of application reflex klystron is preferred & why?

55 | P a g e Q16 List two discriminations between conventional tube and microwave tube. Q17 What do you understand by self-consistent modes? Q18 What is repeller protection & why is it required? Q19 What is the need of slow wave structure in TWT? Q20 Justify the names-control grid, screen grid, suppressor grid. Q21 what is transit time? Why it becomes a limiting factor at lug her frequencies? Q22 Discuss different types of vacuum tubes in lieu of their strengths and weakness. Q23 What can be the possible solutions to the limitations of conventional tubes at highfrequencies? Which one is the best? Q24 Elaborate the principle of working of Klystron. Q25 Why are multicavity klystron and reflex klystron used for entirely differentapplication? Q26 A two cavity klystron amplifier has the following parameters:V0=1000V, R0=40Kohm, I0=25mA, Freq=3GHz,Gap-spacing (d) =1mm, cavities-spacing=4cm, Effective shunt impedance, excludingbeam loading=30K ohm. a) Find the input gap voltage to give maximum voltageV2. b) Find the voltage gain and efficiency of the amplifier neglecting the beam loading. Q27 Why a microwave is called” Microwave”? Q28 What is the frequency range of microwave? What limits the frequency ofmicrowaves? Q29 Write down the different bands in microwave range along with correspondingfrequencies. Q30 Enlist the advantages of microwave frequencies over lower frequency waves. Q31 Make a list of important applications and the corresponding characteristics ofmicrowave. Q32 In which case the wavelength of the propagating m icrowave is greater, when it ismoving through a medium having dielectric constant=2.0 or when moving through air?Calculate the difference of wavelength.

56 | P a g e Q33 If a m icrowave having frequency 10GHz is moving out with speed of light, calculatethecorresponding wavelength. Q34 Write a brief history of development of microwave technology. Q36 What is frequency pulling in case of magnetrons? Q37 List various methods of beam focusing in TWT’S Q38 What is Velocity Modulation? Q39 Describe the excitation of cavities. Q40 What is microwave transition? Q41 Ordinary low frequency circuit analysis is not adequate to describe the electricalphenomenon-taking place at microwave frequencies, why? Q42 Discuss the problem of transit tim e effect in tubes at microwave frequencies? Q43 Why are semiconductors preferred over vacuum tubes in most applications? Q44 Derive an expression for maximum possible theoretical efficiency of a two cavityklystron. Q45 Explain the significance of Hull voltage in a magnetron. Q46 Explain the principle of working of Travelling wave tube. Q47 Find out the expression for efficiency of two cavity Klystron amplifier. Q48 Explain with neat diagram s the following in a Magnetron: a) Resonant Modes and their separation b) Mechanism of Oscillation. Q49 What do you understand by current modulation Q50 In what type of applications reflex klystron is preferred & why? Q51 List at least two discriminations between Klystron & TWT’s. Q52 Discuss problem of inter electrode capacitance & lead inductance of wavefrequencies.

57 | P a g e Q53 Discuss principle of TWT along with neat sketch? Q54 Derive an expression for maximum possible theoretical efficiency of a reflexKlystron. Q55 List two advantages of using Microwave frequency over low frequency? Q56 Define Transit time effect. Q57 What is the basic difference between TWT and Magnetron? Q58 Why at microwave frequency we talk of traveling waves with associated powersinstead ofvoltages and currents? Q59 What is velocity modulation? How is it different from normal modulation? Explainhowvelocity modulation is utilized in klystron amplifier. Q60 What are slow wave structures? Explain how a helical TWT achieve amplification. MICROWAVE SEMICONDUCTOR DEVICES Q1. State square law of diode. Which diode exhibits this law? Q2. Although PIN diode doesn’t exhibit negative resistance effect yet it is a veryimportantdevice at microwave frequencies. Justify. Q3 Give the construction, working and applications of PIN diode. Q4 Compare the main features of PIN diode and Tunnel diode. Q5 What is Gunn effect? Explain this phenomenon using two-valley theory. Q6 How IMPATT diode is different from all other active diodes? Q7 Explain the operation of IMPATT diode aided by various diagrams. Q8 Explain the basic requirements of tunneling phenomenon in Tunnel diode. Q9 Describe briefly the quenched and delayed modes of oscillation in Gunn diode.Whichmode is more suitable and why? Q10 What is tunneling effect? Explain the construction & working of the device, whichusesthis effect, with the help of sketches. Discuss its V-I characteristics also.

58 | P a g e Q11 Explain several modes of operation of Gunn diode with the keep of sketches. Q12 How negative resistance is achieved in IMPATT? Q13 What’s Gunn effect? Q14 Compare transistors and Transfer Electron Devices (TED’S). Q15 How depletion layer is formed in PIN diode at zero bias? Q16 Give advantages and disadvantages of IMPATT diode. Q17 Write down basic requirements for two-valley theory of Gunn diode. Q18 Why FETs are preferred over Bipolar transistors at highest frequencies? Q19 Describe the construction and operation of a PIN diode as a switch. Q20 Explain the V-I characteristics of a Gunn diode. Q21 Explain the use of PIN diode as a modulator. Q22 Why FET’s are preferred over bipolar transistors at high frequencies? Q23 What is the main advantage of using Gunn diode over IMPATT diode? Q24 Discuss applications of PIN diode as a phase shifter. Q25 Explain Gunn effect using two-valley theory? Also explain several modes ofoperation &applications of Gunn diodes. Q26 What is Avalanche transit time Devices? Q27 List advantages of using Gunn diodes over IMPATT diodes. Q28 What is the basic difference between IMPATT and TRAPATT diodes? Q29 Describe how a tunnel diode can be used as an amplifier and as an oscillator withthenecessary circuit diagrams? Q30 What are the applications of Tunnel diode? Q31 Explain the physical description of read diode and the avalanche multiplicationprocess.

59 | P a g e Q32 Discuss the principle of negative resistances in IMPATT diode. Q33 Explain power output and efficiency of IMPATT diode. Q34 How is TRATATT diode different from IMPATT diode? Q35 What are PIN Diodes? Where are they after used? Why? Q36 Explain the use of Pin diode as a transmit/receive switch. Q37 What are BARITT diodes? Q38 What is the principle of operation of BARITT diode? Q39 How is negative resistance effect of tunnel diode used in oscillators? Q40 What do you understand by mode jumping in a magnetron? Q41 Differentiate between a strapped and unstrapped magnetron. Q42 Explain frequency pushing and pulling in context of magnetron. Q43 Explain domain formation in Gunn effect devices. Q44 What are the various frequency modes in which Gunn effect oscillator can be madetooscillate? Explain each mode in detail. Q45 Which microwave diode is suitable at low frequencies and why? Q46 What happens to the perform ance of PIN diode above 100 MHz? MICROWAVE MEASUREMENTS AND COMPONENTS Q1 Describe briefly the equipment to measure impedance using slotted line. Q2 What are non-reciprocal phase shifters? How do they differ from reciprocal phaseshifters? Q3 What is a directional coupler? Give the construction of 2-hole directional coupler. Q4. Give the relationship between reflection coefficient and VSWR. Q5. What are the values of reflection coefficient and VSWR in the following cases? ii) Termination is perfectly matched

60 | P a g e iii) Termination is a short circuit iv) Termination is an open circuit Q6. What are ferrites? Q7 What is Faradays rotation? Give the construction and working of devices based onthisphenomenon. Q8 What are the various methods of impedance matching? Q9 Why is hybrid Tee also called magic Tee? Q10 Why is it named magic tee also? Give construction and working in detail. Q11 Why are resonators of irregular shape? Q12 Write the principle of attenuator. Q13 Differentiate reciprocal & nonreciprocal phase shifter. Q14 What is a phase shifter? Explain its construction and principle of operation. Q15 Differentiate E-plane Tee & H-plane Tee. Q16 Give principle of working of resonator. Q17 Differentiate Transmission line from wave-guides. Q18 What is Smith chart? What is its application? Q19 A (200+j75) Ohm load is to be matched to a 300 ohm line to give SWR=1.Calculate thereactance of the stub and the characteristic impedance of the quarter wave transformer,both connected to the load. Q20 Calculate the length of a short-circuited line required to tune out the susceptance ofa loadwhose Y=(0.004-j0.002) S, placed on an air-dielectric transmission line of characteristicadmittance Y=00.0033S,at a frequency of 150 MHz. Q21 A load ZL=(100-j50) ohm is connected to a line whose Z0=75ohm.Calculate a) The point nearest to the load, at which a quarter wave transformer may be insertedto provide correct matching.

61 | P a g e b) The ZO of the transmission line to be used for the transform er. Q22 A series com bination having an impedances = (450+j600) ohm at 10 MHz isconnected toa 300ohm line. Calculate the position and length of a short-circuited stub designed tomatch this load to the line. Q23 A quarter wave transformer is connected directly to a 50ohm load, to match thisload to atransmission line who’s Z0=75ohm.What must be the characteristic impedance of thematching transformer? Q24 Calculate the length of a piece of 50ohm open-circuited line if its input admittanceto bej80x10-3 S. Q25 With the aid of a smith chart, calculate the position and length of a short-circuitedstubmatching a (180+j120) ohm load to a 300ohm transmission line. Assuming that the loadimpedance remains constant, find the SWR on the mainline when the frequency is (a)increased by 10% (b) doubled. Q26 What is Directional coupler? Give construction of 2-hole directional coupler. Q27 The input power in a two hole directional coupler is 1mW. The coupler has acouplingfactor of 15 db and a directivity of 30 db. Calculate the power in all the ports. Q28 A symmetric directional coupler with infinite directivity and a forward attenuation of20dbis used to monitor the power delivered to a load. Bolometer 1 introduces a VSWR of2onarm 4and bolometer 2 is matched to arm3. If bolometer1 reads 8m wandbolometer2reads2mW, find (a) the amount of power dissipated in ZL (B) VSWR on arm 2. Q29 List the properties of ferrites that m ake them useful in construction of isolator’s andcirculators. Q30 Why TEM waves cannot be propagated in wave-guides? Q31 Why rectangular waveguides are preferred over circular waveguides in someapplications? Q32 what is magic Tee and why E-H plane is named as magic Tee? Q33 Calculate the ratio of crossection of circular waveguide to that of a rectangular oneif eachis to have same cutoff wavelength for its dominant mode. Q34 Discuss the behavior of ferrites in isolators and circulators.

62 | P a g e Q35 Explain the working of H-plane Tee. Q36 Explain the parameters of Smith Chart. Q37 Explain Double stub matching. Q38 Explain the principle of working of probes and loops. Q39 A 5 dB waveguide attenuator is specified as having VSWR of 1.4. Assuming that itisreciprocal, calculate the scattering parameters. Q40 Define coupling factor& Directivity in case of a directional coupler. Q41 Explain the principle of working of a Rectangular waveguide resonator. Q42 Explain the principle of working of the following: (a) Microwave Switch (b) Microwave Phase Shifter. Q43 Calculate the coupling factor and transmission factor of a 30 dB directional coupler. Q44 List various Electronic & mechanical techniques used for measurements atmicrowavefrequencies? Q45 Why TEM waves cannot be propagated in wave-guides? Q46 List various methods that are used to carry out measurement of Low. Medium &highmicrowave power. Q47 What is the main use of coupling probes & coupling loops in wave-guides? Q48 Calculate ratio of cross-section of circular wave-guides to that of rectangular one ofeachis to have same cut off wavelength for its dominant mode? Q49 What is VSWR & reflection Coefficient? Discuss the measurement of low, medium&high VSWR? Q50 Define Faraday’s rotation and also tell any device based on faraday’s rotation. Q51 What is a Rat-race junction?

63 | P a g e Q52 Explain how impedance can be measured using slotted line method. Q53 Discuss methods for measurement of low and high microwave power. Q54 Compare practical advantages and disadvantages of circular wave-guides withthose ofrectangular wave-guides. Q55 What are cavity resonators? What applications do they have? Why do theynormally haveodd shapes? Q56 Write notes on the following: a) Probes and loops b) Circulators and Isolators. Q57 Discuss the quality factor& cavity resonators.

64 | P a g e Q58 Discuss microwave bends, twists and corners. Q59 What is matched load? Q60 What is an E-Plane Tee? Q61 Explain hybrid ring. Q62 Why are attenuators needed? Why they are not a trivial part of the test setup? Q63 Differentiate b/w fixed and variable attenuators. Q64 Discuss insertion loss and attenuation measurement. Q65 Show that theoretical efficiency of reflex Klystron is 27.78%. Q66 What is a BWO? Explain its perform ance characteristics. Q67 What are the applications of BWO? Q68 Explain the function of magic Tee as a duplexer. Q69 Explain the function of magic Tee as a mixer. Q70 Differentiate between primary and secondary waveguides. Q71 Explain the following terms in context of directional couplers: a) Coupling factor b) Directivity c) Isolation DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

65 | P a g e 1. Give the significance of Micro strip line and strip line transmission line. How they are different from coplanner wave guide.2. Find the guided wavelength for standard X band wave guide at 10 GHz assuming dominant mode. 3. Given the spacing between the plates 5 cm Calculate the phase velocity if the signal frequency is 1.6 times the cut-4. Distinguish between TE, TM, TEM modes. Derive expressions for TE waves between parallel plates. i) Define Vp, Vg and Derive the relation foii) Derive the expression for attenuation in parallel plate wave guide in dominant mode5. The coupling factor and isolation of a lossless, symmetric directional coupler are 8 dB and 20 dB respectively. Determinedetermine the directivity of the device?6. A two port network has the scattering matrix show belowuse signal flow graph to determine following things.1. What is the return loss at port2. If port-2 is terminated with a short circuit, what is the return loss seen at port Course Name: Microwave TechniquesCourse Code:TECFaculty : Mr. Tej RajUnit/Title: 1/Introduction to Microwave transmission Line Give the significance of Micro strip line and strip line transmission line. How they are different from coplanner wave guide. Find the guided wavelength for standard X band wave guide at 10 GHz assuming dominant spacing between the plates 5 cm Calculate the phase velocity if the signal -off value. 4. Distinguish between TE, TM, TEM modes. Derive expressions for TE waves between Define Vp, Vg and Derive the relation for velocities of propagation in parallel plates.Derive the expression for attenuation in parallel plate wave guide in dominant modeThe coupling factor and isolation of a lossless, symmetric directional coupler are 8 dB and 20 dB respectively. Determine the scattering matrix of the directional coupler. Also determine the directivity of the device? 6. A two port network has the scattering matrix show below use signal flow graph to determine following things. What is the return loss at port-1 when other port i terminated by matched load? 2 is terminated with a short circuit, what is the return loss seen at portASSIGNMENT SHEET Course Name: Microwave Techniques Assignment No. 1Course Code:TEC-601 Faculty : Mr. Tej Raj Branch: ECEIntroduction to Microwave transmission Line Date of Issue:Give the significance of Micro strip line and strip line transmission line. How they Find the guided wavelength for standard X band wave guide at 10 GHz assuming dominant spacing between the plates 5 cm Calculate the phase velocity if the signal 4. Distinguish between TE, TM, TEM modes. Derive expressions for TE waves between r velocities of propagation in parallel plates. Derive the expression for attenuation in parallel plate wave guide in dominant mode The coupling factor and isolation of a lossless, symmetric directional coupler are 8 dB and the scattering matrix of the directional coupler. Also port i terminated by matched load? 2 is terminated with a short circuit, what is the return loss seen at port-1? Assignment No. 1 Branch: ECE Semester: VI Date of Issue: Date of Submission:

66 | P a g e

67 | P a g e 1) Why TEM wave cannot propagate in a rectangular wave guide, A hallow rectangular wave guide has dimensions 4cm x 2cm Calculate guided wavelength, phase velocity, wave impedance if frequency of signal is 10 GHz. 2) Derive the relation between λg, λc, and λ0 for rectangular waveguide. How λg can be measured in lab explain with bench set up diagram. 3) What are applications of cavity resonator, Derive the expression for phase velocity in a rectangular waveguide and sketch the variation with frequency. 4) Evaluate the ratio of the area of a circular waveguide to that of a rectangular one if both are to have same cut-off frequency for dominant mode. 5) Explain the boundary condition for TE mode. How they are different from the TM mode DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Microwave Techniques Assignment No. 2 Course Code: TEC-601 Faculty : Mr. Tej Raj Branch: ECE Semester: VI Unit/Title: II/ Waveguide Date of Issue: Date of Submission:

68 | P a g e 1. Write the properties of S-matrix. Prove that scattering matrix of a lossless reciprocal network is unitary. 2. Derive S-matrix for Directional coupler. Explain how perfect directivity can be achieved in multi aperture coupler. 3. Explain the construction of four port circulator and derive its S-matrix. What are the applications of circulator? 4. Write down the S matrices of the following microwave components.... You may assume they have ideal characteristics. 5. A 30 dB amplifier 6. An isolator with 20dB front to back transmission ratio 7. A perfect 3 port circulator 8. A perfect 4 port dual directional coupler, with coupling strength -30 dB 9. A 2 meter length of 50 ohm coaxial cable at 400MHz, assuming a velocity factor of 2/3 10. 5). For a rectangular waveguide of cross section dimensions 2.3 cm by 1 cm, Determine the cutoff frequencies of the following modes. TE10, TE01, TE11, TE20. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Microwave Techniques Assignment No. 3 Course Code: TEC-601 Faculty : Mr. Tej Raj Branch: ECE Semester: VI Unit/Title: III Microwave Components Date of Issue: Date of Submission:

69 | P a g e 1) Give the significance of the measurement of VSWR and wavelength. 2) How microwave power is measured and describes the all method. 3) What is the limitation of microwave tube over transistor devices? 4) How scattering matrix is different from the two port network parameter. 5) What is electron bunching? How it occur in Klystron? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Microwave Techniques Assignment No. 4 Course Code: TEC-601 Faculty : Mr. Tej Raj Branch: ECE Semester: VI Unit/Title: IV Measurement of Microwave Characterstics Date of Issue: Date of Submission:

70 | P a g e 1) What are the limitations of Conventional tubes at high frequencies? 2) Draw the schematic of Reflex Klystron oscillator and with the help of Applegate diagram explain its working 3) Draw a neat sketch of Backward wave Oscillator and explain its working. Write short notes on working of TWT. 4) Explain the function of Gunn Diode and its applications 5) Write the short notes on PIN diode. Write short notes on IMPATT diode 6) Sketch and explain the characteristics of varactor diode. What are the applications at microwave frequency DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Microwave Techniques Assignment No. 5 Course Code: TEC-601 Faculty : Mr. Tej Raj Branch: ECE Semester: VI Unit/Title: V/ Microwave Devices Date of Issue: Date of Submission:

71 | P a g e TEC-604 DIGITAL COMMUNICATION UNIT 1: ELEMENTS OF DIGITAL COMMUNICATION AND INFORMATION THEORY: Model of a DigitalCommunication, System, Probability Theory, Entropy and Information Rate, Conditional Entropy and Redundancy, Source Coding, Fixed and Variable Length Code Words, Source Coding Theorem, Prefix free code and, Kraft Inequality, Shannon-Fano and Huffman Coding. UNIT 2: DIGITAL BASE BAND TRANSMISSION PCM Coding, DM, DPCM, ADCM, Data Transfer Rate, Line Coding and Its Properties, NRZ & RZ Types, Signalling Format For Unipolar, Polar, Bipolar(AMI) & Manchester Coding Matched Filter Receiver, Derivation of Its Impulse Response and Peak Pulse Signal to noise ratio, ISI, Rectangular, sync & Raised cosine pulse comparison UNIT 3: DIGITAL MODULATION TECHNIQUES Gram-Schmidt Orthogonalization Procedure, Hilbert transform, Types of Digital Modulation, correlation receiver, Waveforms for Amplitude, Frequency and Phase Shift Keying, Method of Generation and Detection of Coherent & Non-Coherent Binary ASK, FSK & PSK & PSD derivation for Coherent & Non-Coherent Binary ASK, FSK & PSK. Differential Phase Shift Keying, bit error rate comparison of Digital modulation techniques UNIT 4: ADVANCEDMODULATION TECHNIQUES Introduction to M-ary modulation techniques 16 PSK, QPSK , QAM , Continuous phase shift keying , MSK, GMSK. Direct sequence spread spectrum, processing gain Frequency hop Spreadspectrum. UNIT 5: ERROR CONTROL CODING Error Free Communication Over a Noise Channel, Hamming code, Relation Between Minimum Distance and Minimum Distance Error Correcting & detection Capability, Linear Block Codes, Encoding and Syndrome Decoding, Cyclic Codes, , Encoder and Decoder For Cyclic Codes, Convolution Coding & Viterbi decoding, introduction to burst error correction codes SUGGESTEDBOOKS: 1. Haykin, Simon / “Communication Systems” / John Wiley / 5th Ed., 2010. 2. Taub& Schilling / “Principles of Communication Systems” / Tata McGraw-Hill / 3. Prokis J.J / “Digital Communications” / Pearson / 4. Charkrabarti, P. / “Analog Communication Systems” / DhanpatRai& Co.

72 | P a g e SEMESTER/YEAR: 6th/3rd COURSE: Digital Communication S. No. Topic Name 1. Model of a Digital Communication System2. Probability Theory 3. Entropy and Information Rate4. Conditional Entropy and Redundancy5. Source Coding, Fixed and Variable Length Code Words 6. Source Coding Theorem 7. Prefix free code and, Kraft Inequality8. Shannon-Fano and Huffman Coding.9. PCM Coding 10. DM 11. DPCM ,ADCM 12 Data Transfer Rate, Line Coding and Its PropertiesRZ & RZNTypes 13. Signaling Format For Unipolar, Polar DBIT DEHRADUN LESSON PLAN DEPARTMENT: ECE Digital Communication CODE: TEC-604Reference/ Text Book/ Web (R/T/W) No. Of Lectures Model of a Digital Communication System T1,R1 1 T1,R1 2 Entropy and Information Rate T1,T2 1 Conditional Entropy and Redundancy T1,R1 2 Coding, Fixed and Variable Length T1,R1 2 T1,T2 1 Prefix free code and, Kraft Inequality T1,R1 2 Fano and Huffman Coding. T1,R1 3 T1,R1 2 T1,R1 1 T1,R1 2 Data Transfer Rate, Line Coding and Its T1,R1 2 Signaling Format For Unipolar, Polar T1,R1 2 DEPARTMENT: ECE 604 No. Of Lectur Delivery Method Remarks Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk

73 | P a g e 14. Bipolar(AMI) & Manchester Coding T1,T2 2 Chalk & Talk 15. Matched FilterReceiver, Derivation of Its Impulse Response T1,R1 1 Chalk & Talk 16. ISI, Rectangular, sync & Raised cosine pulse comparison. T1,R1 2 Chalk & Talk 17. Gram-Schmidt Orthogonalization Procedure T1,R1 1 Chalk & Talk 18. Hilbert transform, Types of Digital Modulation, T1,R1 1 Chalk & Talk 19. correlation receiver, Waveforms for ASK,PSK AND FSK T2,R1 1 Chalk & Talk 20. Method ofGeneration and Detection of Coherent & Non-Coherent Binary ASK T2 2 Chalk & Talk 21. Method ofGeneration and Detection of Coherent & Non-Coherent Binary PSK T2,R1 2 Chalk & Talk 22. Method ofGeneration and Detection of Coherent & Non-Coherent Binary FSK T2 2 Chalk & Talk 23. PSD derivationfor Coherent & Non-Coherent Binary ASK, FSK & PSK. T2,R1 2 Chalk & Talk 24. Differential Phase Shift Keying T2 1 Chalk & Talk 25. Bit errorrate comparison of Digital modulation techniques. T2,R1 2 Chalk & Talk 26. M-ary modulation techniques 16 PSK, QPSK T2 2 Chalk & Talk 27. QAM, Continuous phase shiftkeying T1 2 Chalk & Talk 28. MSK, GMSK 2 Chalk & Talk 29. Direct sequence spread spectrum, processing gain Frequency hop Spreadspectrum. T1,T2 3 Chalk & Talk

74 | P a g e 30. Error Free Communication Over a Noise Channel T2 1 Chalk & Talk 31. Hamming code,Relation Between MinimumDistance and Minimum Distance Error Correcting & detection Capability T1 2 Chalk & Talk 32. Linear Block Codes T1,R1 2 Chalk & Talk 33. Encoding and Syndrome Decoding T2 1 Chalk & Talk 34. Cyclic Codes, , Encoder and Decoder For Cyclic Codes, T2 2 Chalk & Talk 35. Convolution Coding & Viterbi decoding T2 2 Chalk & Talk 36. introduction to burst error correction codes. T2 1 Chalk & Talk Total Lectures: 62 TEXT BOOKS: [T1] Haykin, Simon / “Communication Systems” / John Wiley / 5th Ed., 2010. [T2] Communication System, B P Lathi, BSP, Hyderabad. REFERENCE BOOKS: [R1] Prokis J.J / “Digital Communications” / Pearson / DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

75 | P a g e 1. A ternary source produces alphabets A,B& C with probabilities PA=PB=p & Pc. Which one of the following gives the correct values for the maximum value of the entropy of the source & the corresponding value of p & the range of p? 2. During transmission over a communication channel, bits errors occur independently with probability p. If a block of n bits is transmitted, then what is the probability of at most one bit error in this case? 3. A video transmission system transmits 625 picture frames per second. Each frame consists of 400 X 400 pixel grid with 64 intensity levels per pixel. What is the data rate of the system? 4. In a communication system, each message (1 or 0) is transmitted three times in order to reduce the probability of error. The detection is based on the majority rule at the receiver. What will be the probability of error for this communication system If Pe is the probability of bit error? 5. Consider a source with three messages having symbol probabilities 0.5, 0.4 & 0.1 :- (i) obtain Shannon-Fano code & calculate its efficiency. (ii) Repeat (i) for second order extension code & determine its efficiency. ASSIGNMENT SHEET Course Name: Digital Communication Assignment No. 1 Course Code:TEC-604 Faculty : Mr. Arjun Singh Branch: ECE Semester: VI Unit/Title: 1/ Elements of Digital Communication and Information Theory Date of Issue: Date of Submission:

76 | P a g e 1. If Eb, the energy per bit of a binary digital signal is 10-5 watt-sec & the one –sided power spectral density of the white noise, NO=10-6 W/Hz, then what will be the output SNR of the matched filter? 2. The input to a linear Delta modulator having a step size = 0.628 is a sine wave with frequency fm& peak amplitude Em. If the sampling frequency fs= 40 KHz, then what will be the combination of the sine wave frequency & peak amplitude, where slope overload will take place? 3. A voice grade telephone circuit has to transmit audio signal in digital signal form. Suggest & explain the scheme for the same with suitable block diagram. Calculate the data rate if ADC of 12 bits is used in your scheme. 4. For a bit-rate of 8 Kbps, what will be the best possible value of the transmitted frequencies in a coherent binary FSK system? 5. In a digital communication system employing FSK, the 0 & I bits are represented by sine waves of 10 KHz & 25 KHz respectively. Find out the bit interval for which these waveforms will be orthogonal? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Digital Communication Assignment No. 2 Course Code:TEC-604 Faculty : Mr. Arjun Singh Branch: ECE Semester: VI Unit/Title: II & III/ Digital Base Band Transmission & Digital Modulation Techniques Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

77 | P a g e 1. In BPSK signal detector, the local oscillator has a fixed phase error of 200. By what factor does this phase error deteriorate the SNR at the output? 2. During transmission over a certain binary communication channel, bit errors occur independently with probability p. What will be the probability of AT MOST one bit in error in a block of n bits? 3. Suppose that we wish to achieve an error rate performance of 10-6 or less with an uncoded DS spread spectrum system. The available bandwidth expansion factor is W/R=1000. Find out the jamming margin. 4. A DS binary PSK spread spectrum has a processing gain of 500. What is the interference margin against continuous-tone interference if the desired error probability is 10-5? 5. Prove that if the sum of two error patterns e1 & e2 is a valid code word cj, then each error pattern has the same syndrome. ASSIGNMENT SHEET Course Name: Digital Communication Assignment No. 3 Course Code:TEC-604 Faculty : Mr. Arjun Singh Branch: ECE Semester: VI Unit/Title: II & III/ Digital Base Band Transmission & Digital Modulation Techniques Date of Issue: Date of Submission:

78 | P a g e QUESTION BANK DIGITAL COMM 1-Define Information? what are the various information resources? 2-Explain information content of a symbol? what are the properties of I(xi)? 3-Calculate the amount of information if binary digits (binits) occur with equally li4-kelihood in a binary PCM system? 4-If there are M equally likely and independent symbols ,then prove that amount ofinformation carried by each symbol will be I(xi) = N bits. 5-If I(xi) is the information carried by symbols (x1) and I(x2) is the inform ation carried bymessage x2.then prove that the am ount of information carried compositely due to x1 & x2 is I(x1,x2) = I(x1)+ I(x2). 6-What do you mean by entropy? What are the assumptions related to it? Express it inmathematical form. 7-Define :- 1)entropy for binary source. 2) lower& upper bounds on entropy H(x).Define information rate? Verify the following expression:- I(xi,xj)= I(xi)+I(xj) . if xi &xjare independent. 8-A DMS has four symbols x1,x2,x3,x4 with probabilitiesp(xi)=0.4,p(x3)=0.3,p(x3)=0.2,p(x4)=0.1, calculate H(x) also find the amount ofinformation contained in the messages x1x2x3x4 & x4x3x3x2 & compare with the H(x)obtained earlier? 9-An analog signal is bandlimited to fm Hz and sampled at nyquistrate,the samples arequantized into 4 levels .each level represent one symbol.thus there are 4 symbols .theprobabilities of occurrence of these 4 levels (symbols) are p(x1=p(x4) =1/8 &p(x2)=p(x3)=3/8. obtained information rate of the sources. 10-The probabilities of five possible outcomes of an experiment are given as p(x1)=½,p(x2)=1/4, p(x3)=1/8 ,p(x4)=p(x5)=1/16, determine the entropy and information rate ifthere are 16 outcomes per seconds.

79 | P a g e 11-An analog signal bandlimitted to 10 khz is quantized in 8 levels of pcm system with probabilities of ¼,1/5,1/5 1/10,1/10,1/20,1/20,1/20 respectively, find the entropy and therate of information? 12-Express channel matrix of DMC , explain the types of channels in DMC. 13-Define conditional and joint entropies, with their mathematical representation? 14-What do you mean by mutual information define its properties? 15-What do you mean by channel capacity per symbol and channel capacity per secondalso explain capacities of special channels. 16-Define: 1)AWGN 2)uncertainity in the transmission process.3) code efficiency 4)code redundancy. 17-Explain source coding (definition) code word lengthaverage code word lengthkraft inequalityShannon-fano algorithm. UNIT-2 &3: 1- Define companding .What is A law companding and µ law companding? 2-. What is differential pulse code modulation? Explain. 3- What isPulse Code Modulation? . whatare the most comm on methods of pulsemodulation. 4-With a near block diagram explain about delta modulation? 5. With a neat block diagram explain about DPCM? 6. Explain with a neat diagram, the different blocks of adaptive differential pulse codemodulation. 7.With a block diagram explain about Adaptive sub band coding. 8.Write short notes on : a) Quantization noise b) Digital multiplexers. 9. Derive an expressionfor SNR in delta modulation. 10. Compare PCM, DPCM and DM.

80 | P a g e 11-Draw the following data format for the given bit stream-1100010 a) Polar NRZ b)Unipolar RZ c) Mnchester d) 12-How TDMA system is used in satellite communication? 13-Distinguish between DPSK, BPSK and QPSK 14-Compare of Various Digital Modulation Techniques. UNIT-4 1-What is the difference between analog and digital communication? 2-What are the different digital modulation techniques.? 3-What do you understand by waveform coding .? 4-Explain with diagram generation of coherent ASK,FSK and PSK. 5-Explain the generation of non coherent ASK,FSK and PSK. 6-Compare different types of digital techniques. 7-Draw and explain electronic commutator. 8-What is bit interleaving in digital communication? 9-Explain T1 carrier system with neat diagram. 10-What do you understand by synchronization and signaling of T1 system. 11-What is frequency shift keying ? Explain in detail about FSK transmitter andreceiver. 12). With a neat schematic diagram, explain the Balanced ring modulator of BPSK. 13) What is TDM and PCM HIERARCHY? UNIT 5 1. Draw the code tree of a Convolutional code of code rate r=1/2 and Constraintlength of K=3 starting from the state table and state diagram for an encoderwhich is commonly used.

81 | P a g e 2. Draw the trellis diagram of a Convolutional code of code rate r=1/2 andConstraint length of K=3 starting from the state table and state diagram for anencoder which is comm only used. 3. Decode the given sequence 11 01 01 10 01 of a convolutional code with a coderate of r=1/2 and constraint length K=3, using viterbi decoding algorithm. 4. Explain the construction of Block Code and how the error syndrome is calculated. 5. Explain in detail about Orthogonal Codes, Biorthogonal Codes andTransorthogonal Codes. 6. Define the following terms: a. code word b. block length c. code rate d. channel data rate e. code vectors f. hamming distance 7. What are hamming codes? Write the properties of hamming codes. 8. Explain the advantages of coding in communication system. 9. What is the use of syndromes? Explain syndrome decoding. 10. Write the advantages and disadvantages of convolution codes. 11. Compare linear block codes, cyclic code and convolution codes by giving theiradvantages and disadvantages. 12. What are code tree, code trellis and state diagram s for convolution encoders? 13. Explain about error detection and correction capabilities of hamming codes. 14. Explain FEC and ARQ systems of error control. 15. Explain how generator and parity matrices are obtained for cyclic codes.

82 | P a g e THU-608 PRINCIPLES OF MANAGEMENT UNIT 1 INTRODUCTION TO MANAGEMENT: Theories of management: Traditional behavioral,contingency and systems approach. Organization as a system. UNIT 2 MANAGEMENT INFORMATION: Interaction with external environment. Managerial decisionmaking and MIS. UNIT 3 PLANNING APPROACH TO ORGANIZATIONAL ANALYSIS: design of organization structure; jobdesign and enrichment; job evaluation and merit rating. UNIT 4 MOTIVATION AND PRODUCTIVITY: Theories of motivation, leadership styles and managerial grid.Co-ordination, monitoring and control in organizations. Techniques of control. Japanese management techniques. SUGGESTED BOOKS 1. Peter Drucker, Harper and Row: The Practice of Management. 2. Schemerhorn” introduction to Management” 10thedition,John Wiley (India). 3. Staner: Management, PHI Learning. 4. Daft: Principles of Management, Cengage Learning.

83 | P a g e SEMESTER/YEAR: 6th/3rd COURSE: PRINCIPLES OF MANAGEMENT S. No. Topic Name 1. INTRODUCTION TO MANAGEMENT: Theories of management: Traditional behavioral contingency and systems approach Organization as a system. 2 MANAGEMENT INFORMATION: Interaction with external environment Managerial decision,making MIS 3 PLANNING APPROACH TO ORGANIZATIONAL ANALYSIS: design of organization structure; DBIT DEHRADUN LESSON PLAN DEPARTMENT: ECE PRINCIPLES OF MANAGEMENT CODE: THUReference/ Text Book/ Web (R/T/W) No. Of Lectures Delivery Method INTRODUCTION TO T1,R1 2 Chalk & TalkTheories of management: Traditional T1,R1 2 Chalk & Talkcontingency and systems approach T1,R1 2 Chalk & Talk T1,R1 2 Chalk & TalkMANAGEMENT INFORMATION: T1,R1 2 Chalk & TalkInteraction with external environment T1,R1 2 Chalk & TalkManagerial decision,making T1,R1 2 Chalk & TalkT1,R1 2 Chalk & TalkPLANNING APPROACH TO ORGANIZATIONAL ANALYSIS: T1,R1 2 Chalk & Talkdesign of organization structure; T1,R1 2 Chalk & TalkDEPARTMENT: ECE THU-601 Delivery Remarks Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk

84 | P a g e job design and enrichment T1,R1 2 Chalk & Talk job evaluation T1,R1 1 Chalk & Talk Merit rating. T1,R1 2 Chalk & Talk 4.. MOTIVATION AND PRODUCTIVITY: T1,R1 2 Chalk & Talk Theories of motivation T1,R1 2 Chalk & Talk leadership styles T1,R1 1 Chalk & Talk managerial grid T1,R1 2 Chalk & Talk Co-ordination T1,R1 1 Chalk & Talk Monitoring T1,R1 1 Chalk & Talk control in organizations T1 1 Chalk & Talk Techniques of control T1,R1 2 Chalk & Talk Japanese management techniques. T1 1 Chalk & Talk Total Lectures: 40 TEXT BOOKS: [T1] Himanshu Aggarwal REFERENCE BOOKS: [R1] L M Parsad

85 | P a g e Q.1 what is Management and why is it important to learn about management? Q.2 List the principles of scientific management. Q.3 How does the job of a top manger differ from those of the several levels of middle management? Q.4 What are the 14 principles given by HennryFayol related to modern management. Q.5 What are the essential skills of a manager? Q.6 What are the functions of managers? Explain the roles of managers as suggest by Henry Mintzberg. Q.7 What do you understand by bureaucracy? Discuss the characteristics of Max weber bureaucratic model. Q.8 The Neo Classical Theory is human Oriented. Discuss. State the characteristics of Neo Classical Theory. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 1 Course Code:THU-601 Faculty :Ms. Manvi Chopra Branch: All Branches Semester: VI Unit/Title: 1/ Introduction of Management Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

86 | P a g e Q.1 Define and describe business process and their relationship to information systems. Q.2 What are business processes? What role do they play in organizations? How are they enhanced by information systems? Q.3 Explain the major constraints in operating the MIS. Q.4 Explain the role of organizations environment on the MIS and business processes? Q.5 What is Decision Support System? Briefly explain the characteristics of Decision Support System. Q.6 What do you understand by environmental analysis? Discuss the procedure of environmental analysis. Q.7 Explain the planning for implementation step in MIS. Q.8 Define an information system from both a technical and a business perspective. Q.1 Explain the nature and significance of planning? ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 2 Course Code:THU-601 Faculty :Ms. Manvi Chopra Branch: All Branches Semester: VI Unit/Title: 2/ Management information system Date of Issue: Date of Submission:

87 | P a g e Q.2 Explain the roles of planning function? Q.3 What is Job Evaluation Process Chart. Q.4 Define Performance Appraisal. What are its salient features? What are its merits &demerits. Q.5 What are the various methods of job Appraisal? Q.6 What is organizational analysis? Explain the models of organizational analysis? Q.7 Discuss the planning approach to organizational analysis? Q.8 What is merit rating and discuss its limitations. DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 3 Course Code:THU-601 Faculty :Ms. Manvi Chopra Branch: All Branches Semester: VI Unit/Title: 3/ Planning Approach to organization Analysis Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

88 | P a g e 1. Name the steps involved in motivation process. 2. What is Motivation and how is Moslow’s hierarchy of needs theory a theory of motivation? 3. What are McGregor’s Theory X and Theory Y assumptions? 4. What are three needs McClelland proposed which are present in work situation? 5. What is the relationship between planning and controlling in Organization control process? 6. “ Leadership is a driving force which gets things done by others.” Examine and comment. 7. “Good Leadership is an integral part of effectiveness direction.” Discuss, bringing out clearly the qualities of an effective leader. 8. Define Leadership. Explain the various Styles and theories of leadership. ASSIGNMENT SHEET Course Name: Principle of Management Assignment No. 4 Course Code:THU-601 Faculty :Ms. Manvi Chopra Branch: All Branches Semester: VI Unit/Title: 4/ Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

89 | P a g e CASE -1 “Managing by objective is nothing new here” , said commissioner Gaurav of the metropolis Police Department. “ We have always had important objectives toward which every one in my department strives. Our job is to maintain law and order, firmly but fairly; to protect human lives and property; and to be the conscience and spirit of the general welfare of the millions of people who call our city home. Everyone in this department knows these objectives. Every man and woman knows that he or she must work toward them and that, if they do not, they will be replaced. I recognize that in a manufacturing concern you can measure objectives by profits, sales, costs and product output. We can’t, of course, do that, for we are service operation. But this does not mean that we are not managing by objectives. Ask anyone in my department? Questions 1. (a) Is commissioner Gaurav engaging in managing by objectives? What, if anything, is missing? (b) What would you suggest the commissioner do? CASE - 2 TUTORIAL SHEET Course Name: Principles of Management Tutorial Sheet No. 1 Course Code:THU-608 Faculty :Ms. Manvi Chopra Branch: CSE Semester: VI Unit/Title: Date of Discussion:

90 | P a g e The personnel Manager of Bushan steels, an engineering unit based at Kolkata has been banging the executive conference table of the company for some months asserting that the true function of Management is to take care of the needs of the staff and let the staff take care of the goals of the organization. The marketing Manager has, on the other hand, been expressing the view that the real function of management is to take care of the market and staff must fall in line with the objectives, plans and priorities of the company. Question Which of these views is correct and why? QUESTION BANK DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name:Principles of Management Tutorial Sheet No. 2 Course Code:THU-608 Faculty :Ms. Manvi Chopra Branch: CSE Semester: VI Unit/Title: Date of Discussion:

91 | P a g e Unit - 1 1) Define Management. 2) Is management – an art or science? 3) Give some features of management. 4) What are the essential skills of a manager? 5) Define scientific management. 6) List the principles of scientific management. 8) State the contributions of Fayol towards management. 9) What do you mean by ‘Scalar chain’? 10) What do you mean by ‘Esprit de corps’? 11) What are the various levels of management? 12) What are the roles played by a manager? 13) What are the functions of management? 14) What are the classifications of business organization?. 15) Trace the evolution of management with reference to the contributions made by management thinkers. 16) What is the role of scientific management in the modern era? 17) Explain the contributions of F.W.Taylor to Management. 18) Explain the contributions of Henri Fayol. 19) Explain the contributions of Abraham Maslow and McGregor. 20) Discuss the nature, purpose, merits and demerits of management. 21) Differentiate between Management and Administration with suitable examples. 22 )Discuss the merits and demerits of various types of organization. 23) Explain the recent developments in modern management theory. Unit-2 &3

92 | P a g e 1) Trace the steps involved in the decision-making process. 2) Explain in detail the classification of decisions. 3) Discuss the various quantitative techniques for decision-making 1) Define ‘Planning’. 2) What are the types of planning? . 3) Define the ‘mission’ and ‘vision’ of an organization? 4) What do you mean by MBO? 5) What are policies? 6) What are the various types of plans? 7) Define the term ‘Strategy’. 8) State the features of Policies. . 9) What do you understand by the term ‘Planning premises’? 10) What are the main factors to consider for implementation of a strategy? 11) Differentiate objectives and goals. 12) Distinguish between strategy and tactics. 13) State the hierarchy of objectives. 14) Differentiate policies and procedures. 15) What are the different types of policies? 16) What do you mean by SWOT ANALYSIS? 17) State the levels of strategy. 18) What are the main objectives of a project? 19) Mention the features of MBO. 20) What is Forecasting? 21) Define planning. Discuss the steps involved in planning. 22) “Planning is all pervasive.”- Discuss with reference to its nature, merits and demerits.

93 | P a g e 23) Explain the various characteristics identified in planning. 24) Discuss in detail the planning of premises. 25) What are objectives? State the characteristic features and requirements of a sound objective. 26) Discuss in detail the features and process of MBO. (or) Discuss the contributions of Peter.F.Drucker to management. 27) Differentiate between Objectives & Goals with examples. 28) Differentiate between Strategy & Policy. 29) Discuss about the effective implementation of a strategy. 30) Explain in detail the strategic planning process. 31) Discuss the steps involved in formulation of a Policy. 32) Classify and explain policies. Give the requisites of a sound. 13) Discuss the merits and demerits of different types of plans 35) Discuss the different types of planning. 36) What is job design? 37) What are the benefits of specialization? 38) What are the limitations of specialization? 39) What is job rotation? 40) What is job enlargement? 41) What is job enrichment?

94 | P a g e Unit-4 1) Define Motivation. 2) Name the steps involved in motivation process. 3) What are the types of motivation? 4) What are the different Motivational theories? 5) List out the basic needs in hierarchy. 6) Who is a leader? 7) Define Leadership. 8) List the few leadership theories. 9) State house path goal approach. 10) Name the various leadership styles. 11) Explain the importance of leadership. 12) Explain the motivation process. 13) Explain the Maslow’s need hierarchy theory. 14) Explain the special motivational techniques. 15) Explain the different styles of leadership. 16) What are the four basic ingredients of leadership skill? 17) Explain the McClelland’s needs theory. 18) Explain the special motivational techniques. 19) Explain the trait approaches to leadership theories. 20) What is Control? 21) Define control. 22) What are the characteristics of control? 23) Why need of control in the organization?

95 | P a g e 24) What are the importances of controlling? 25) What are the disadvantages of control? 26) What are the interrelationship between planning and control? 27) Give some critical point standards of control 28) What are the types of control? 29) What is feedback control? 30) What is concurrent control? 31) What is feed forward control? 32) List the differences between feedback control and feed forward 33) What are the requirements for effective control? 34) Explain briefly the control techniques. 35) Discuss the control process and types of control. 36) What are the characteristics of control? Explain its need for management. 37) Explain the characteristic of an ideal control system. 38) Define control. Describe the features of a good control system. 39) What are the various good qualities of efficient controlling system?

96 | P a g e DATA STRUCTURES USING C++ TCS607

UNIT 1 COMPLEXITY ANALYSIS: Time and Space complexity of algorithms, asymptotic analysis, big O and other notations, importance of efficient algorithms, program performance measurement, data structures and algorithms. LINEAR LISTS: Abstract data type, sequential and linked representations, comparison of insertion, deletion and search operations for sequential and linked lists, list and chain classes, exception and iterator classes for lists, doubly linked lists, circular lists, linked lists through simulated pointers, lists in STL, skip lists, applications of lists in bin sort, radix sort, sparse tables. UNIT 2 STACKS AND QUEUES: Abstract data types, sequential and linked implementations, exception handling in classes, representative applications such as parenthesis matching, towers of Hanoi, wire routing in a circuit, finding path in a maze, simulation of queuing systems, equivalence problem. UNIT 3 HASHING: Search efficiency in lists and skip lists, hashing as a search structure, hash table, collision avoidance, linear open addressing, chains, uses of hash tables in text compression, LZW algorithm. UNIT 4 TREES: Binary trees and their properties, terminology, sequential and linked implementations, tree traversal methods and algorithms, heaps as priority queues, heap implementation, insertion and deletion operations, heapsort, heaps in Huffman coding, leftist trees, tournament trees, use of winner trees in mergesort as an external sorting algorithm, bin packing. UNIT 5 GRAPHS: Definition, terminology, directed and undirected graphs, properties, connectivity in graphs, applications, implementation – adjacency matrix and linked adjacency chains, graph traversal – breadth first and depth first, spanning trees. Suggested Books: 6. T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, Introduction to Algorithms, MIT Press, 2001. 7. A. Aho, J. E. Hopcroft and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley, 1974 8. M. T. Goodrich and R. Tamassia, Algorithm Design: Foundations, Analysis and Internet Examples, John Wiley & Sons, 2001.

97 | P a g e DEV BHOOMI INSTITUTE OF SEMESTER/YEAR: 6th /3rd COURSE:Data Structure using C++ S. No. Topic Name1. Time and Space complexity of algorithms2. Asymptotic analysis, Big O and

other notations, 3. Importance of efficient algorithms,4. Program performance measurement5. Data structures and algorithms6. Abstract data type, sequential and linked representations, 7. Comparison of insertion,

deletion and search operations for sequential lists8. Comparison of insertion,

deletion and search operations for linked lists9. List and chain classes 10. Exception

DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN LESSON PLAN DEPARTMENT: ECE Data Structure using C++ CODE: TCS-607 Topic Name Reference/Text Book/Web (R/T/W) No. Of Lectures UNIT-1 Time and Space complexity of algorithms T1,R1 1 Asymptotic analysis, Big O and T1,R1 1

algorithms, T1,T2 1 Program performance measurement T1,R1 1 Data structures and algorithms T1,R1 1 Abstract data type, sequential and linked T1,T2 1 deletion and search operations for sequential lists

T1,R1 2 deletion and search operations for linked lists

T1,R1 1 T1,R1 1 T1,R1 2 TECHNOLOGY, DEHRADUN Delivery Method Remarks Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk Chalk & Talk

98 | P a g e and Iterator classes for lists 11. Doubly linked lists, circular lists, T1,R1 2 Chalk & Talk 12 Linked lists through simulated pointers, T1,R1 1 Chalk & Talk 13. Lists in STL, skip lists, T1,R1 1 Chalk & Talk 14. Applications of lists in bin sort, radix sort, T1,T2 1 Chalk & Talk 15. Sparese tables T1,R1 1 Chalk & Talk UNIT-2 16. Abstract data types, sequential implementations T1,R1 2 Chalk & Talk 17. Linked implementations, T1,R1 1 Chalk & Talk 18. Exception handling in classes T1,R1 2 Chalk & Talk 19. Representative applications such as parenthesis matching, towers of Hanoi,

T2,R1 1 Chalk & Talk 20. Wire routing in a circuit, finding path in a maze T2 1 Chalk & Talk 21. Simulation of queuing systems, equivalence problem

T2,R1 1 Chalk & Talk UNIT-3 22. Search efficiency in lists and skip lists T2 1 Chalk & Talk 23. Hashing as a search structure, hash table T2,R1 1 Chalk & Talk 24. Collision avoidance T2 1 Chalk & Talk 25. Linear open addressing T2,R1 1 Chalk & Talk 26. Uses of hash tables in text compression T2 2 Chalk & Talk 27. LZW algorithm T1 2 Chalk & Talk Unit-4 28. Binary trees and their properties, terminology 1 Chalk & Talk 29. Sequential and linked implementations T1,T2 1 Chalk & Talk

99 | P a g e 30. Tree traversal methods and algorithms T2 1 Chalk & Talk 31. Heaps as priority queues, T1 1 Chalk & Talk 32. Heap implementation, insertion and deletion operations

T1,R1 2 Chalk & Talk 33. Heapsort T1,R1 1 Chalk & Talk 34. Heaps in Huffman coding T1 1 Chalk & Talk 35. Leftist trees, T2 1 Chalk & Talk 36. Tournament trees T2 1 Chalk & Talk 37. Use of winner trees in mergesort as an external sorting algorithm

T1,R1 1 Chalk & Talk 38 Bin packing T1,R1 1 Chalk & Talk UNIT-5 39 Definition, terminology, directed and undirected graphs

T1,R1 1 Chalk & Talk 40 Properties, connectivity in graphs T1 1 Chalk & Talk 41 Applications, implementation – adjacency matrix T2 1 Chalk & Talk 42 Linked adjacency chains T2 1 Chalk & Talk 43 Graph traversal – breadth first T1,R1 1 Chalk & Talk 44 Depth first T1,R1 1 Chalk & Talk 45 Spanning trees. T1 1 Chalk & Talk Total Lectures: 53 TEXT BOOKS: [T1]T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, Introduction to Algorithms, MIT Press,2001.

[T2]A. Aho, J. E. Hopcroft and J. D. Ullman, The Design and Analysis of Computer Algorithms,

Addison-Wesley, 1974

100 | P a g e 1. What do you understand by worst case, average case and best case time complexity of an algorithm?

2. Write an algorithm to concatenate two circularly linked lists pointed by list 1 and list 2 in such a way that circular list pointed by list 2 is appended to the circular list pointed by list 1?

3. How can a polynomial in two variables be represented by a singly linked list? Write an algorithm to add two such polynomials?.

4. Define algorithm and data structure. Give the difference between linear and non-linear data structures with example?

5. Define time complexity. Explain Big oh (O) notation? 6. Write a C++ program to construct and delete elements in a circular queue using linked list?

DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name:Data Structure using C++ Assignment No.1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch:CSE Semester: VI Unit/Title: UNIT-I Date of Issue: Date of Submission:

101 | P a g e 1. What is an ADT? Show the insert and remove operations in/from the Queue ADT during the traversal in a tabular fashion?

2. Write a C++ program to implement stack and its operations, PUSH and POP? 3. Write a complete program in C to implement stack using liked list? 4. What is priority queue? How it is implemented? Take an example to show your implementation? 5. Devise function in C which check for Full and Empty for a circular queue. Also find out the

number of elements in circular queue?

DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name:Data Structure using C++ Assignment No.1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch:CSE Semester: VI Unit/Title: UNIT-II Date of Issue: Date of Submission:

102 | P a g e 1. Write an algorithm for searching an algorithm using linear search method?. 2. Discuss various methods used for resolving hash collisions? 3. Explain linear probing and quadratic probing using a suitable example? 4. What is a hash table, explain its applications? 5. Show the working of Huffman algorithm. with an example. Also write the applications of huffman’s

algorithm? 6. What is the difference between indexing and hashing?

DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name:Data Structure using C++ Assignment No.1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch:CSE Semester: VI Unit/Title: UNIT-III Date of Issue: Date of Submission:

103 | P a g e 1. What is a heap? Explain how an array of integers can be sorted using heap sort method. Given 20, 55, 46, 34, 13, 90, 87, 32 are elements of an array, show the different stages of sorting?

2. Write an algorithm to construct a binaty tree for the input 14, 15, 4, 9, 7, 18, 3, 5, 16, 4, 20, 17, 9 indicating a message for duplicate members? Draw the tree constructed by the above program?

3. Write a short note on external sorting method? How can we use winner trees in mergesort? 4. What do you mean by heap sort? Explain and write analysis of heap sort? 5. Write a recursive procedure which finds the number of nodes in a tree?

DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name:Data Structure using C++ Assignment No.1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch:CSE Semester: VI Unit/Title: UNIT-IV Date of Issue: Date of Submission:

104 | P a g e 1. Write an algorithm to check whether a graph is connected or not? 2. Write an algorithm which counts the number of connected components in a graph? 3. Define adjacency matrix corresponding to a diagraph? 4. Explain spanning tree and draw a spanning tree for the following graph

5. Explain the various graph representation techniques? DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN ASSIGNMENT SHEET Course Name:Data Structure using C++ Assignment No.1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch:CSE Semester: VI Unit/Title: UNIT-V Date of Issue: Date of Submission: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

105 | P a g e Q.1What is a data structure? Explain the characteristics of Data Structure. Q. what do you mean by Asymptotic Notation? Explain its type. Q.3 Explain about the types of linked lists. Write the programs for Linked List (Insertion and Deletion) operations Q4. If you are using C language to implement the heterogeneous linked list, what pointer type will you use? Q5. A two dimensional array TABLE [6] [8] is stored in row major order with base address 351. What is the address of TABLE [3] [4]? TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch: ECE Semester: VI Unit/Title:UNIT-1 Date of Discussion: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

106 | P a g e Q1. Evaluate the following prefix expression " ++ 26 + - 1324" (Similar types can be asked) . Q2. How is it possible to insert different type of elements in stack? Q.3. Which data structure is needed to convert infix notations to post fix notations? Q4. Write an algorithm to evaluate a postfix expression. Execute your algorithm using the following postfix expression as your input : a b + c d +*f . Q5. What are circular queues? Write down routines for inserting and deleting elements from a circular queue implemented using arrays. TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch: ECE Semester: VI Unit/Title:UNIT-2 Date of Discussion: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

107 | P a g e Q.1 Given a set of input representing the nodes of a binary tree, write a non recursive algorithm that must be able to output the three traversal orders. Write an algorithm for checking validity of the input, i.e., the program must know if the input is disjoint, duplicated and has a loop. Q.2 What is a Binary Search Tree (BST)? Make a BST for the following sequence of numbers 45, 36, 76, 23, 89, 115, 98, 39, 41, 56, 69, 48 Traverse the tree in Preorder, Inorder and postorder. Q.3 Two Binary Trees are similar if they are both empty or if they are both nonempty and left and right sub trees are similar. Write an algorithm to determine if two Binary Trees are similar. Q.4 The degree of a node is the number of children it has. Show that in any binary tree, the number of leaves are one more than the number of nodes of degree 2 .Q.5 Taking a suitable example explains how a general tree can be represented as a Binary Tree. TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch: ECE Semester: VI Unit/Title:UNIT-3 Date of Discussion: DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN

108 | P a g e Q.1 Draw the complete undirected graphs on one, two, three, four and five vertices. Prove that the number of edges in an n vertex complete graph is n(n-1)/2. Q.2 Draw the complete undirected graphs on one, two, three, four and five vertices. Prove that the number of edges in an n vertex complete graph is n(n-1)/2. Q.3 What are the different ways of representing a graph? Represent the following graph using those ways. Q.4 What are the different ways of representing a graph? Represent the following graph using those ways. Q.5 Write an algorithm which does depth first search through an un-weighted connected graph. In an un-weighted graph, would breadth first search or depth first search or neither find a shortest path tree from some node? Why? TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch: ECE Semester: VI Unit/Title:UNIT-4 Date of Discussion:

109 | P a g e Q.1Bubble sort algorithm is inefficient because it continues execution even after an array is sorted by performing unnecessary comparisons. Therefore, the number of comparisons in the best and worst cases are the same. Modify the algorithm in such a fashion that it will not make the next pass when the array is already sorted. Q.2 What are B-trees? Construct a B-Tree of order 3 for the following set of Input data: 69, 19, 43, 16, 25, 40, 132, 100, 145, 7, 15, 18. Q.3 Draw the 11 item hash table resulting from hashing the keys: 12, 44, 13, 88, 23, 94, 11, 39, 20, 16 and 5 using the hash function h(i) = (2i+5) mod 11. Q.4 What is the average number of comparisons in a sequential search? Q.5 1 Sort the following list using Heap Sort technique, displaying each step. 20, 12, 25 6, 10, 15, 13 DEV BHOOMI INSTITUTE OF TECHNOLOGY, DEHRADUN TUTORIAL SHEET Course Name:Data Structure using C++ Tutorial Sheet No. 1 Course Code:TCS-607 Faculty :Mr. HimanshuDewedi Branch: ECE Semester: VI Unit/Title:UNIT-5 Date of Discussion: