Determining the Optimal Process Technology for Performance-

Constrained Circuits

Michael Boyer & Sudeep Ghosh

ECE 563: Introduction to VLSI

December 5th, 2006

Outline

• Motivation

• Methodology

• Related work

• Results

• Conclusion

Performance Classes

1. Unconstrained– General-purpose microprocessors

2. Constrained– Digital signal processors – Many embedded devices

• Relation to technology scaling

Methodology

• Build circuit in multiple technologies

• Vary supply voltage and measure:– Delay– Active power– Leakage power

• Vary duty cycle and frequency and compute minimum power

Circuit

PTM Threshold Voltages

Technology Vth0n Vth0p

130nm 0.3782 -0.321

90nm 0.397 -0.339

65nm 0.423 -0.365

45nm 0.466 -0.4118

32nm 0.5088 -0.450

Total Power Calculation

= activity factor

T = circuit delay

Ttarget = maximum delay = 1 / frequency

leakagetargetactivetargettotal PTTPTTP ))/(1()/(

Related Work

• 1995: Minimizing Power Consumption in Digital CMOS Circuits– Chandrakasan & Brodersen

• 2005: An Ultra Low Power System Architecture for Sensor Network Applications– Hempstead, et al

Delay vs. Supply Voltage

0

2

4

6

8

10

12

14

16

18

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Supply Voltage (V)

Del

ay

(n

s)

130nm

90nm

65nm

45nm

32nm

Delay vs. Supply Voltage

0

100

200

300

400

500

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Supply Voltage (V)

Del

ay

(n

s)

1.6um

0.6um

Active Power vs. Supply Voltage

0.1

1

10

100

1000

10000

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Supply Voltage (V)

Act

ive

Po

we

r (u

W)

130nm

90nm

65nm

45nm

32nm

Active Power vs. Supply Voltage

1

10

100

1000

10000

100000

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Supply Voltage (V)

Act

ive

Po

we

r (m

W)

1.6um

0.6um

Leakage Power vs. Supply Voltage

0.1

1

10

100

1000

10000

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Supply Voltage (V)

Lea

kag

e P

ow

er (

uW

)

130nm

90nm

65nm

45nm

32nm

Leakage Power vs. Supply Voltage

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Supply Voltage (V)

Lea

kag

e P

ow

er (

pW

)

1.6um

0.6um

Conclusion

• 0.6um best choice for low duty cycle, low frequency operation

• Problems:– PTMs– 1.6um

References• S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, vol. 19,

no. 4, pp. 23-29, 1999.

• A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.

• M. Hempstead, et al, “An Ultra Low Power System Architecture for Sensor Network Applications”, Proceedings of the 32nd International Symposium on Computer Architecture, 2005.

• Y. Cao, et al, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, CICC, pp. 201-204, 2000.

• C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies”, Symp. VLSI Circuits, pp. 5-6, 2001.