Determination of Determination of Logic Reversibility Logic Reversibility

in Reduced in Reduced Ordered Binary Ordered Binary

Decision DiagramsDecision DiagramsZakaria HamzaZakaria Hamza

CS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Professor: Dr. Gerhard DueckProfessor: Dr. Gerhard Dueck

OutlineOutline

Achieved GoalsAchieved Goals Milestones of ProjectMilestones of Project Outstanding IssuesOutstanding Issues ResultsResults Logic Synthesis AlgorithmLogic Synthesis Algorithm Discussions and ConclusionDiscussions and Conclusion

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Achieved GoalsAchieved Goals

Determination of basic function Determination of basic function properties:properties: TautologicalTautological ReversibleReversible ContradictoryContradictory

Module-based interpreter included for Module-based interpreter included for function developmentfunction development

Ability to map to and from PLA and Ability to map to and from PLA and SPEC files directlySPEC files directly BDD graph generationBDD graph generation

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Achieved GoalsAchieved Goals Demonstration of the Demonstration of the

logic synthesis logic synthesis algorithm:algorithm: Detect input typeDetect input type Use fastest algorithm to Use fastest algorithm to

derive properties of a derive properties of a binary function and binary function and output output

11stst image: sample dual image: sample dual variable ROBDDvariable ROBDD

22ndnd image: sample truth image: sample truth table derived from table derived from specification and PLA specification and PLA file.file.

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Milestones of ProjectMilestones of Project

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Logic Function Analysis

Determine FunctionProperties

Determine Reversibility

Create User Interface

ROBDD/BDD Tools Truth Table Tools

Function Analysis

Generate Reversibility

Optimize Algorithm

: Pending

: Completed

Outstanding IssuesOutstanding Issues

Generate reversible functions from logic Generate reversible functions from logic function specificationsfunction specifications

Determine if patterns are found within Determine if patterns are found within functions:functions: TransitivityTransitivity SymmetrySymmetry Simplification patternsSimplification patterns

Decide best option to analyze any given Decide best option to analyze any given PLA/SPEC configurationPLA/SPEC configuration

Optimize incompletely specified functions Optimize incompletely specified functions Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Results (Runtime)Results (Runtime)

Java-Based Logic Engine:Java-Based Logic Engine: Cross-platform (requires 1.4.2 or newer)Cross-platform (requires 1.4.2 or newer) Compatible with UNIX command line Compatible with UNIX command line

based packages (i.e.: CUDD)based packages (i.e.: CUDD) Includes powerful source code for Includes powerful source code for

handling BDD structures using JDDhandling BDD structures using JDD Relies on a virtual machine and does not Relies on a virtual machine and does not

drivers or platform specific featuresdrivers or platform specific features Uses system calls if availableUses system calls if available

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Results (Toolbox)Results (Toolbox)

Includes C and POSIX command line Includes C and POSIX command line verification programsverification programs

PLA and SPEC interchangeabilityPLA and SPEC interchangeability Programmed adaptability to GraphViz Programmed adaptability to GraphViz

based graph data structures (for large based graph data structures (for large numbers of variables)numbers of variables)

Supports modifying logic functionsSupports modifying logic functions Determines if a function is reversible or Determines if a function is reversible or

could be made reversible using an could be made reversible using an exponential algorithmexponential algorithm

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Results (GUI)Results (GUI)

Planned support for modification of Planned support for modification of Karnaugh maps, Toffoli networks, BDD Karnaugh maps, Toffoli networks, BDD and other logic display formalismsand other logic display formalisms

Allow user input and interaction with Allow user input and interaction with display formalism structuresdisplay formalism structures

UI engine used to define customizable UI engine used to define customizable operations and functionsoperations and functions

Toolbox is integrated with UIToolbox is integrated with UI

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Logic Synthesis Logic Synthesis AlgorithmAlgorithm

Input PLA/SPEC/BDD data structuresInput PLA/SPEC/BDD data structures Use dynamic programming to analyze function and Use dynamic programming to analyze function and

generate as much information about it as possiblegenerate as much information about it as possible Module section for specific functionalityModule section for specific functionality

ReversibilityReversibility Simplification/ReductionSimplification/Reduction ContradictionContradiction Quine-McCluskey/SAT/Circuit optional (brute force) algorithms, Quine-McCluskey/SAT/Circuit optional (brute force) algorithms,

etc.etc. Create BDDCreate BDD

Convert to ROBDDConvert to ROBDD User interface manual specifications (inherited functions User interface manual specifications (inherited functions

from Quiver/RevLib as well)from Quiver/RevLib as well) Heuristic algorithm to generate output function or graphHeuristic algorithm to generate output function or graph

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Further WorksFurther Works

Resolve outstanding issues (further Resolve outstanding issues (further developing a thesis base)developing a thesis base)

Optimize code for better performance Optimize code for better performance and increased range of operabilityand increased range of operability

Use sparse matrices to store truth Use sparse matrices to store truth tablestables

Optimize algorithm runtime for large Optimize algorithm runtime for large numbers of variables (>20) or use numbers of variables (>20) or use hardware with larger addressing modeshardware with larger addressing modes

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject

Discussions and Discussions and ConclusionsConclusions

Current algorithm consumes exponential Current algorithm consumes exponential resources relative to the number of input resources relative to the number of input variablesvariables

Functions may or may not terminate Functions may or may not terminate depending on how effectively virtual memory depending on how effectively virtual memory is usedis used

Storing large truth tables is simply infeasible Storing large truth tables is simply infeasible and a graph structure is almost and a graph structure is almost indispensableindispensable

Tree-based compression structures may Tree-based compression structures may reduce runtime dramatically if properly reduce runtime dramatically if properly encodedencoded

Zakaria HamzaZakaria HamzaCS6805: Logic Synthesis Final CS6805: Logic Synthesis Final ProjectProject