designing wideband frontends for gsps ... - analog devices

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Designing Wideband Frontends

for GSPS Converters

March 2014

2

Agenda

Frontend Parameter Definitions

Differences between Active (Amplifiers) and Passive (Baluns)

Frontends

Balun Parameters

Return Loss Example

Phase Imbalance

Layout Example

Balun Types

Frontend Matching Example

Optimization

Resources and References

www.analog.com/highspeedadc

3

Analog Inputs: Introduction

XFMR

1:X ZRs

Rs

*Cf

0.1uF

Converter

Internal

Input ZVIN-

VIN+

CadcRadc

0.1uF

0.1uF

Rt

Rt

0.1uFAmplifier

Or

Gain Block

Ro

Frontend

*Optional

The term “frontend” generally implies that this is a network or coupling circuit that connects between the last stage of the signal chain (usually an amplifier, gain block or tuner) and the converter’s analog inputs.

In order to achieve DS performance the designer must understand the frontend goals

There are typically two types of frontends, they are passive or active. It must also be very linear, well balanced and properly laid out on the printed

circuit board (pcb) in order to preserve the signal content properly.


4

Analog Inputs: Laying the Foundation

Designing an input network is important because it allows for a complete evaluation over the converter’s entire useable band.

When designing the network there are 5 parameters to keep in mind: Input Impedance / VSWR or Voltage Standing Wave Ratio, is a unitless

parameter that shows how much power is being reflected into the load over the bandwidth of interest. Input impedance of the network is specified value of the load, usually this is 50ohms.

Passband Flatness is usually defined as the amount of fluctuation/ripple that can be tolerated within the specified bandwidth.

Bandwidth is simply the beginning and ending of the frequencies to be used in the system.

SNR (signal-to-noise ratio) / SFDR (spurious free dynamic range)

Input Drive Level is a function of the bandwidth, input impedance, and VSWR specifications. This sets the gain/amplitude required for a fullscale input signal at the converter. It is highly dependent on the frontend components chosen, i.e. – transformer, amplifier, AAF, and can be one of the most difficult parameters to achieve.


Quick Note on BW

FREQUENCY (MHz)

FU

ND

AM

EN

TA

L L

EV

EL

(d

B)

0

–6

–5

–7

–8

–2

–1

–3

–4

0 450 50040035030025020015010050

04

41

8-0

38

Bandwidth

(-3dB)

Passband

Flatness

Inp

ut

Dri

ve

Le

ve

l (d

Bm

)

www.analog.com/highspeedadc 5

6

Amplifier vs. Transformer

List of critical system parameters and which

performs best….

Parameter Usual preference Bandwidth Transformer

Gain Amplifier

Passband flatness Amplifier

Power requirement Transformer

Noise Transformer

DC vs. AC coupling Amplifier (dc level preservation)

Transformer (dc isolation)


Transformer Basics

Turns Ratio n = N1/N2

Defines the ratio of primary voltage to secondary voltage

Impedance Ratio n2 = Z1/Z2

Seen as the primary reflected from the secondary, the square of the turns ratio

The transformer’s signal gain 20 log (V2/V1) = 10 log (Z2/Z1)

A transformer with a voltage gain of 3 dB would have a 1:2 impedance ratio

This is good since data converters are voltage devices. Voltage gain is noise FREE!

7 www.analog.com/highspeedadc

Understanding the Transformer - Modeling


Understanding the Transformer - Performance

Return

Loss

Insertion

Loss


Understanding Transformer Return Loss

All XFMRs have loss, use return loss to calculate the correct impedance match, i.e. – termination resistors

Example: Center frequency = 110MHz, Impedance ratio = 1:4

Return Loss = -18.9 dB @ 110MHz = 20*log(50-Zo/50+Zo)

10^(-18.9/20) = (50-Zo/50+Zo)

Zo = 39.8ohm

Next ratio the primary Zo to the secondary ideal impedance.

Z(Prim Reflected) / Z(Sec Ideal) = Z(Prim Ideal) / Z(Sec Reflected)

39.8/200 = 50/X

Solving for X, X = 251ohm


0

4

8

12

16

0 1 10 100 1000 10000

Frequency (MHz)

Ph

as

e I

mb

ala

nc

e (

de

g)

Double XFMR Config

Single XFMR Config

Performance Difference

@ 100MHz

Phase

Imbalance

Amplitude

Imbalance

0.

0

0.

5

1.

0

1.

5

2.

0

0 1 10 100 1000 10000

Frequency (MHz)

Am

pli

tud

e I

mb

ala

nc

e (

dB

)

Double XFMR Config

Single XFMR Config

Performance Difference

@ 100MHz

Input Balancing: Transformer Specs


Input Balancing: Testing the Data Converter

NOTES :

1 ) AIN levels should be adjusted for the

frequency and level specified .

2 ) Encode setting should be adjusted to the

specified rate .

3 ) Unless onboard regulators are used ,

supplies should be at nominal .

4 ) Temperature should be at ambient unless

otherwise noted .

5 ) Use the appropriate configuration file for

ADC Analyzer .

6 ) Use appropriate " Revs " on Eval board and

Parts as noted .

Analog

Ouput

differentail or

single - ended

Supply

Input

Encode

Input

Differential

Analog

Input

AD 92 xx , AD 94 xx or

AD 66 xx Evaluation

Board

ADC - FIFO

Board

Supply

Input

Monitor

PC

USB

Standardized 6 - 9 V

or Lab Supplies

Standardized 6 - 9 V

or Lab Supplies

ADC DUT

Analog

Ouput

Signal Generator

Ch 1

Oscilloscope

Ch 2

2-Way

Splitter LPF or BPF

* Both Signal Generators Refernce

Phase Locked

* All Cables Must

be Matched

Lengths

2-Way

Splitter LPF or BPF

Signal Generator

Signal Generator

12

2nd Harmonic Distortion


13

3rd Harmonic Distortion


14

Transformer Configurations

IN OUT

~OUT

IN OUT

~OUT

IN OUT

~OUT

IN OUT

~OUT

IN OUT

~OUT

Single Configurations

Double Configurations

Triple Configuration


XFMR & Balun Phase Imbal Performance


WB 1:1 Z Ratio XFMR/Balun Types

MFG / Model Number BW Cost (USD)

Hyperlabs / HL9402/3

20GHz

$2400/$1000

Picosecond / 5310A 6.5GHz $1200

Marki uWave / BAL-0006SM 6GHz

$124

MiniCircuits / TCM1-83X+ 8GHz

<$10

MiniCircuits / TCM1-63AX+ 6GHz

<$10

MiniCircuits / TCM1-43X+ 4GHz

<$10

Anaren / B0322J5050A00 2.2GHz <$5


18

Input Balancing: Layout

2HD = 5dB Better

Balanced

Unbalanced

Performance Results


19

Generic Passive Frontend and Performance Specs

Performance Specs Case 1 – R1=25,

R2=33, R3=33

Case 2 – R1=25,

R2=33, R3=10

Case 3 – R1=10,

R2=68, R3=33

Bandwidth (-3dB) 3169 MHz 3169 MHz 1996 MHz

Pass-Band Flatness (2GHz Ripple) 2.34 dB 2.01 dB 3.07 dB

SNRFS @ 1000 MHz 58.3 dBFS 58.0 dBFS 58.2 dBFS

SFDR @ 1000 MHz 74.5 dBc 74.0 dBc 77.5 dBc

H2/H3 @ 1000 MHz -74.5 dBc/-83.1 dBc -77.0 dBc/-74.0 dBc -77.5 dBc/-85.6 dBc

Input Impedance @ 500MHz 46 Ohms 45.5 Ohms 44.4 Ohms

Input Drive @ 500 MHz +15.0 dBm +12.6dBm +10.7dBm


20

Bandwidth Matching


Summary

GSPS converters offer ease of use in theory however, achieving bandwidth in the +1GHz range can pose new challenges to designing a frontend network.

Phase imbalance is important when specifying a balun yielding optimal second order linearity.

Poor layout techniques can eat away converter performance too.

Lastly, remember there are many parameters that need to be met in order to satisfy the “match” for your particular application.


For More Information on the High Speed

ADC Portfolio Visit www.analog.com/highspeedadc

Resources Available on the Web Include:

Training Videos

Reference Circuits

Application Notes

Technical Articles

http://ez.analog.com/community/data_converters/high-speed_adcs


http://www.analog.com/highspeedadc





23

References:

Papers/Articles

1. Transformer-Coupled Front-End for Wideband A/D Converters – Analog Dialogue, April 2005

2. Wideband A/D Converter Front-End Design Considerations – When to Use a Double Transformer Configuration– Analog Dialogue, July 2006

3. Wideband A/D Converter Front-End Design Considerations II - Amplifier- or Transformer Drive for the ADC? – Analog Dialogue, February 2007

4. AN-827, A Resonant Approach to Interfacing Amplifiers to Switch-Capacitor ADCs

5. AN-742, Frequency Domain Response of Switched-Capacitor ADCs

6. AN-912, Driving a Center-Tapped Transformer with a Balanced Current-Output DAC

7. Low-Noise Electronic System Design, C.D. Motchenbacher and J.A. Connelly, Wiley, 1993


24

References:

Papers/Articles

1) How to Test Power Supply Rejection Ratio in an ADC, EETimes, July 2003, Rob Reeder

2) Ask The Applications Engineer—37, Low-Dropout Regulators, Analog Dialogue, May 2007

4) Powering High-Speed Analog-to-Digital Converters with Switching Power Supplies,

EETimes – TechOnLine, May 2009, Michael Cobb

7) CN-0135, Powering the AD9272 Octal Ultrasound ADC/LNA/VGA/AAF with the ADP5020

Switching Regulator PMU for Increased Efficiency

8) CN-0137, Powering the AD9268 Dual Channel, 16-bit, 125 MSPS Analog-to-Digital Converter

with the ADP2114 Synchronous Step-Down DC-to-DC Regulator for Increased Efficiency

9) Improve The Design Of Your Passive Wideband ADC Front-End Network, E Design, 03/10

10) Achieve CM Convergence Between Amps And ADCs, Electronic Design, 07/10

11) Transformer-Coupled Front-End for Wideband A/D Converters – Analog Dialogue, 04/05

12) Pushing the State of the Art with Multichannel A/D Converters – Analog Dialogue, 05/05

13) Which ADC Architecture is Right for Your Application – Analog Dialogue, June 2005

14) Wideband A/D Converter Front-End Design Considerations – When to Use a Double

Transformer Configuration– Analog Dialogue, July 2006

15) Wideband A/D Converter Front-End Design Considerations II - Amplifier- or Transformer

Drive for the ADC? – Analog Dialogue, February 2007

16) Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective – Analog

Dialogue, February 2008

17) All RAQs: located at www.analog.com/raq


25

References:

Application Notes

1) AN-742, Frequency Domain Response of Switched-Capacitor ADCs 2) AN-827, A Resonant Approach to Interfacing Amplifiers to Switch-Capacitor ADCs 3) AN-935, Designing an ADC Transformer-Coupled Front End 4) AN-835, Testing High-Speed A/D Converters 5) AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)

6) AN-501, Aperture Uncertainty and ADC System Performance

7) AN-756, Sampled Systems and the Effects of Clock Phase Noise and Jitter ADI Webinars

1) Designing Transformer Coupled Front-Ends for High Performance A/D Converters, 04/05

2) Designing Power Supplies for High-speed A/D Converter Applications, August 2010

3) Designing with Switching Regulators in High-Speed A/D Converter Applications, June 2009 S-parameter data

Go to AD9204/12/15/19/22/26/28/31/33/35/36/37/44/45/46/48/51/52/58/59/68/87 webpage, click on Evaluation Boards, upload S-parameter data in an MS Excel spreadsheet

Design Tools

1) ADI DiffAmpCalc, http://analog.com/diffampcalc

2) ADIsimADC, www.analog.com/adisimadc

3) ADIsimclock, www.analog.com/adisimclock Books

Low-Noise Electronic System Design, C.D. Motchenbacher and J.A. Connelly, Wiley, 1993


http://analog.com/diffampcalc

http://www.analog.com/adisimadc

http://www.analog.com/adisimclock

Useful Data Converter Formulas

Theoretical Signal-to-Noise Ratio (SNR)

RMS Signal =(FSR / 2)/ sqrt(2), RMS Noise = Qn = q/ sqrt(12)

SNR (dB) = RMS Signal / RMS Noise = 20*log(2(n-1)*sqrt(6)) = 6.02*n + 1.76

Signal-to-Noise Ratio and Distortion (SINAD)

SINAD (dB) = -20*log (sqrt(10(-SNR W/O DIST/10) + 10(THD/10)))

Total Harmonic Distortion (THD)

THD (-dB) = 20*log (sqrt((10(-2ND HAR/20))2 + (10(-3RD HAR/20))2 +… (10(-6TH HAR/20))2 )

Effective Number of Bits (ENOB)

ENOB (BITS) = (SINAD – 1.76 + 20*log(FSR/ActualFSR))/ 6.02

Theoretical Noise Floor

Noise Floor (-dB) = 6.02*n + 1.76 + 10*log (N/2),

(See Table1 ), Assume coherent sampling and no windowing

Noise Floor (-dB) = 6.02*n + 10*log (3*N/(p*ENBW)), Assume noncoherent sampling and no windowing

FFT Points 12-BIT 14-BIT 16-BIT

1024 101 113 125

2048 104 116 128

4096 107 119 131

8192 110 122 134

16384 113 125 137

32768 116 128 140

SNR (dB) 74.0 86.0 98.1

Definitions / Terms

Fs = Sampling Rate (Hz)

Fin = Input Signal Frequency (Hz)

FSR = Full Scale Range (V)

n = Number of Bits

q = LSB Size

Qn = Quantization Noise

LSB = Least Significant Bit = FSR/2n

N = Number of FFT Points

ENBW = Equivalent Noise Bandwidth of window function (Example: Four-Term Blackman-Harris Window, ENBW = 2)

Table 1

26

27

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