designing dc-blocking capacitor transitions to enable...
TRANSCRIPT
Designing DC-Blocking
Capacitor Transitions to Enable
56Gbps NRZ & 112Gbps PAM4
Scotty Neally, Samtec Teraspeed Consulting
Scott McMorrow, Samtec Teraspeed Consulting
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Speakers
Scotty Neally
Signal Integrity Consultant
Samtec Teraspeed Consulting
Scotty Neally is an experienced signal integrity consultant with a background in
high density PCB design and measurement, automation of signal integrity design
flows, and currently focuses on system design for emerging technologies.
Scott McMorrow
CTO, Signal Integrity Products
Samtec Teraspeed Consulting
Scott McMorrow is an expert in high-performance design and signal integrity
engineering, with a broad background in complex system design, interconnect
and signal integrity engineering, modeling and measurement methodology, and
professional training, spanning over 25 years.
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Tradeoffs
o Cost
o Leadtime
o Performance
• Reliability
System Design
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Decision Diagram
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(Low) Cost
(Fast) Leadtime
(High) Accuracy
Traditional Capacitor Models
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RLC ModelShorting Resistor PEC Plane
DC Blocking Capacitor Design Layout
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Design Optimization
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Test Vehicle Preview
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De-embeddedReference Plane
1mm
MLCC SEM Measurements
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HFSS Model
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Shunt Simulation
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Using the test vehicle with 4 different
capacitor values and 2 structures
(VOID & SOLID) we compare the
insertion loss of each
o 220nF, 150nF, 47nF, 22nF
0201 PKG Family
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Capacitor ModelingSim to Measurement Comparison
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Compare Capacitor Models1. SIM 220nF - All Model Types2. SIM 220nF/MEAS All Values Complex Model (VOID)3. SIM 220nF/MEAS All Values Complex Model (SOLID)
Channel Exploration4. SIM & MEAS 220nF, Chip to Module Host TX Pkg Only (high loss pkg)5. SIM & MEAS 220nF, Chip to Module Optimistic TX/RX (low loss pkg)
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14 & 5
How do simulation results vary between modeling structures?
How do capacitor values for a given case size (0201) affect inductance?
How does the transition geometry (SOLID vs VOID) impact channel performance?
What impact does loop inductance have on these geometries?
What To Pay Attention To
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1. SIM - 220nF Capacitor, All Model Types
1. SIM - 220nF Capacitor, All Model Types
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1. SIM - 220nF Capacitor, All Model Types
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Model Comparison 56G Single Bit Response
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COMPLEX_SOLID
COMPLEX_VOID
SHORT_VOID
SIMPLE_VOID
46.7mV
32.1mV62.0mV
33.0mV
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2 & 3. SIM / MEAS - All Measured Values
(VOID & SOLID Configuration)
2. SIM vs MEAS – SDD11 (VOID)
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SIMULATION MEASUREMENT
-220nF-150nF
-47nF-22nF
-220nF
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3. SIM vs MEAS – SDD11 (SOLID)
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-220nF-150nF
-47nF-22nF
SIMULATION MEASUREMENT
-220nF
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-220nF-150nF
-47nF-22nF
SIMULATION MEASUREMENT
-220nF
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2. SIM vs MEAS – SDD21 (VOID)
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SIMULATION MEASUREMENT
-220nF-150nF
-47nF-22nF
-220nF
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3. SIM vs MEAS – SDD21 (SOLID)
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-220nF-150nF
-47nF-22nF
SIMULATION MEASUREMENT
-220nF
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2. SIM vs MEAS – TDR, 12ps RT (VOID)
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-220nF-150nF
-47nF-22nF
SIMULATION MEASUREMENT
-220nF
3. SIM vs MEAS – TDR, 12ps RT (SOLID)
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4. Chip to Module ExplorationSimulation to Measurement Comparison
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220nF DC Blocking cap with Host Board package only:• 56G NRZ• 112G PAM4• 112G PAM4, 1 TAP DFE• 112G PAM4, 3 TAP DFE• 112G PAM4, 12 TAP DFE
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4. Host Package Only StudyIncludes TX Package & 220nF Cap
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DIE PIN ARx6 FQSFP
56G NRZ
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Measured VOIDVoltage Bathtub - All Cases
112G PAM4
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Measured VOIDVoltage Bathtub - All Cases
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112G PAM4 3 TAP DFE
Measured VOIDVoltage Bathtub - All Cases
5. Chip to Module ExplorationSimulation to Measurement Comparison
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220nF DC Blocking cap with optimistic TX/RX package:• 56G NRZ• 112G PAM4• 112G PAM4, 1 TAP DFE• 112G PAM4, 3 TAP DFE• 112G PAM4, 12 TAP DFE
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5. Optimistic Host/Module Package StudyIncludes TX/RX Package & 220nF Cap
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DIE PIN ARx6 FQSFP PKG
56G NRZ
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Measured VOIDVoltage Bathtub - All Cases
112G PAM4
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Measured VOIDVoltage Bathtub - All Cases
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112G PAM4 3 TAP DFE
Measured VOIDVoltage Bathtub - All Cases
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Test Vehicle Correlation WorkVOID, SOLID, & CAL Layouts
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Test Vehicle Correlation Work220nF VOID Measurements
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Test Vehicle Correlation Work220nF VOID Simulation v2.0
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QUESTIONS?
Thank you!
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