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Design synthesis and implementation for FPGA using Xilinx ISE

Design synthesis and implementation for FPGA using Xilinx ISE

Prepared by

Vysakh P

Amrita School of Engineering

Under the Guidance of

Prof. Ramesh Bhakthavatchalu

Department of ECE

Amrita School of Engineering

Amrita Vishwa Vidyapeetham

VERSION 1.0

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Step 1: Invoking the ISE project navigator:

Run: ISE in explorer

A Splash screen appears indicating the start o the navigator session.

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This is the first look of the Project navigator window

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Step 2: Starting a new project:

Select : File -> New Project to start a new project

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Enter the Project name, location and top level source type

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Specify the Device properties

Refer to the inside of kit lid to get the required device properties of the kit you are using

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Adding the Source:

If you already have a source file , (design/ test bench) skip to page no : 12

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Choose your file type, insert the file name, verify the location and proceed

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Specify the port and module names and directions in the module definition window. This will

include the post definition to the automatically generated HDL template

This step can be skipped to specify the port specifications in the design file.

To skip, press next without specifying the ports.

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Verify the summary of the template file that will be created and click Finish

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Click yes if a confirmation to create directory is asked

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If you already have a design file / test bench, add it in the Add existing source

window.

This appears either after adding new sources or skipping it.

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Verify the summary of the project that will be created and click Finish

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Specify the file association type in the next window. Design files will be implementation and

test benches will be simulation type.

This is to be done for all the files that have been added into the design.

Give All to allow the tool to choose the t e of association.

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Step 3: Working with the Design.

The top module will be automatically identified and marked with the symbol.

Double clicking the design file name will open it in the right side window. It can be edited and

saved from there.

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Syntax check of the design file can be done with the Check Syntax option in the Synthesis XST

tree.

Ensure that the file to be checked is highlighted in the source window.

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A successful syntax check will display a next to the Syntax Check option,

In case there are errors, a will be displayed and the errors can be viewed in the errors tab of the

log window. Clicking on the error will highlight the error in the code window.

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To generate a test bench fo rhte design, right click the top module and click New Source. In case

there is already a test bench, click add source to browse for it.

Give association as Simulation while opening an existing test bench.

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Select the appropriate file type and give the file name.

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Verify the Association Source, the design for which you intent to generate the test bench

template. In case there is a mismatch, verify the file you highlighted and clicked during New

Source operation.

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Verify the parameters in the summary window.

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The Test bench (or any other simulation component) will not be visible in the source tree until

source category is changed to Behavioral Simulation

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Highlight the required test bench to get the simulator options.

Click Behavioral Check Syntax to check for syntax errors in the test bench.

Model Sim simulator can also be integrated for call by specifying the simulator in device

properties window (Page 6)

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Upon successful syntax check, click Simulate behavioral model to apply and run the test bench

vectors on the design

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The simulation window opens, showing the resultant wave form. Extra nets, signals and registers

can be added from the Sim objects window by dragging and dropping the required signal.

Run time can be ad usted and reset from the tool bar.

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After completing the required test runs, change back to implementation mode.

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Highlight the top module and click Synthesize - XST in the process window.

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This synthesizes the design into a devise compatible form.

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Step 4: Implementing the Design.

The synthesized design is to be transferred into the device.

First step is to specify the pins to which the nets are connected. This is done using a User

Constraints File (UCF).

To add a UCF, right click on the top module and click New Source.

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Select Implementation Constraints File and specify the UCF file name.

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Verify file association details and click next.

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Highlight the UCF file and click Edit Constraints (text)

Give the pin mapping details for each net used in the design in the following syntax and save it.

net net_name loc = ppin_number

The pin number is to be finalized after referring to the kit documentation to see the device

available at the pin.

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Highlight the top module and click Implement design to perform the translation, mapping and

place & route of the design.

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Highlight the top module and click Generate Programming File to generate a bit file of the

implemented design.

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Step 5: Transferring the Design to the FPGA.

After successfully generating a bit file , begin XILINX impact by typing impact at the explorer

Run.

Click create a new project radio button and browse to the working folder.

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Specify the configuration file (.bit generated in the project directory upon implementing the

design. ) in the Assign New Configuration File window.

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Click yes in the following dialogue box stating a change in the device configuration, This is tocope with some minor tweaks in the kit.

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Click OK at the warning box stating a change of startup clock. This is to facilitate JTAGprogramming of the device.

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Now a JTAG Scan chain with the device in the kit will be displayed.

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Right Click on the device icon to get programming options. Click Program to transfer the bit

stream into the device.

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Click OK in the Programming Properties window.

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The bit stream will be transferred into the device, and the design will be functional in the FPGA

from this point.

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To change the configuration file, right click on the window and select Assign New Configuration

File