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ECE 477 Digital Systems Senior Design Project Fall 2005

Homework 11: Software Design Considerations, Narrative, and DocumentationDue: Thursday, November 10, at Classtime

Team Code Name: _Backseat Drivers _____ Group No. __11__

Team Member Completing This Homework: _Chad Aeschliman _

Report Outline: Introduction (brief description of design project, with a focus on software design

considerations) Software design considerations (memory models, memory sections/mappings, startup

code, organization of embedded application code) Software design narrative (detailed description of what each code module does) Software documentation

o Flowcharts/algorithmso Listing (with comments)o References (sources for published code adapted for use in your project)

Evaluation:

Component/Criterion Score Multiplier Points

Introduction & Software Considerations 0 1 2 3 4 5 6 7 8 9 10 X 3

Software Design Narrative 0 1 2 3 4 5 6 7 8 9 10 X 3

Software Documentation 0 1 2 3 4 5 6 7 8 9 10 X 3

Technical Writing Style 0 1 2 3 4 5 6 7 8 9 10 X 1

TOTAL

NOTE: This is the last in a series of four “design component” homework assignments, each of which is to be completed by one team member. The completed homework will count for 10% of the team member’s individual grade.

Include this sheet as a cover page for your report


Introduction: This project inputs a video from a camera mounted in a car and from this determines the lateral position of the vehicle within the lane. Based on this it warns the driver if he is drifting out of the lane. The lane position is determined through a cross correlation of two sections of the image. Because this project is built around image processing there is a lot that needs to be done in software. The input image must be filtered and then large sections of data must be manipulated, particularly to perform the cross correlation. Also, to be effective this all must happen quickly and in real time.

Software Design Considerations: Our microprocessor is an Analog Devices BF532. It uses pipelining with three L1 SRAM caches, one for instructions, one for data, and one scratchpad. It also has a twelve channel DMA controller for handling data transfers between external peripherals. There are numerous options for adding external memory including glueless support for SDRAM. Booting can be done using a SPI interface to either external flash or EEPROM. The 4GB memory space uses 32 bit addressing and contains all internal and external memory, registers, and peripherals. The address space has following assignments taken from the datasheet [1] and is shown in figure 1.

Figure 1: Memory Map for Analog Devices BF532

(1) Internal SRAM: The internal L1 SRAM has physically separated instruction (1a), data (1b), and scratchpad (1c) memory blocks to enable pipelining. These blocks are all accessed at full microprocessor speed.


The instruction memory block is 48kB in size and can only be used for instructions. It is made up of a 32kB main section and a 16kB four-way set associative cache. During bootup it is filled from the boot ROM after which execution begins automatically.

The data memory block is 32kB in size and can be used for either data or instructions. It will be used to store subsections of the image for fast access. It is divided into two 16kB banks. Each bank will be able to hold 2000 pixels making it possible to do the cross correlation, which operates on only a subsection of the data, using this high speed memory.

The 4kB scratchpad block can only be used for the stack and local variables.

(2) External SDRAM: The MT48LC4M16A2 SDRAM from Micron [2] will be used for external memory. It is 64Mb in size and runs at 133MHz. Its architecture consists of 4 banks, each of which has 1M of 16bit data stored in 4096 rows and 256 columns. The primary use of the SDRAM will be to store the input image. Access to the SDRAM is entirely through the DMA, which is able to transfer data directly from the video input to the SDRAM so the processor is free to work on other tasks. The DMA is also able to perform block copying of 2D data which will facilitate filing the L1 data cache with subsections of the image. (3) Core and System Registers: The core and system MMR registers are used to configure the MCU and also to access the external peripherals such as the programmable flags used for output. In particular, the registers related to the programmable flags are located in the system MMR bank at addresses 0xFFC0 2400 through 0xFFC0 2419.

Boot Memory: The boot memory does not appear in the memory space and can only be used for booting. Our implementation uses 64kB of EEPROM accessed through the SPI interface. Although the processor can have up to 80kB of instructions in the on chip memory our code size is limited to 48kB because the 32kB data cache is being used to store image data. Thus the upper 16kB of the EEPROM will not be used. Booting from the EEPROM is achieved by setting the voltage level on two input pins. With these pins set appropriately, loading the code into the instruction memory is automatic as mentioned above with no configuration or programming required.

Software Design Narrative: The basic structure of the code is an initialization section and then a single interrupt service routine which will be called whenever an image is available. Appendix 1 in the software documentation is a flowchart showing the basic modules of the code and their execution order.

Initialization: The first step in the initialization is to configure the CPU. This consists of:

Set the clock frequency to 400MHz by setting the PLL registers. Disable all interrupts except the DMA Disable the watchdog timer Configure the real time clock Configure the UART serial port for debugging Set input/output status of programmable flags


Set the SDRAM configuration registers

The next step is to setup and start the video input. This consists of: Configure system DMA registers to point to the video input Configure the memory DMA registers to point to the SDRAM Set a global flag to indicate this is the first image Start the memory transfer When DMA ISR is called, catch that this is the first image and go to the rest of the

initialization, then clear the “first image” flag

Finally, perform some sanity checks Check that memory seems to actually contain an image

o Image pixels should not all have the same or nearly the same value Check that after copying the same subimage into both internal data banks the banks are

identical and not the same as they were before copying the data If everything works, blink the output LEDs a couple times, otherwise beep a couple times

and stop executing

If the initialization passes, wait on the DMA interrupt. All processing will occur within the DMA ISR or a subroutine called by the DMA ISR.

Input Image:Inputting an image simply requires waiting on the DMA interrupt. Once the video transfer has been started the first time it will continue indefinitely until stopped. At this point in the code, interrupts will be disabled in case the processing takes longer than the frame rate.

Input Turn Signal:The turn signal is indicated by two level indicators that are attached to the turn signal lever. They are set at slightly different angles such that when the turn signal is not active one of the indicators is on and the other is off. Moving the lever up turns both off and moving the lever down turns both on. So the turn signal is on if the xor of the two signals is 0 and it is off if the xor of the two signals is 1.

Process Image (x-corr):The first step is to temporally lowpass filter the image. This is done to preserve strong features but drop transient features. The current filtering method is a simple weighted averaging of the current image with the previous filtered image, i.e.

filtered_image = k*new_image + (1-k)*filtered_image, where k is typically << 1To perform this, the old filtered image and the new subimage are loaded into the internal data memory, the operation is performed, and the result is stored in the SDRAM for the next time. This is done for both subimages. Next the subimages are highpass filtered spatially by taking the derivative of the subimages along the rows. To perform this, the filtered subimage is loaded into the internal SRAM, the operation is performed, and the result is maintained in the internal memory. This is done for both subimages. After this step, the two filtered subimages are in the internal data memory, ready for the next step.


Perform Cross-Correlation:The cross-correlation can be performed quickly by recognizing the following relationship:

xcorr(x1,x2) = FFT(FFT(x1)*conj(FFT(x2))), where conj(x) is the complex conjugateThe first step is to find the complex Fourier transform of both subimages. This can be done using already existing routines provided by the compiler. The next step is to find the conjugate of the second subimage. The next steps are to multiply the subimages and then perform the FFT again. The final step is to find the mean of the correlation between all the rows giving a single correlation vector. All of these steps should be done in internal memory and the result should be stored in internal memory.

Determine Vehicle Position:The first step is to find the maximum value of the cross correlation. This provides a measure of the quality of the cross correlation and also provides an indication of where the most prominent lane boundary is. Now find the maximum value of the cross correlation in the opposite half vector of the current maximum. The ratio of this maximum value to the previous maximum gives an indication of whether two lane boundaries are present or only one. If two peaks are present than the position of the vehicle relative to the center of the lane is the average value of the location of the two peaks, where the center of the correlation vector is 0. Also, the coefficients for a linear fit of each peak location to the current lane position are updated. These coefficients are used when there is only one peak to predict the position of the vehicle.

The solution is valid if the maximum value for the cross correlation is above a threshold and also if the mean value of the correlation is below a certain value. This latter check ensures that the correlation is composed of sharp peaks which indicate a strong feature and not just a general high value of correlation due to bright patches in the image.

If the solution is valid, update the location which is stored in memory using a similar averaging filter to the temporal image filter:

location = k*new_location + (1-k)*old_location

Preprocess Image (obstacle):The first step is to perform a 2D derivative of a subimage which covers the region where an obstacle might be expected, i.e. a vertical strip in front of the vehicle.

Find Obstacles:The next step is to sum the absolute value of subsections of this derivative to find areas with a high density of features. If this sum exceeds a certain threshold then there is an obstacle.

Set Outputs:Update the LED display with the location if it is valid. If it is not valid blank the display. If the location is too far from the center of the lane and the turn signal is not on, turn on the buzzer. If there is an obstacle, turn on the buzzer and flash the LEDs.

This completes the processing for that image. Enable interrupts again and wait on the next interrupt.


Software Documentation/Appendix:Appendix 1 Flowchart of softwareAppendix 2 Matlab code which implements algorithm, corr2xs.mAppendix 3 C code of various routines from eval kit example for getting video input[3]

A Main initialization, main.cB PLL initialization, PLL_Setup.cC PPI initialization, PPI_Config.cD DMA initialization, DMA_Config.cE SDRAM initialization, SDRAM_Config.c

Appendix 4 References


Preprocess Image (x-corr):Temporally LP filter imageSpatially HP filter image

Preprocess Image (obstacle):Perform 2D derivative of image

HP filter result

Find Obstacles:Look for regions with high

density

Perform Cross-Correlation:Compute FFT of both subimages

Compute IFFT of product of FFTs

Determine Vehicle Position:Find peaks of x-correlation

Convert to lane positionCheck for valid solution

Set Outputs:Warn if leaving lane is not active and position is valid

Warn if obstacle detected

Initialization:Set control registers

Start video inputPerform sanity checks

Appendix 1: Flowchart of Software

Input Image:Called when image is available


Appendix 2 Matlab code which implements algorithm, corr2xs.m

% Chad Aeschliman clearclc filename = '..\WebCam Center\Capture\20051106\lane4.avi';aviinfo(filename)startframe = 1;stopframe = 500;numframes = stopframe-startframe+1;posstore = zeros(1,numframes);qualstore = zeros(1,numframes);qual2store = zeros(1,numframes);invalid = false; % input video and put grayscale images into arraymovie = aviread(filename,startframe:stopframe);sample = frame2im(movie(1));M = zeros(numframes,size(sample,1),size(sample,2));for index = 1:numframes M(index,:,:) = mean(frame2im(movie(index)),3);endclear('movie', 'sample') % loop through imagesfigure(1)center = 161;cutoff1 = 175;cutoff2 = cutoff1 - 10;cutoff3 = cutoff2 - 1;cutoff4 = cutoff3 - 10;threshold = 40;ml = 1;mr = 1;bl = 16;br = -16; for index = 1:numframes range = 159; current_image = squeeze(M(index,:,:)); sub_image1 = current_image(cutoff4:cutoff3,center-range:center+range); sub_image2 = current_image(cutoff2:cutoff1,center-range:center+range); sub_image1 = sub_image1 - mean(mean(sub_image1)); sub_image2 = sub_image2 - mean(mean(sub_image2)); sub_image1(sub_image1>threshold) = 127; sub_image2(sub_image2>threshold) = 127; sub_image1(sub_image1<-10) = -10; sub_image2(sub_image2<-10) = -10; if index==1 filt_image1 = sub_image1; filt_image2 = sub_image2; end filt_image1 = .9*filt_image1 + .1*sub_image1; filt_image2 = .9*filt_image2 + .1*sub_image2; filt_image1(sub_image1==127) = 127; filt_image2(sub_image2==127) = 127; filt_image1s = filt_image1; filt_image2s = filt_image2; filt_image1s = filt_image1s - mean(mean(filt_image1s));


filt_image2s = filt_image2s - mean(mean(filt_image2s)); filt_image1s(filt_image1s>threshold) = 127; filt_image2s(filt_image2s>threshold) = 127; filt_image1s(filt_image1s<=0) = -10; filt_image2s(filt_image2s<=0) = -10; fft1 = fft(filt_image1s,[],2); fft2 = fft(filt_image2s,[],2); xcorr = mean(ifft(fft1.*conj(fft2),[],2),1); xcorr = xcorr/max(max(xcorr)); subplot(2,1,1); current_image(cutoff4:cutoff3,center-range:center+range) = filt_image1s+128; current_image(cutoff2:cutoff1,center-range:center+range) = filt_image2s+128; current_image(cutoff1,:) = 255; current_image(cutoff2,:) = 255; current_image(cutoff3,:) = 255; current_image(cutoff4,:) = 255; image(current_image); axis('image'); colormap(gray(256)); subplot(2,1,2) range = 50; xcorr = xcorr/max(xcorr); xcorr = [xcorr(1:range) xcorr(end-range:end)]; xcorr = fftshift(xcorr); plot(-range:range,xcorr); [maxval,maxloc] = max(xcorr); maxloc = maxloc-(range+1); left = 0; if maxloc < 0 maxlocl = maxloc; xcorr(1:range) = 0; left = 1; else maxlocr = maxloc; xcorr(range+1:end) = 0; end [maxval2,maxloc] = max(xcorr); maxloc = maxloc-(range+1); if maxloc < 0 maxlocl = maxloc; else maxlocr = maxloc; end match = .6; if maxval2 > match location = .5*(maxlocl + maxlocr); else if left location = ml*maxlocl + bl; else location = mr*maxlocr + br; end end if (index==1)||(invalid) locationlast = location; else if (maxval2 > match) bl = .99*bl + .01*(location - maxlocl*ml);


br = .99*br + .01*(location - maxlocr*mr); end end location = .9*locationlast + .1*location; locationlast = location; if 1-mean(abs(xcorr)) < .75 invalid = true; else invalid = false; end if invalid location = nan; end posstore(index) = location; qualstore(index) = 1-mean(abs(xcorr)); qual2store(index) = 1-abs(maxval2-maxval); title(num2str(location)); xlabel(num2str([ml bl mr br])); ylim([-1 1]); drawnow;endfigure(2)plot(1:numframes,posstore,... 1:numframes,10*qualstore,... 1:numframes,10*qual2store);


Appendix 3 C code of various routines from eval kit example for getting video input [3]Appendix 3A main.c/*****************************************************************************************///// Name: BF533 EZ-KIT video ITU-656 receive mode///*****************************************************************************************

(C) Copyright 2003 - Analog Devices, Inc. All rights reserved.

File Name: Main.c

Date Modified: 10/25/04 TL Rev 0.2

Software: VisualDSP++3.1

Hardware: BF533 EZ-KIT Board

Special Connections: Connect a CVBS video source to the right bottom video jack "AVIN1" change switch #6 of SW3 to on of the ADSP-BF533 EZ-KIT Lite.

Purpose: After reset the ADV7183 is configured to output digital

video data in ITU656 mode 8bits wide. Additionally, The DSP is

configured to receive video data in ITU-656 format via the PPI Interface.

The DMA channel 0 is dedicated to transfer the data to the

external SDRAM immediately (Address 0x0).

******************************************************************************************/

#include <cdefBF533.h> //BF533 Register Pointer Definition#include <stdio.h>#include <sys\exception.h> //Interrupt Handling Header

// Sets up here all Prototype Functions void Init_EBIU(void);void Init_Flash(void);void Init_ADV(void);void Init_Interrupts(void);void Init_SDRAM(void);void Init_DMA(void);void Init_PPI(void);void Init_PLL(void);

void main(){

int i = 0;


//setup;Init_PLL();Init_EBIU(); //Async Memory Interface SetupInit_Flash(); //Flash Setup to config the flash GPIOsInit_ADV(); //Link the ADV7183 clock to the PPI and ADV7183 reset

printf("\n ADV Setup Lock Delay!\n"); //Gives the ADV7183 time to lock after reset

Init_Interrupts(); //Enter an interrupt subroutine after DMA has been finishedInit_SDRAM(); //SDRAM Setup to store the video imageInit_DMA(); //DMA Setup "PPI->DMA->SDRAM" Its configured in Stop

ModeInit_PPI(); //PPI Setup

while (1){

i = 1;}

}//end main


Appendix 3B PLL_Setup.c/******************************************************************************///// Name: BF533 EZ-KIT PLL Setup///******************************************************************************


File Name: PLL_Setup.c



Hardware: ADSP-BF533 EZ-KIT Board

Special Connections: None

Purpose: The file sets up the PLL

*********************************************************************************/

#include <cdefBF533.h>#include <ccblkfn.h>#include <sysreg.h>

void Init_PLL(void){

volatile int test=0;

sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register

*pSIC_IWR = 0x1;*pPLL_CTL = 0x2C00;ssync();idle();

}//end Init_PLL


Appendix 3C PPI_Config.c/******************************************************************************///// Name: BF533 EZ-KIT PPI Setup///******************************************************************************


File Name: PPI_Config.c





Purpose: The file sets up the PPI transfer

*********************************************************************************/

#include <cdefBF533.h>

void Init_PPI(void){

//The PPI is set to receive 525 lines for each frame*pPPI_FRAME = 525;

//PPI enabled, input mode, active video only, receive field 1&2, //packing enabled, skipping disabled, 8bit data bus, nothing inverted*pPPI_CONTROL = PORT_EN | FLD_SEL | PACK_EN | DLEN_8 ;

}//end Init_PPI


Appendix 3D DMA_Config.c/******************************************************************************///// Name: BF533 EZ-KIT DMA Setup///******************************************************************************


File Name: DMA_Config.c





Purpose: The file sets up the DMA transfer

*********************************************************************************/

#include <cdefBF533.h>#define Line_Length 720#define Frame_Length 525

void Init_DMA(void){

//Target address of the DMA*pDMA0_START_ADDR = 0x0;

//Line_Length 16bit transfers will be executed*pDMA0_X_COUNT = Line_Length;

//The modifier is set to 2 because of the 16bit transfers*pDMA0_X_MODIFY = 0x2;

//Frame_Length 16bit transfers will be executed*pDMA0_Y_COUNT = Frame_Length;

//The modifier is set to 2 because of the 16bit transfers*pDMA0_Y_MODIFY = 0x2;

//PPI Peripheral is used*pDMA0_PERIPHERAL_MAP = 0x0;

//DMA Config: Enable DMA | Memory write DMA | 2-D DMA | Discard DMA FIFO before start | enable assertation of interrupt | NDSIZE for stop mode | Enable STOP DMA

*pDMA0_CONFIG = DMAEN | DI_EN | WNR | WDSIZE_16| DMA2D | RESTART | DI_EN;

}//end Init_DMA


Appendix 3E SDRAM_Config.c/******************************************************************************///// Name: BF533 EZ-KIT SDRAM Setup///******************************************************************************


File Name: SDRAM_Config.c





Purpose: The file sets up the SDRAM

*********************************************************************************/

#include <cdefBF533.h>#include "ccblkfn.h"

//SDRAM Setupvoid Init_SDRAM(void){

if (*pEBIU_SDSTAT & SDRS) {//SDRAM Refresh Rate Control Register*pEBIU_SDRRC = 0x00000817;

//SDRAM Memory Bank Control Register*pEBIU_SDBCTL = 0x00000013;

//SDRAM Memory Global Control Register*pEBIU_SDGCTL = 0x0091998d;

ssync();}

}//end Init_SDRAM


Appendix 4 References: [1] “Blackfin Embedded Processor” Analog Devices, http://www.analog.com/UploadedFiles/Data_Sheets/320040195ADSP_BF531_2_3_b.pdf

[2] “64Mb Synchronous DRAM” Micron,http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf

[3] Example code included with evaluation kit.

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