Analog Integrated Circuits and Signal Processing, 27, 179–189, 2001©C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.

Design Procedure for Two-Stage CMOS Transconductance OperationalAmplifiers: A Tutorial

G. PALMISANO, G. PALUMBO AND S. PENNISIDipartimento Elettrico Elettronico e Sistemistico, Universita’ di Catania, Viale Andrea Doria, 6 I-95125 Catania, Italy

Tel: ++39.095.73823.05/13/18 Fax: 39.095.330793E-mail: gpalmisano@dees.unict.it; gpalumbo@dees.unict.it; spennisi@dees.unict.it

Received April 1, 1999; Revised July 24, 2000; Accepted September 12, 2000

Abstract. This paper deals with well-defined design criteria for two-stage CMOS transconductance operationalamplifiers. A novel and simple design procedure is presented, which allows electrical parameters to be univocallyrelated to the value of each circuit element and biasing value. Unlike previous methods, the proposed one issuited for a pencil-and-paper design and yields accurate performance optimization without introducing unnecessarycircuit constraints. Bandwidth optimization strategies are also discussed. SPICE simulations based on the proposedprocedures are given which closely agree the expected results.

Key Words: CMOS, amplifiers, OTAs, analog design, frequency compensation

I. Introduction

The two-stage operational transconductance amplifier(OTA) in Fig. 1 is a widely used analog building block[1–5]. Indeed, it identifies a very simple and robusttopology which provides good values for most of itselectrical parameters such as dc gain, output swing,linearity, CMRR, etc. Although the term OTA was orig-inally conceived for operational transconductance am-plifiers with linear transconductance (used for the im-plementation of continuous-time filters), for the sake ofsimplicity we will use the same term OTA for generaloperational transconductance amplifiers.

Despite its popularity, only uncomplete design pro-cedures were proposed for this OTA which arbitrarilyreduce the degree of freedom in the design equations,hence precluding the possibility to meet optimizedperformance [6,7]. Indeed, the approach proposed in[6] sets arbitrarily the compensation capacitor equalto the load capacitor, and that presented in [7] intro-duces constraints that require an onerous recursive pro-cedure. Finally, in [8,9] optimized design is left tocomputer simulation by means of a symbolic analysissoftware.

In this paper, a well-defined procedure for two-stageOTAs is presented which allows the value of each cir-cuit element of the amplifier (i.e., transistor aspect ra-

tios, bias current and compensation capacitor) to be uni-vocally related to the required amplifier performance.In such a way, OTA parameters are optimized with astraightforward pencil-and-paper analysis using accu-rate design equations.

The design procedure is based on the following mainparameters: noise, phase margin (M�), gain-bandwidthproduct ( fGBW), load capacitance (CL), slew rate (SR),input common mode range (CMR), output swing (OS),and input offset voltage (due to systematic errors).When M� is not given it is set to minimize settlingtime [10].

Important parameters such as dc gain, CMRR andPSRR, will not be used during the design steps sincethey depend on the output resistance of MOS transis-tors that is not easily modeled for a hand analysis. Suchparameters greatly depend on the amplifier topology(typical dc gain and CMRR in a two-stage OTA are inthe ranges of 60–80 dB and 70–90 dB, respectively)and can only be predicted by simulation using accuratetransistor models. Of course, there are electrical pame-ters which can be improved with appropriate circuitarrangements. For instance, a high drive capability canbe achieved by employing class AB instead of class Atopologies [11–13].

The proposed procedure in its general form is de-scribed in Section II. We will use the Miller

180 Palmisano, Palumbo and Pennisi

VDD

VSS

I B

C L

M3 M4

M1 M2_

IN IN+

M5

M8M7

M6

R C CCOUT

A

Fig. 1. Schematic of the two-stage OTA.

compensation and the nulling resistor technique for thecompensation of the right half-plane zero [14].

Three other possible extensions of the general ap-proach in Section II are discussed in Section III, whichallow optimization of the gain-bandwidth product tobe achieved. In these last approaches the compensationpath is properly used to perform a pole-zero compen-sation which increases the frequency of the amplifiernon-dominant pole. Unlike the general procedure, theseextensions, which are optimized for gain-bandwidthproduct performance, need some approximations.

Design examples are provided and comparisons be-tween simulated and expected results are also carriedout.

II. Standard Design Approach

A. Description

The procedure starts from the noise requirement. Ne-glecting flicker noise which contributes at low frequen-cies, the input noise voltage spectral density of the OTAin Fig. 1 is given by

Sn( f ) = 2 · 4kT2

3

1

gm1,2

[1 + gm3,4

gm1,2

](1)

where only the noise sources of the input stage havebeen considered. To minimize noise, we assume gm3,4 <

gm1,2 (which is easily met) and calculate the trans-conductance gain of transistors M1 and M2 fromequation (1)

gm1,2 ≈ 16

3

kT

Sn( f )(2)

If reduction of low frequency noise is required, flickernoise can be lowered by increasing the channel lengthand proportionally the channel width of M1 and M2.

Now, we are not able to determine the aspect ra-tio of M1 and M2, since their bias currents are notset, but the knowledge of gm1,2 and the gain-bandwidthproduct requirement, allows us to draw the value ofthe compensation capacitor according to the followingequation

CC = 1

2π

gm1,2

fGBW(3)

The slew rate performance of the amplifier dependson the slews on both the output node of the differentialstage and the output node of the second stage (i.e., theoutput of the OTA), to which we will refer as internaland external slew rate, respectively. These slew rateterms are related to the quiescent currents ID1,2 andID8 according to

SRINT = 2ID1,2

CC(4a)

SREXT = ID8 − 2ID1,2

CL(4b)

In order to satisfy slew rate performance, we have to setinternal and external slew rate not lower than the targetvalue SR. In a first design step we can set SRINT =SREXT = SR and get

ID1,2 = SR

2CC (5a)

ID8 = SR(CC + CL) = 2

(1 + CL

CC

)ID1,2 (5b)

Remembering that gm = 2√

Kn,p(W/L)ID where(Kn,p = µn,pCox/2), from equation (5a) the aspect ratioof transistors M1 and M2 is(

W

L

)1,2

= g2m1,2

4KN ID1,2(6)

For a two-stage amplifier in which the frequency be-havior can well be assumed with a single non-dominantpole (i.e., a single second pole), the phase margin is ex-pressed by

M� = 90◦ − arctanfGBW

fSP(7)

Two-Stage CMOS Transconductance Operational Amplifiers 181

where, due to the pole-splitting effect, the frequency atwhich the second pole occurs, fSP, is

fSP = gm5

2πCL(8)

Therefore, the transconductance gain of M5 results

gm5 = 2π fGBWCL tg(Mφ) (9)

and, since ID5 = ID8, its aspect ratio is(W

L

)5

= g2m5

4K P ID8(10)

Once the transconductance of transistor M5 isknown, we also can find the value of the resistance RC

that compensates for the right half-plane zero causedby the forward path to the output. This resistance canbe implemented with a MOS transistor in triode regionand is given by

RC = 1

gm5(11)

For two-pole amplifiers, it can be useful to definethe separation factor, K , between the second pole andthe gain-bandwidth product

K = fSP

fGBW(12)

When the amplifier phase margin is greater than 45◦,fGBW is equal to fT and parameter K is equal to the tan-gent of the phase margin. For instance, a phase marginof 60◦ means a K value of about 1.7.

Using equations (3), (8) and (12), the compensationcapacitor can also be expressed as

CC = Kgm1,2

gm5CL (13)

As far as transistors M3 and M4 is concerned, theycontribute to the systematic offset and CMRR, besidesaffecting noise performance according to equation (1).In order to improve both offset and CMRR, accuratematching must be guaranteed by both a proper layoutdesign and symmetrical bias conditions. This meansthe same drain-source voltages, other than the sameaspect ratios. Consequently, we must set

VGS3 = VDS4 = VGS5 (14)

which gives(W

L

)3,4

= ID3,4

ID5

(W

L

)5

(15)

Starting from equation (15), we can define the lengthand hence the width of transistors M3 and M4 follow-ing different requirements. Setting minimal length tominimize silicon area or setting high channel length tominimize flicker noise.

Other useful relations to complete the design canbe obtained by considering positive and negative CMRand/or OS, which are together linked since from equa-tion (15) VDSsat3,4 = VDSsat5 and VDSsat7 = VDSsat8 (notethat VGS7 = VGS8). Saturation drain-source voltageshave typical values in the range of 50–350 mV and aregiven by

VDSsat = √ID/[Kn,p(W/L)] (16)

Therefore, assuming the analog ground equal to half thepower supply (i.e., VDD/2) for the positive and negativeoutput swings we get

OS + = VDD

2− |VDSsat5| (17a)

OS− = VDD

2− VDSsat8 (17b)

and for the input common mode voltages

CMR+ = VDS1,2 − VDSsat1,2 = VDD − |VGS3,4,5|−

(VDD

2− VGS1,2

)= VDD

2− |VDSsat3,4,5|

− |VTP| + VTN (18a)

CMR− = VDS7 − VDSsat7 = VDD

2− VGS1,2 − VDSsat7,8

= VDD

2− VDSsat1,2 − VTN − VDSsat7 (18b)

Hence, in order to satisfy both the two set of conditionswe have to chose

VDSsat3,4,5 = min{(VDD/2 − |VTP| + VTN

− CMR+), (VDD/2 − OR+)} (19a)

VDSsat7,8 = min{(VDD/2 − VTN + VDSsat1,2

− CMR−), (VDD/2 − OR−)} (19b)

Of course, VDSsat3,4,5 are previously set on the base ofslew rate, phase margin, gain-bandwidth, and matchingrequirements. Therefore, if VDSsat3,4,5 does not meetthe input and/or output positive swing requirements, ahigher aspect ratio must be set for transistors M3-M5which gives better phase margin but higher area andnoise contribution.

Being currents ID7 and ID8 known, from equa-tion (19b) we can determine the aspect ratio of tran-sistors M7 and M8.

182 Palmisano, Palumbo and Pennisi

Table 1. Summary of the design flow.

PerformanceParameters

DesignParameters

Noise

fGBW

SRINT

SREXT

M�

gm1,2

CC

ID1,2

ID8

gm5

VGS3 = VDS4 = VGS5

VDSsat7

VDSsat8

(W/L)1,2

ID7

ID5

(W/L)5

(W/L)3,4

(W/L)7

(W/L)8

(W/L)6

IB

Are Setby

Systematic offset

OS

CMR

Finally, since the drain-source saturation voltage ofM6 is equal to VDSsat7,8, we have a degree of freedom insetting current IB and the aspect ratio of M6, accordingto the following equation

IB = (W/L)6

(W/L)7ID7 (20)

The design flow, which relates the performance tothe design parameters, is summarized in Table 1.

B. Simulations

In order to evaluate the accuracy of proposed proce-dure, the two-stage OTA in Fig. 1 has been designedby using a standard 1.2-µm CMOS technology whichhas the main following process parameters:

KN = 30 µA/V2, K P = 10 µA/V2,

VT N = −VT P = 0.75 V.

The target specification is reported in the first col-umn of Table 2. The requirement in terms of dc gainand CMRR are set on the base of the topology ratherthan on the design approach, as mentioned before. Fur-thermore, a load capacitor, CL , equal to 4 pF has beenassumed.

Using the design procedure outlined in Section II,we have determined the values of transistor aspect ra-

Table 2. Main electrical parameters of the OTA in Fig. 1.

Parameters Target Simulated

DC Gain >60 dB 67 dBfGBW 10 MHz 12 MHzM� 60◦ 59◦Slew rate 10 V/µs 11.5 V/µsInput white noise 10 nV/

√Hz 13 nV/

√Hz

Systematic offset 0 V 0.1 mVOS ≥2 V 2 VCMR ≥1.2 V 1.2 VCMRR >70 dB 78 dB

Table 3. Component values for the OTA in Fig. 1.

Parameters Value Unit

IB 18 µAM1 M2 28/1.2M3 M4 17/1.2M5 75/1.2

µm/µmM6 7/1.2M7 14/1.2M8 33/1.2CC 3.5 pFRC 2.3 k

tios, bias currents, compensation capacitor and nullingresistor which are shown in Table 3.

In order to confirm the expected performance,SPICE simulations using LEVEL 2 models and

Two-Stage CMOS Transconductance Operational Amplifiers 183

Fig. 2. Loop-gain frequency response of OTA in Fig. 1.

including device areas and perimeters have been car-ried out.

Fig. 2 illustrates the frequency response whichshows a dc gain, a gain-bandwidth product and a phasemargin of 67 dB, 9 MHz and 67◦, respectively. These re-sults are very close to the target values. A step responsein unity-gain configuration is depicted in Fig. 3. The ac-curate agreement between the expected and simulatedslew rate is apparent. Table 2 summarizes the main tar-get and simulated parameters.

III. Optimized Design Approaches

With the previous approach, the maximum achievablegain-bandwidth is limited by the second pole,gm5/2πCL , that depends on the load capacitor CL .Therefore, to achieve a high gain-bandwidth producta very high gm5 value is required. However, it has beenshown that it is possible to take advantage of techniquesfor compensation of the right half-plane zero to obtain

a better frequency response. The original of these tech-niques was applied to NMOS opamps [15] and then toCMOS opamps [16]. It breaks the forward path throughthe compensation capacitor by introducing a voltagebuffer in the compensation branch. Another solutionuses a current buffer to break this forward path [17].Optimized versions of these techniques, as well as ofthat employing the nulling resistor, were discussed in[18–20].

In this section we will give procedures which op-timize the gain-bandwidth product while keeping un-changed as much as possible all the remaining electricalparameters previously set.

A. Nulling Resistor Approach

In this approach the left half-plane zero introduced bythe nulling resistor RC in Fig. 1,

fz = 1

2π

gm5

(gm5 RC − 1) CC,

184 Palmisano, Palumbo and Pennisi

Fig. 3. Step response of the OTA in unity-gain configuration.

is exploited to compensate for the second pole givenin equation (8). Therefore, the compensation sets thefollowing condition

gm5

CL= gm5

(gm5 RC R − 1) CC R(21)

where CC R and RC R are the new compensation capac-itor and resistor, respectively.

Once this compensation is achieved, the new secondpole is [18]

fSP = 1

2π RC RCo1(22)

where Co1 is the equivalent capacitance at the outputof the first stage and is equal to Cdb2 + Cdb4 + Cgs5.

This second pole does not depend on the load ca-pacitance, hence a higher gain-bandwidth product canbe reached.

The final task is to choose the dominant pole (orequivalently fGBW ) in order to provide the desired phasemargin.

Substituting equations (3) and (22) in equation (12)the new expression of K is

K = CC R

gm1,2 RC RCo1(23)

Assigned the value of K (i.e., the phase margin),from equations (21) and (23) we get CC R and RC R ,that are

CC R = Kgm1,2

2gm5Co1

(1 +

√1 + 4

gm5

gm1,2

CL

Co1

)

∼= K

√gm1,2

gm5Co1CL (24a)

RC R = 1

2gm5

(1 +

√1 + 4

gm5CL

K gm1,2Co1

)

∼=√

CL

K gm1,2gm5Co1(24b)

where the approximations hold for CL greater than Co1.

Two-Stage CMOS Transconductance Operational Amplifiers 185

Equation (24a) shows that the compensation capac-itor is now approximately proportional to the geomet-ric media of Co1 and CL and hence is lower than thatin equation (13). Therefore, the optimized approachwith nulling resistor provides a higher gain-bandwidthproduct.

B. Voltage Buffer Approach

Let us consider the compensation technique which usesa voltage buffer to break the forward path throughthe compensation branch. Usually, the simple commondrain in Fig. 4 is employed and connected betweennodes A and OUT in Fig. 1. Taking into account forthe finite output resistance of the buffer which is aboutequal to 1/gm9V , the compensation branch introducesa left half-plane zero at fz = gm9V /2πCCV .

Therefore, a pole-zero compensation with the orig-inal second pole is achieved by setting

gm5

CL= gm9V

CCV(25)

The compensation is highly accurate since it onlydepends on matching tolerances between transconduc-tances and capacitors. Using this technique, the newsecond pole is

fsp = gm9V

2πC ′o1

(26)

where C ′o1

∼= Co1 +Cgs9V is the equivalent capacitanceat the output of the first stage. The separation factor isgiven by

K = gm9V

gm1,2

CCV

C ′o1

(27)

I BV

M9V

CCV

VDD

A

OUT

VSS

I BC

VSS

Vbias

I BC

VDD

A

M9C

CCC

(a) (b)

OUT

Fig. 4. Voltage buffer (a) and current buffer (b) compensation blocks.

Since the actual value of C ′o1 is unknown (it depends

on the aspect ratio of transistor M9V that has to be stillcomputed), evaluation of the exact solution for gm9V

and CCV needs an iterative method. However, to pro-vide a high second pole a small geometrical dimensionfor M9V has to be set. Hence, we can neglect Cgs9V

with respect to Co1 and solve equations (25) and (27)for CCV and gm9V . It results

CCV∼=

√K

gm1,2

gm5Co1CL (28a)

gm9V∼=

√K gm5gm1,2

Co1

CL(28b)

It is apparent from equations (24a) and (28a), that theapproaches based on nulling resistor and voltage buffergive the same compensation capacitor and hence thesame gain-bandwidth product. However, a voltagebuffer in the compensation branch greatly reduces theoutput swing preventing its use in many practical cases.

C. Current Buffer Approach

Let us consider the compensation technique which usesa current buffer to break the forward path through thecompensation branch. At this purpose, the commongate in Fig. 4b can be used which is connected be-tween nodes A and OUT in Fig. 1. In this case theopen-loop gain is characterized by a dominant pole, azero (given by gm9C/2πCCC ), and two complex andconjugate poles. A detailed treatment of this subjectcan be found in [20] where it is demonstrated that thegain-bandwidth product optimization is achieved bysetting

gm9C = 2gm1,2 (29a)

and

CCC∼=

√gm12

gm5

(2K − 1

2 + K+ 1

2

)CLCo1 (29b)

Assuming similar electrical parameters, phase mar-gin and load capacitance, capacitance CCC is slightlylower than capacitance CCV and hence the gain-bandwidth product in this last case is the highest amongthe optimized approaches.

Moreover, the optimization using current bufferpreserves the original output swing. Finally, a betterimplementation of this approach can be achieved by

186 Palmisano, Palumbo and Pennisi

using a cascode differential stage instead of a simpledifferential stage and taking advantage one of the twocommon gates.

D. Final Remarks

The frequency limitation of the current mirror M3-M4,which performs the differential to single ended conver-sion [21–22], introduces a pole-zero doublet with thezero higher than the pole by an octave.

The doublet can be neglected in the traditional de-sign described in Section II, but must be considered inthe optimized approaches due to the high value of thegain-bandwidth product.

Since the pole and zero are close one to each other,the doublet does not appreciably modify the transitionfrequency but it can greatly affect the phase margin.From a design point of view, it can be shown that tak-ing into account the pole-zero means a larger compen-sation capacitor which in turn leads to a smaller gain-bandwidth product [23–24]. The new gain-bandwidthproduct, fNGBW , is approximately given by [23–24]

fNGBW∼= 2 fsp f 2

d

K fd(2 fd + fsp)(30)

where fd is the pole frequency of the doublet and isequal to gm3,4/2π2Cgs4.

Therefore, the new compensation capacitor, CNC,which provides the desired phase margin is given by

CNC = fGBW

fNGBWCC (31)

E. Simulations

We have worked out three design examples to validatethe optimized approaches. The same data of the nu-meric example in Section II have been used, settingthe value of K to 2 (i.e., a phase margin of 63◦). Fromequations (24), (28) and (29), with Co1 = 168 fF givenfrom the previous design, the following values for thecompensation network components are obtained

CC R = 0.7 pF and RC R = 10.8 k

CCV = 0.7 pF and gm9V = 1 × 10−4 A/V

CCC = 0.6 pF and gm9C = 4.3 × 10−4 A/V

Table 4. Component values for the voltage and current buffer.

Parameters Value Unit

IBV 18 µAM9V 7/1.2 µm/µmIBC 36 µAM9C 50/1.2 µm/µm

Table 5. Calculated and simulated parameters for the optimizeddesigns.

OptimumExpected Simulateda Simulatedb

Compensation fGBW M� fGBW M� fGBW M�

Method (MHz) (deg.) (MHz) (deg.) (MHz) (deg.)

Resistance 32 63 41 51 38 57.5Voltage buffer 39 63 38 48 36.5 54Current buffer 41 63 47.5 42 44 56

aWithout taking into account the pole-zero doublet.bTaking into account the pole-zero doublet.

which refer to the nulling resistor, the voltage bufferand the current buffer compensation approaches,respectively.

The amplifiers have been designed using these val-ues, the aspect ratios of transistors M1–M8 and currentIB in Table 3, and the component values for the volt-age and current buffer in Table 4. Real active loadshave been used for the current generators in Fig. 4.The expected and simulated gain-bandwidth and phasemargin are reported in columns 1 and 2 of Table 5, re-spectively. The simulated values show a phase marginwhich is in all cases lower than the expected one anddiffers by about 15 degrees for the voltage buffer. Thisdeviation is mainly caused by the pole-zero doubletthat is not taken into account in the calculated perfor-mance. Actually, the doublet pole frequency is around350 MHz in our designs and affects mainly the phasemargin as mentioned before.

Remembering the remarks in subsection D, we canaccount for the pole-zero doublet by considering alower gain-bandwidth product and hence a new com-pensation capacitance, leaving unchanged the phasemargin (see equations (28) and (29)). The new com-pensation capacitances are nearly equal to 0.9 pF forthe three designs. After this optimization, the simulatedresults are shown in the third column of Table 5 whichgood agree the expected ones.

Of course, gain-bandwidth products as high as 40MHz are the ultimate performance for a two-stageamplifier with the selected 1.2 µm-CMOS process. At

Two-Stage CMOS Transconductance Operational Amplifiers 187

Fig. 5. Frequency responses of the loop-gain for the optimized compensation techniques: (⁄ ) nulling resistor, (�) voltage buffer and (∇) currentbuffer.

this frequency we should consider second-order effectssuch as the pole-zero doublet due to the source-coupledpair and mainly the uncompensated half-plane zero dueto the gate-drain capacitance of transistor M5. How-ever, the last results in Table 5 are, without any doubt,an optimum starting point for a further optimization.

Fig. 5 illustrates the frequency response of the threeamplifiers. The loss of 4.5 dB in the gain of the am-plifier compensated with the current buffer is due tothe finite output resistance of the upper current gener-ator in Fig. 4b. The original gain can be restored byadopting the alternative implementation suggested insubsection C .

IV. Conclusions

A general approach for the design of two-stage CMOStransconductance amplifiers has been presented. It isbased on first-order transistor models and provides sim-ple equations for an accurate pencil-and-paper standard

design. Despite its simplicity, the proposed strategyallows calculated performance to be closely in agree-ment with the simulated one.

Optimized designs for high gain-bandwidth productare also discussed which use typical frequency com-pensation techniques.

The proposed approach is a valid aid for analogdesigners and, especially for the standard design proce-dure, it can well be integrated into an analogknowledge-based CAD tool.

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Palmisano was born in Lampedusa, Italy, in 1956.He graduated in 1982 with a degree in Electronics En-gineering at the University of Pavia, Italy. From 1983to 1991, he research there, as researcher, at the Depart-ment of Electronics, in the field of CMOS and BiCMOSanalog integrated circuits. In 1992, he was visiting pro-fessor at UAM (Universidad Autonoma Metropolitana)in Mexico City where he held a course on microelec-tronics for the doctoral students. In 1993 and 2000,he joined the Faculty of Engineering at the Universityof Catania as Associate Professor and Full Professor,respectively, teaching Microelectronics.

Since 1995, he has been a consultant for STMicro-electronics in the design of RF integrated circuits forportable communications equipment.

He has designed several innovative analog circuitssuch as operational amplifiers, switched-capacitor fil-ters, A/D and D/A converters, within the frameworkof national and European research projects, as wellas several integrated circuits for both the base-bandand the RF front-end of mobile communications sys-tems, within research collaborations with electronicsindustries.

He is co-author of more than 100 papers in inter-national journals and conference proceedings, a bookon current operational amplifiers, and several interna-tional patents.

His current research interests include low-voltageamplifiers and RF integrated circuits.

Two-Stage CMOS Transconductance Operational Amplifiers 189

Palumbo was born in Catania, Italy, in 1964. Sincethe middle of 1987 he worked at the Instituto Elet-trico e Elettronico” of the University of Catania, to-wards its laurea degree whose main topic was the de-sign of electronic circuits by means expert systems. Hereceived the laurea degree in Electrical Engineeringand the Ph.D. degree from the University of Catania in1988 and 1993, respectively. In 1989 he was awardedwith a grant by AEI of Catania. In 1993, he conductedthe course on Electronic Devices for diploma degree inElectronics Engineering, and now he teaches a courseon Electronics for Digital Systems and a first course ofElectronics. In 1994, he joined the Department of Elec-trical Electronics and System (DEES) at the Universityof Catania as a researcher, and in 1997 he became anassociate professor. Now he is a full professor at thesame department.

His primary research interest was analog circuitswith particular emphasis on feedback circuits, compen-sation techniques, current-mode approach, low-voltagecircuits. Recently, his research involves digital circuitswith emphasis on high performance digital circuit. Inthese fields he is developing some the research activitiesin collaboration with ST microelectronics of Catania.

He is co-author of the book CMOS Current Ampli-fiers, Kluwer Academic Publishers, 1999. Moreover,he is author or co-author of more than 130 scientific

papers on referred international journals and confer-ences. He is serving as an Associated Editor of theIEEE Transaction on Circuits and Systems part I. Prof.Palumbo is an IEEE Senior Member.

Salvatore Pennisi was born in Catania, Italy, in1965. He received the laurea degree in ElectronicsEngineering in 1992, and in 1997 the Ph.D. degreein Electrical Engineering, both from the University ofCatania. In 1996 he joined the Faculty of Engineering,University of Catania, as a researcher, and from 1999 heteaches a course on electronics. His primary researchinterests include CMOS analog design with emphasison current-mode techniques. In this field he developedvarious innovative building blocks and unconventionalarchitectures of operational amplifiers. More recently,his research activity involves low-voltage/low-powercircuits and multi-stage amplifiers (with related opti-mized compensation techniques), and IF CMOSblocks. Dr. Pennisi is co-author of more than 50 publi-cations on international journals and conferences, of ascientific monograph titled CMOS Current Amplifiers(Kluwer Academic Publishers, 1999), and has con-tributed to the Wiley Encyclopedia of Electrical andElectronics Engineering (Wiley & Sons, 1999).