design organization and parameterization
DESCRIPTION
Design Organization and Parameterization. Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University. Outline. Definition and usage of subprograms Packaging parts and utilities Design Parameterization Design Configuration - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/1.jpg)
Design Organization and Parameterization
Instructors: Fu-Chiung Cheng
(鄭福炯 )Associate Professor
Computer Science & EngineeringTatung University
![Page 2: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/2.jpg)
Outline
• Definition and usage of subprograms• Packaging parts and utilities• Design Parameterization• Design Configuration• Design Libraries
![Page 3: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/3.jpg)
Design Organization and Parameterization
Functional design of a digital system is often done independently of the physical characteristics or technology in which design is being implemented
Based on technology, power consumption, speed, and temperature range, components are categorized into various libraries from which designs choose specific components
To support such design environments, VHDL provides language constructs for parameterizing and customizing designs and for definition and usage of libraries.
![Page 4: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/4.jpg)
Design Organization and Parameterization
definition and usage of libraries:– Library– Use clause– Package
customizing designs– Configuration declarations
parameterizing designs – By use of generic parameters, VHDL allows a desig
n to be parameterized such that the specific timing, number of bits or even the wiring is determined when the design is configured
![Page 5: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/5.jpg)
Chapter focuses
Subprograms: functions and procedures Library packages Design parameterization Design configuration
![Page 6: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/6.jpg)
Definition and Usage of Subprograms
Single bit comparator
GT Equation a_gt_b = a . gt + b' . gt + a . b'
EQ Equation a_eq_b = a . b . eq + a' . b' . eq
LT Equation a_lt_b = b . lt + a' . lt + b . a'
![Page 7: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/7.jpg)
Use functions in place of Boolean Expressions
ARCHITECTURE functional OF bit_comparator ISFUNCTION fgl (w, x, gl : BIT) RETURN BIT ISBEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);END fgl;FUNCTION feq (w, x, eq : BIT) RETURN BIT ISBEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);END feq;
BEGINa_gt_b <= fgl (a, b, gt) AFTER 12 NS;a_eq_b <= feq (a, b, eq) AFTER 12 NS;a_lt_b <= fgl (b, a, lt) AFTER 12 NS;
END functional;
![Page 8: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/8.jpg)
Definition and Usage of functions
![Page 9: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/9.jpg)
ARCHITECTURE structural OF nibble_comparator ISCOMPONENT comp1PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);END COMPONENT;FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional);CONSTANT n : INTEGER := 4;SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);
BEGIN-- next pageEND structural;
![Page 10: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/10.jpg)
ARCHITECTURE structural OF nibble_comparator IS-- previous pages
BEGINc_all: FOR i IN 0 TO n-1 GENERATEl: IF i = 0 GENERATEleast: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );END GENERATE;m: IF i = n-1 GENERATEmost: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),a_gt_b, a_eq_b, a_lt_b);END GENERATE;r: IF i > 0 AND i < n-1 GENERATErest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),im(i*3+0), im(i*3+1), im(i*3+2) );END GENERATE;END GENERATE;
END structural;
![Page 11: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/11.jpg)
Definition and Usage of Procedures
Defining a procedure as test benchapply_data (a,
00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS);
apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
Feed a and b with 13 integers each
![Page 12: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/12.jpg)
ARCHITECTURE procedural OF nibble_comparator_test_bench IS
TYPE integers IS ARRAY (0 TO 12) OF INTEGER;
PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME) IS
VARIABLE j : INTEGER;
VARIABLE tmp, pos : INTEGER := 0;
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGIN
…
END procedural;
![Page 13: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/13.jpg)
ARCHITECTURE procedural OF nibble_comparator_test_bench IS ….BEGIN
FOR i IN 0 TO 12 LOOPtmp := values (i); j := 0;WHILE j <= 3 LOOP
IF (tmp MOD 2 = 1) THEN buf (j) := '1';ELSE buf (j) := '0';END IF;tmp := tmp / 2;j := j + 1;
END LOOP;target <= TRANSPORT buf AFTER i * period;
END LOOP;END apply_data;
![Page 14: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/14.jpg)
COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0);gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);END COMPONENT;FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural);SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);SIGNAL eql, lss, gtr : BIT;SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0';BEGINa1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);apply_data (a, 00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS);apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END procedural;
![Page 15: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/15.jpg)
Simulation reportTIME SIGNALS==== ============================(NS) a(3:0) b(3:0) gtr eql lss0 "0000" "0000" '0' '0' '0'48 ...... ...... ... '1' ...500 "1111" "1110" ... ... ...548 ...... ...... '1' '0' ...1500 "1110" "1111" ... ... ...1548 ...... ...... '0' ... '1'2500 ...... "1100" ... ... ...2536 ...... ...... '1' ... '0'3500 "1010" ...... ... ... ...3524 ...... ...... '0' ... '1'4000 "0000" "1111" ... ... ...4500 "1111" ...... ... ... ...4548 ...... ...... ... '1' '0'5000 "0000" ...... ... ... ...5012 ...... ...... ... '0' '1'5500 ......
![Page 16: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/16.jpg)
Details of a subprogram body
![Page 17: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/17.jpg)
Loop statement with FOR iteration scheme
![Page 18: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/18.jpg)
If statement
![Page 19: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/19.jpg)
Utility Procedures
Procedures or functions such as – Binary to integer– Integer to binary
are very useful. They can be grouped as a library. They can be reused.
![Page 20: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/20.jpg)
Binary to Integer Conversion
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) ISVARIABLE result: INTEGER;
BEGINresult := 0;FOR i IN bin'RANGE LOOP -- ‘RANGE attribute makes
IF bin(i) = '1' THEN -- this a generic procedureresult := result + 2**i;END IF;
END LOOP;int := result;
END bin2int;
![Page 21: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/21.jpg)
Integer to Binary Conversion
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) ISVARIABLE tmp : INTEGER;
BEGINtmp := int;FOR i IN 0 TO (bin'LENGTH - 1) LOOP -- ‘LENGTH attribute
IF (tmp MOD 2 = 1) THEN -- is usedbin (i) := '1';
ELSE bin (i) := '0';END IF;tmp := tmp / 2;
END LOOP;
END int2bin;
![Page 22: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/22.jpg)
Procedures within procedure
PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);CONSTANT values : IN integers;CONSTANT period : IN TIME) IS
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGINFOR i IN 0 TO 12 LOOP
int2bin (values(i), buf);target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;
![Page 23: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/23.jpg)
Functions serve as utilities
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER ISVARIABLE result: INTEGER;
BEGINresult := 0;FOR i IN bin'RANGE LOOP
IF bin(i) = '1' THENresult := result + 2**i;
END IF;END LOOP;RETURN result;
END to_integer;
![Page 24: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/24.jpg)
Packaging Parts and Utilities
Component declarations as well as utilities can be packaged
A package declaration containing component declarations of simple gates
Eliminates the need for individual declarations
![Page 25: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/25.jpg)
Package Declaration
-- Packaging components
PACKAGE simple_gates ISCOMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2 PORT (i1: i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
END simple_gates;
![Page 26: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/26.jpg)
Package Declaration
PACKAGE basic_utilities ISTYPE integers IS ARRAY (0 TO 12) OF INTEGER;
FUNCTION fgl (w, x, gl : BIT) RETURN BIT;
FUNCTION feq (w, x, eq : BIT) RETURN BIT;
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER);
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR);
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME);
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER;
END basic_utilities;
![Page 27: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/27.jpg)
Package Definition
PACKAGE BODY basic_utilities ISFUNCTION fgl (w, x, gl : BIT) RETURN BIT ISBEGIN
RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
END fgl;FUNCTION feq (w, x, eq : BIT) RETURN BIT ISBEGIN
RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);
END feq;…. – next three pages
END basic_utilities;
![Page 28: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/28.jpg)
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS
VARIABLE result: INTEGER;
BEGIN
result := 0;
FOR i IN bin'RANGE LOOP
IF bin(i) = '1' THEN
result := result + 2**i;
END IF;
END LOOP;
int := result;
END bin2int;
![Page 29: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/29.jpg)
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS
VARIABLE tmp : INTEGER;
VARIABLE buf : BIT_VECTOR (bin'RANGE);
BEGIN
tmp := int;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF (tmp MOD 2 = 1) THEN
bin (i) := '1';
ELSE bin (i) := '0'; END IF;
tmp := tmp / 2;
END LOOP;
END int2bin;
![Page 30: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/30.jpg)
PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);CONSTANT values : IN integers; CONSTANT period : IN TIME) ISVARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGINFOR i IN 0 TO 12 LOOP
int2bin (values(i), buf);target <= TRANSPORT buf AFTER i * period;
END LOOP;END apply_data;FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result: INTEGER;BEGIN
result := 0;FOR i IN bin'RANGE LOOP
IF bin(i) = '1' THEN result := result + 2**i;END IF;
END LOOP;RETURN result;
END to_integer;
END basic_utilities;
![Page 31: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/31.jpg)
Using functions in packages
USE WORK.basic_utilities.ALL;ARCHITECTURE functional OF bit_comparato
r ISBEGIN
a_gt_b <= fgl (a, b, gt) AFTER 12 NS;a_eq_b <= feq (a, b, eq) AFTER 12 NS;a_lt_b <= fgl (b, a, lt) AFTER 12 NS;
END functional;
![Page 32: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/32.jpg)
USE WORK.basic_utilities.ALL;ARCHITECTUR procedural OF nibble_comparator_test_benc
h ISCOMPONENT comp4 PORT (
a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT;a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural);SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);SIGNAL eql, lss, gtr : BIT;SIGNAL vdd : BIT := '1';SIGNAL gnd : BIT := '0';
BEGINa1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);apply_data (a, 0&15&15&14&14&14&14&10&00&15&00&00&15, 500 N
S);apply_data (b, 0&14&14&15&15&12&12&12&15&15&15&00&00, 500 N
S);
END procedural;
![Page 33: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/33.jpg)
Aggregate for elements of the array
ALTERNATIVE: use aggregate operation
apply_data (a, (00,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS);
apply_data (b, (00,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);
![Page 34: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/34.jpg)
Design Parametrization
Component models can be parameterized to better utilize gate or component models and to make general models usable in different design environments
VHDL: generic parameters Generic parameters: timing, delay When a parameterized gate is used, its generic
(parameters) values are passed to the parameters
![Page 35: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/35.jpg)
Parametrized Inverter
ENTITY inv_t ISGENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;--ARCHITECTURE average_delay OF inv_t ISBEGIN
o1 <= NOT i1 AFTER (tplh + tphl) / 2;END average_delay;
![Page 36: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/36.jpg)
Parametrized 2-input NAND Gate
ENTITY nand2_t ISGENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS);PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2_t;--ARCHITECTURE average_delay OF nand2_t ISBEGIN
o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;END average_delay;
![Page 37: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/37.jpg)
Parametrized 3-input NAND Gate
ENTITY nand3_t ISGENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS);PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);
END nand3_t;--ARCHITECTURE average_delay OF nand3_t ISBEGIN
o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2;END average_delay;
![Page 38: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/38.jpg)
Entity declaration of with generics
![Page 39: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/39.jpg)
Graphical representation with generics
• Port association and generic association must be donewhen used
![Page 40: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/40.jpg)
ARCHITECTURE default_delay OF bit_comparator ISCOMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT;FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);-- Intermediate signalsSIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN-- a_gt_b outputg0 : n1 PORT MAP (a, im1);g1 : n1 PORT MAP (b, im2);g2 : n2 PORT MAP (a, im2, im3);g3 : n2 PORT MAP (a, gt, im4);g4 : n2 PORT MAP (im2, gt, im5);g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);….
END default_delay;
Use default delays
![Page 41: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/41.jpg)
ARCHITECTURE fixed_delay OF bit_comparator ISCOMPONENT n1GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT);END COMPONENT;COMPONENT n2GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT);END COMPONENT;COMPONENT n3GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT);END COMPONENT;FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;BEGIN-- a_gt_b output….-- a_eq_b output…-- a_lt_b outputEND fixed_delay;
![Page 42: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/42.jpg)
BEGIN-- a_gt_b outputg0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1);g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2);g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3);g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4);g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5);g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b);-- a_eq_b outputg6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6);g7 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (a, b, eq, im7);g8 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im6, im7, a_eq_b);-- a_lt_b outputg9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8);g10 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, lt, im9);g11 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (b, lt, im10);g12 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im8, im9, im10, a_lt_b);
END fixed_delay;
![Page 43: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/43.jpg)
Component instantiation statement with generic map
Generic map aspect comes first
![Page 44: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/44.jpg)
Bit comparator with timing parameters
ENTITY bit_comparator_t ISGENERIC (tplh1, tplh2, tplh3, tphl1, tphl2, tphl3 : TIME);
PORT (a, b, -- data inputs
gt, -- previous greater than
eq, -- previous equal
lt : IN BIT; -- previous less than
a_gt_b, -- greater
a_eq_b, -- equal
a_lt_b : OUT BIT); -- less than
END bit_comparator_t;
![Page 45: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/45.jpg)
ARCHITECTURE passed_delay OF bit_comparator_t ISCOMPONENT n1GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT);END COMPONENT;COMPONENT n2GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT);END COMPONENT;COMPONENT n3GENERIC (tplh, tphl : TIME);PORT (i1, i2, i3: IN BIT; o1: OUT BIT);END COMPONENT;FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);-- Intermediate signalsSIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
![Page 46: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/46.jpg)
-- a_gt_b outputg0 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (a, im1);g1 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (b, im2);g2 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, im2, im3);g3 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, gt, im4);g4 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im2, gt, im5);g5 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im3, im4, im5,a_gt_b);-- a_eq_b outputg6 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im1, im2, eq, im6);g7 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (a, b, eq, im7);g8 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im6, im7, a_eq_b);-- a_lt_b outputg9 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, b, im8);g10 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, lt, im9);g11 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (b, lt, im10);g12 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im8, im9, im10,a_lt_b);
END passed_delay;
![Page 47: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/47.jpg)
Page 174Fig 6.26
![Page 48: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/48.jpg)
ARCHITECTURE iterative OF nibble_comparator ISCOMPONENT comp1GENERIC (tplh1 : TIME := 2 NS; tplh2 :TIME := 3 NS; tplh3 : TIME := 4 ns;) PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);END COMPONENT;FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_delay);SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGINc0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));c1to2: FOR i IN 1 TO 2 GENERATEc: comp1 PORT MAP(a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) );END GENERATE;c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8),
a_gt_b, a_eq_b, a_lt_b); -- default valuesEND iterative;
Fig 6.27 mistake
![Page 49: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/49.jpg)
Associated with OPEN (default)
ARCHITECTURE iterative OF nibble_comparator IS
. . .
BEGIN
c0: comp1 -- Association by position,GENERIC MAP (OPEN, OPEN, 8 NS, OPEN, OPEN, 10 NS)
PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
. . .
END iterative;
![Page 50: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/50.jpg)
Named association
ARCHITECTURE iterative OF nibble_comparator IS
. . .
BEGINc0: comp1
GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)
PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
. . .
END iterative;
same as the previous slide (others are defaults)
![Page 51: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/51.jpg)
Named association
PORT AS DECLARED:PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
ARCHITECTURE BECOMES:ARCHITECTURE iterative OF nibble_comparator IS. . .BEGIN
c0: comp1GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)PORT MAP (a => a(0), b => b(0), gt => gt, eq => eq, lt => lt,a_gt_b => im(0), a_eq_b => im(1), a_lt_b => im(2));
. . .END iterative;
![Page 52: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/52.jpg)
Named association
Rule: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open, inputs only if defa
ult
![Page 53: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/53.jpg)
A customizable test benchUSE WORK.basic_utilities.ALL;ARCHITECTURE customizable OF nibble_comarator_test_be
nch ISCOMPONENT comp4 PORT (
a, b : IN BIT_VECTOR (3 DOWNTO 0); gt, eq, lt : IN BIT;a_gt_b, a_eq_b, a_lt_b : OUT BIT); -- use which implementation?
END COMPONENT; -- require configuration statementSIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);SIGNAL eql, lss, gtr : BIT;SIGNAL vdd : BIT := '1';SIGNAL gnd : BIT := '0';
BEGINa1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);apply_data (a, (0,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS);apply_data (b, (0,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);
END customizable;
![Page 54: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/54.jpg)
Configuring customizable for testing structural architecture of nibble_comparator
USE WORK.ALL;CONFIGURATION functional OF
nibble_comparator_test_bench ISFOR customizable
FOR a1 : comp4USE ENTITY
WORK.nibble_comparator(structural);END FOR;
END FOR;
END functional;
![Page 55: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/55.jpg)
Graphical representation
Use structural of nibble_comparator
![Page 56: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/56.jpg)
Configuring customizable for testing iterative architecture of nibble_comparator
USE WORK.ALL;CONFIGURATION average_delay OF
nibble_comparator_test_bench ISFOR customizable
FOR a1 : comp4USE ENTITY
WORK.nibble_comparator(iterative);END FOR;
END FOR;END average_delay;
No need to recompile the test bench
![Page 57: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/57.jpg)
Configuration Declaration
d
Configuration declaration replaces or adds to a configuration specification
![Page 58: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/58.jpg)
ARCHITECTURE flexible OF nibble_comparator ISCOMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGINc0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), i
m(2));c1to2: FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8),a_gt_b, a_eq_b, a_lt_b);
END flexible; • Which comp1 implementation is used? • general purpose nibble_comparator
![Page 59: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/59.jpg)
USE WORK.ALL;CONFIGURATION default_bit_level OF
nibble_comparator_test_bench ISFOR customizable
FOR a1 : comp4USE ENTITY WORK.nibble_comparator(flexible);FOR flexible
FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator (default_delay);END FOR;FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (default_delay); END FOR;END FOR;
END FOR;END FOR;
END FOR;
END default_bit_level;
![Page 60: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/60.jpg)
default_delay ofbit_comparator
flexible OF nibble_comparator
Fig 6.36
![Page 61: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/61.jpg)
USE WORK.ALL;CONFIGURATION fixed_bit_level OF nibble_comparator_tes
t_bench ISFOR customizable
FOR a1 : comp4USE ENTITY WORK.nibble_comparator(flexible);
FOR flexibleFOR c0, c3: comp1USE ENTITY WORK.bit_comparator (fixed_delay);END FOR;FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (fixed_delay); END FOR;END FOR;
END FOR;END FOR;
END FOR;
END fixed_bit_level;
Binding to the fixed_delay architecture
![Page 62: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/62.jpg)
USE WORK.ALL; -- See Fig 6.39CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS
FOR customizableFOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible);
FOR flexibleFOR c0, c3: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay)GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS,tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS);END FOR;FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR;END FOR;
END FOR;END FOR;
END FOR;END passed_bit_level;
Using configuration declarations for component bindings, and specification of generic parameters
![Page 63: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/63.jpg)
Fig 6.41
![Page 64: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/64.jpg)
ARCHITECTURE partially_flexible OF nibble_comparator ISCOMPONENT comp1PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT
BIT);END COMPONENT;FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_dela
y);SIGNAL im : BIT_VECTOR ( 0 TO 8 );
BEGINc0: comp1 PORT MAP ( . . . );c1to2 : FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP ( . . . );END GENERATE;
c3: comp1 PORT MAP ( . . . );END partially_flexible;
![Page 65: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/65.jpg)
USE WORK.ALL;CONFIGURATION incremental OF nibble_comparator_test_bench IS
FOR customizableFOR a1 : comp4 USE ENTITY WORK.nibble_comparator
(partially_flexible);FOR flexible
FOR c0, c3: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS);END FOR;FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6
NS); END FOR;END FOR;
END FOR;END FOR;
END FOR;END incremental;
![Page 66: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/66.jpg)
Unbound VHDL description of set-reset latch
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);END sr_latch;ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT);END COMPONENT;SIGNAL im1, im2, im3, im4 : BIT;
BEGINg1 : n2 PORT MAP (s, c, im1);g2 : n2 PORT MAP (r, c, im2);g3 : n2 PORT MAP (im1, im4, im3);g4 : n2 PORT MAP (im3, im2, im4);q <= im3;
END gate_level; -- Fig 6.44
![Page 67: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/67.jpg)
Unbound VHDL description of a D-latch
ENTITY d_latch IS PORT (d, c : IN BIT; q : OUT BIT);END d_latch;ARCHITECTURE sr_based OF d_latch IS
COMPONENT sr PORT (s, r, c : IN BIT; q : OUT BIT);END COMPONENT;COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT);END COMPONENT;SIGNAL dbar : BIT;
BEGINc1 : sr PORT MAP (d, dbar, c, q);c2 : n1 PORT MAP (d, dbar);
END sr_based; -- Fig 6.45
![Page 68: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/68.jpg)
Unbound VHDL description for an n-bit D-F/F
ENTITY d_register ISPORT (d : IN BIT_VECTOR; c : IN BIT; q : OUT BIT_VECTOR);
END d_register;ARCHITECTURE latch_based OF d_register IS
COMPONENT dl PORT (d, c : IN BIT; q : OUT BIT);END COMPONENT;
BEGINdr : FOR i IN d'RANGE GENERATE
di : dl PORT MAP (d(i), c, q(i));END GENERATE;
END latch_based; -- Fig 6.46
![Page 69: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/69.jpg)
USE WORK.ALL; -- see Fig 6.47CONFIGURATION average_gate_delay OF d_register IS
FOR latch_basedFOR dr
FOR di : dl USE ENTITY WORK.d_latch(sr_based);FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand2_t(average_delay) GENERIC MAP (5 NS, 6 NS); END FOR; FOR g1, g3 : n2 USE ENTITY WORK.nand2_t(average_delay) GENERIC MAP (2 NS, 4 NS); END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv_t(average_delay) GENERIC MAP (3 NS, 5 NS); END FOR;END FOR;
END FOR;END FOR;
END FOR;END average_gate_delay; -- Fig 6.48
![Page 70: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/70.jpg)
ARCHITECTURE single OF d_register_test_bench ISCOMPONENT reg PORT
(d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT;q : OUT BIT_VECTOR (7 DOWNTO 0) );
END COMPONENT;FOR r8 : reg USE CONFIGURATION WORK.single_gate_de
lay;SIGNAL data, outdata : BIT_VECTOR (7 DOWNTO 0);SIGNAL clk : BIT;
BEGINr8: reg PORT MAP (data, clk, outdata);data <= X"00", X"AA" AFTER 0500 NS, X"55" AFTER 1500
NS;clk <= '0', '1' AFTER 0200 NS, '0' AFTER 0300 NS,'1' AFTER 0700 NS, '0' AFTER 0800 NS,'1' AFTER 1700 NS, '0' AFTER 1800 NS;
END single; -- Fig 6.51
![Page 71: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/71.jpg)
ENTITY xor2_t IS
GENERIC (tplh : TIME := 9 NS; tphl : TIME := 7 NS);
PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END xor2_t;
ARCHITECTURE average_delay OF xor2_t IS
BEGIN
o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2;
END average_delay;
----
ENTITY inv_t IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;
ARCHITECTURE average_delay OF inv_t IS
BEGIN
o1 <= NOT i1 AFTER (tplh + tphl) / 2;
END average_delay; -- Fig 6.53 (library for Parity checking circuit)
![Page 72: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/72.jpg)
ENTITY parity ISPORT (a : IN BIT_VECTOR (7 DOWNTO 0); odd, even : OUT BIT);
END parity;--ARCHITECTURE iterative OF parity IS
COMPONENT x2 PORT (i1, i2: IN BIT; o1: OUT BIT);END COMPONENT;COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT);END COMPONENT;SIGNAL im : BIT_VECTOR ( 0 TO 6 );
BEGINfirst: x2 PORT MAP (a(0), a(1), im(0));middle: FOR i IN 1 TO 6 GENERATEm: x2 PORT MAP (im(i-1), a(i+1), im(i));END GENERATE;last: odd <= im(6);inv: n1 PORT MAP (im(6), even);
END iterative;
![Page 73: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/73.jpg)
CONFIGURATION parity_binding OF parity ISFOR iterative
FOR first : x2 USE ENTITY WORK.xor2_t (average_delay)GENERIC MAP (5 NS, 5 NS);END FOR;FOR middle (1 TO 5)
FOR m : x2 USE ENTITY WORK.xor2_t (average_delay)GENERIC MAP (5 NS, 5 NS);END FOR;
END FOR;FOR middle ( 6)
FOR m : x2 USE ENTITY WORK.xor2_t (average_delay)GENERIC MAP (6 NS, 7 NS);END FOR;
END FOR;FOR inv : n1 USE ENTITY WORK.inv_t (average_delay) GENERIC MAP (5 NS, 5 NS);END FOR;
END FOR;END parity_binding; -- Fig 6.55 Parity Circuit Design Configuration
![Page 74: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/74.jpg)
Design Library
Logic families or groups of components (i.e. libraries) are categorized according to their physical characteristics, price, complexity, usage, or other properties.
VHDL language supports the use of design libraries for categorizing components or utilities.
![Page 75: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/75.jpg)
Design Library
Existing VHDL Libraries:– STD:
STANDARD package: BIT, BIT_VECTOR, TIME, …. TEXTIO package
– IEEE: std_logic_1164 package: std_logic (All basic functions
are available in this package) numeric_std package: numeric_bit package:
– Work: The library current in use
![Page 76: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/76.jpg)
Design Library
Altera Max Plus II VHDL Libraries:– altera:
reg24 (pre-tested components)
– lpm: (Library of parameterized modules) lpm_and, lpm_or, …
![Page 77: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/77.jpg)
Multi-value Logic (std_logic)
Value Representing===== ==============='U' Uninitialized'X' Forcing Unknown'0' Forcing 0'1' Forcing 1'Z' High Impedance'W' Weak Unknown'L' Weak 0'H' Weak 1'-' Don't care
std_logic satisfies most hardware design needs
![Page 78: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/78.jpg)
AND table for std_logic type
![Page 79: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/79.jpg)
Use of Library
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;--ENTITY nand2_t IS
GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS);PORT (i1, i2 : IN std_logic; o1 : OUT std_logic);
END nand2_t;ARCHITECTURE average_delay_mvla OF nand2_t ISBEGIN
o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;END average_delay_mvla;
![Page 80: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/80.jpg)
Use of Library ls7400 (user-defined)
Ex1LIBRARY ls7400;USE ls7400.simple_gates.ALL;
Ex2LIBRARY ls7400;USE ls7400.ALL;
Ex3LIBRARY ls7400;USE ls7400.ALL;..… FOR g1, g3 : n2… USE ENTITY ls7400.nand2 (single_delay);… END FOR;
![Page 81: Design Organization and Parameterization](https://reader035.vdocuments.site/reader035/viewer/2022070418/56815a30550346895dc770af/html5/thumbnails/81.jpg)
Summary
Definition of subprograms Packaging utilities and components Design parameterization Design configuration