design of portable hearing aid based on fpga

978-1-4244-2800-7/09/$25.00 ©2009 IEEE ICIEA 2009

Design of Portable Hearing Aid based on FPGA Yang Min

(Electronic Engineering Department, College of Mechanical and Electrical Engineering Shanghai Normal University,

Shanghai China, 201418) [email protected]

Abstract: Aiming at incommodity of extent hearing aid in the

market, a new design of hearing aid is brought forward in this

paper. First, the system construction is discussed, the difference

between which and other hearing aids is it uses FPGA for voice

processing. Second, the application of FPGA and embedded soft

core Nios II is described, how to utilize SOPC builder explore

Nios II embedded processor and what’s the benefit. DSP

algorithm is also implemented in FPGA chip by Verilog HDL and

because of strong ability of parallel processing the system based

on FPGA runs faster than DSP chip does in signal processing.

Third, the practicability of this device is explained through

comparing with other hearing aids. The table shows the design

has fine market respect because of its small size, cheap price and

preferable operating performance.

Keywords: FPGA; Hearing Aid; Nios II; DSP;

I. INTRODUCTION

Hearing aid is widely used for people who are handicapped in audition. In China there are more than 40,000,000 people whose auditions have disability, including aged people and Children. They need some devices to help them communicate with the society, which is called hearing aid. There are many kinds of hearing aid in the market. Body hearing aid is the oldest style, which is made by analog circuit and has the cheapest price. There are a large number of customers all over the world such as China and America. Body hearing aid is easy to use, but its big bulk decides it can only be put into pocket, that isn't convenient and friction between box and pocket produces noises. The advantage of body hearing aid is not only its price, and also it has great power and seldom brings whistle. Since 1996 the first digital device was produced [1], digital hearing aids bloom and bring different choices to handicapped people. Digital device are made by logical circuit and work in

nonlinear area. They divide the range of self-frequency spectrum into a couple of bands so that they can make up for different audition loss. And most digital devices use low noise, low distortion component so they work better that analog ones. But their shapes are too tiny to use conveniently for old people since their hands are not so flexible sometimes. In this paper, we want to bring forward a design of digital hearing aid, which uses SOPC (System on Programmable Chip), concrete speaking, uses FPGA (Field Programmable Gate Array) with embedded software processor Nios II. This device promotes the advantages of Nios II so that it can easily cooperate with peripheral equipments and use DSP (Digital Signal Processing) to deal with voice signal through relevant simulation environment.

II. CHARACTERISTIC OF FPGA AND NIOS II

A. Why we should use FPGA

FPGA is a programmable logic device, evolving from simple programmable devices such as PROM (Programmable Read-Only Memory) PAL (Programmable Array Logic). The difference is FPGA use look-up table to implement all the logic function, which works like a small size memory. FPGA has high capacity and small bulk so that it is suitable for the design of miniaturized application system while its characteristic ability of programmable and re-configurable decreases the cost of exploitation.

In modern embedded technology MCU (Micro Controller Unit), FPGA and DSP play them important role, they have notable merits in special field. MCU is good at control and man-machine interface, FPGA is a nice choice for complicate logical design while DSP is good for mass data processing. But now with the improvement of FPGA manufacturing technology, MCU and DSP can be both embedded into a

1895

Authorized licensed use limited to: Gandhi Institute of Technology & Management. Downloaded on July 12,2010 at 16:04:38 UTC from IEEE Xplore. Restrictions apply.

FPGA chip. Technicians utilize SOPC builder to custom embedded controller, typically Nios II, and DSP builder to add data processing module. These tools make FPGA stronger so that it can handle almost all the applications in digital system design.

B. Nios II – an embedded soft core in FPGA

Nios II processor is a general-purpose RISC soft core provided by Altera in 2004. It has full 32-bit instruction set, data path, and address space. Inheriting all the advantages of Nios, Nios II can easily implement custom peripheral equipment and instructions. The Avalon bus is a unique technology used in FPGA, its most importance is solving bottleneck of bandwidth for every bus arbiter. Nios II can be loaded on certain families FPGA, basically technicians use assorted software circumstance including Quartus II, Nios II IDE and SOPC builder to explore the device, and then use software development environment based on the GNU C/C++ tool chain to write software program. After synthesizing the design and downloading it into FPGA chip, an embedded processor is produced.

Noteworthiness is Nios II has single-instruction 32*32 multiplication and division, 64-bit or 128-bit products of multiplication so that it is not inferior to DSP chip in mass data processing, even better. Construction of programmable DSP system can be built by DSP builder, and the function can be described by HDL (Hardware Describe Language).

III. DESIGN OF SYSTEM SCHEME

Digital hearing aid deals with voice through circuit so it often does in a fixed buildup. Block construction can be seen in figure 1. Microphone acquires voice and converts it into electronic signal. The next an analog to digital converter chip special for audio is needed. Then we get sampled voice. Ordinarily voice is sent into DSP chip, but this time we send it into FPGA chip. These two chips have similar functions; the difference is that FPGA has better performance and works faster than DSP chip though their parallel operation both base on highly pipeline[2]. Ripe algorithms such as FFT, IIR and FIR are proved many times faster running in FPGA than DSP. It is because FPGA implement the instructions by hardware.

In the part of signal processing, effort focus on dividing frequency, channels, automatic control of gain, how to eliminate background noise and how to compensate frequency response. In order to get basic information from low frequency and get details from high frequency we divide voice into two frequency band and do wave filtering individually, which is a general method. People often decide the frequency division point at about 1.7~2.2 KHz [4]. Volume adjustment depends on external potentiometer getting an analog input. De-noising and compensation of frequency response are hotspots in research of hearing aid because the output voice users hearing is clear or not depend on the algorithm. But the algorithms are not involved in this paper.

Figure1. Block construction of digital hearing aid

After processing the signal goes through a digital to analog audio converter and presents by speaker. Whistle is another troublesome problem in digital hearing aid. Since speaker is fixed too close to microphone, the output voice comes into microphone again and forms feedback that brings whistle. We compared different ways to decrease whistle, then we found that it is an unavoidable problem in digital hearing aid while it seldom occurs in body hearing aid just because the distance between microphone and speaker is long enough. So we decide to follow this way and improve it, which means we use ear-jack in the circuit so that people can use all-purpose long line earphone. Now whistle is solved.

IV. HOW TO ADD MODULES

Start SOPC builder to create a new Nios II system, which include Nios II processor and relevant peripherals. According to hearing aid’s usage requirement, we need chiefly add following modules, shown in figure 2.

• 32-bit CPU

• Timer

MIC A/D audio converter

FPGA

D/A audio converter

Speaker Nios II

Sampled Signal

Worked Signal

1896


• JTAG

• External Flash Interface

• Analog to Digital Converter Interface

• Digital to Analog Converter Interface

What we think about is how to make the hearing aid device has perfect performance and small bulk, so it doesn’t need too much input/output interface. In this system core chip is Cyclone II EP2C35F672, presented by Altera. The chip has 35,000 logic elements which is enough to implement the design.

Figure2. Internal Module in FPGA

32-bit CPU uses as master port because it is the core of control and algorithm. We want the device can be used in quiet circumstance; indoor circumstance and noise circumstance so several sets of algorithm different circumstances are needed for different conditions. A small size potentiometer suit for old people or children to select number for circumstance and parameters of algorithm are stored in external flash. A/D and D/A interface of audio plus potentiometer interface can be explained by verilog HDL and C program in Nios II IDE. DSP module is created by DSP builder and Matlab/ Simulink. After setting model in Simulink, we get Verilog file by SignalCompiler that can be used in Quartus II. That’s why DSP module is so easy to be embedded into FPGA. Avalon bus handles the communication among all the slave modules, since the interface modules obey the same regulation, we don’t need waste time in dealing with time sequence.

DSP is an important part in hearing aid, which directly decides the voice hearing from speaker. DSP can depart into two parts: hardware and software. We have constructed hardware circuit by setting modules with Nios II as described above, which has better ability of processing data than DSP chip does [2]. While we can’t use statements of DSP to control processing directly, we need custom instructions by DSP builder and Matlab/Simulink. Nios II have provided algorithm prototype for FFT and IIR. These custom-built instructions can be used in HDL file as library functions.

V. ANALYSIS OF PORTABLE HEARING AID’S

PRACTICABILITY

Hearing aid is the necessary for the hearing handicapped people and demand is so large. Since body hearing aid is cheap and easy to use, but it can’t bring good effect. On the other hand, advanced digital hearing aids have perfect performance but their high price scare most people away. My idea is to design a kind of digital hearing aid with cheap price, small size bulk and strong signal processing ability. FPGA is a good choice. After analyzing of basic indications we realize with the application of FPGA and Nios II, it is possible to turn this design into product. Indications comparison of different hearing aids is given in table 1. Let’s call it FPGA temporarily.

TABLE 1. Comparison of different hearing aids

styles portable De-noise whistle easy nursing price

Body × × × √ √ √

CIC √ √ √ × × ×

ITE √ √ √ × × ×

BTE √ √ √ × × ×

FPGA √ √ √ √ √ √

CIC- completely in the canal; ITE- in the canal; BTE- behind the ear

• Portable Except CIC, hearing aids are all visible whatever big or small. Body hearing aid is biggest and need to be put in pocket so it isn’t portable. Device based on FPGA has medium bulk because there are only one FPGA and few external converter chips. All the processing procedure is done in FPGA so that the circuit board becomes tiny, thin and light. With favorable appearance design we can hang it from the

Nios II 32-bit CPU

Avalon Switch Fabric

Timer

JTAG Potentiometer interface

A/D Interface

D/A Interface

Flash

DSP Module Interface

1897


neck just like MP3, which will be a better way to maintain the user’s self-respect.

• De-noise The performance of de-noising depends on excellent algorithm. In consideration of digital hearing aids all using DSP algorithm, and better DSP chip bring better result, we don’t compare them temporarily.

• Whistle As we know whistle comes from the feedback of leaked speaker. When the device is hanged from the neck, which means that we keep the distance between MIC and speaker, it helps decreasing whistle. So ear-jack is used in this design, every kind of earphone is suitable, that is a cheap and convenient method. At the same time, it saves time and money for custom-built earphone.

• Easy Too small to use is a objective problem for tiny hearing aid. For example, user fixes his CIC hearing aid with the help of his family while he can’t change the setting frequently in varying circumstance without anybody’s help. Take a look from this side, we’ll find the device in pocket or from neck is more convenient.

• Nursing Because the earphone is put in the ear canal users have to clean their ear and special earphone everyday. But we never clean our walkman’s earphone.

• Price Body hearing aid is the cheapest in these kinds, which only costs dozens of dollars. Other devices vary from hundreds to thousands of dollars. While the price of design based on FPGA is acceptable by common people because there are few hardware in the circuit. In addition, the cost of experiment and exploitation is even cheaper than anything else.

1) FPGA is a programmable device. Most of work is finished by software and HDL program, Error correction and debugging is easy in simulation environment and has no extra spending. So hardware costs little.

2) Nios II is an open soft core. Compare with other hard core such as ARM and PowerPC, you don’t need to pay for Nios II processor but get the same function.

VI. CONCLUSION

In this paper we bring forward a design method of digital hearing aid, in which FPGA works as core and Nios II plays the role of central processor. The hardware we used has fast processing speed and tiny bulk, and are easily to improve. The part of speaker is modified so that it is more flexible for users, they can carry and use it everywhere conveniently. New design has good portability and usability. Cooperating with appropriate DSP algorithm it’ll be a perfect hearing aid device.

REFERENCES

[1] X.B. Xiao, N.Y. Wang and G.S. Hu, “The progress of Algorithms Applied in Digital Hearing Aid,” Journal of Biomedicine Engineering, Vol.21, No.4, pp694-698, April, 2004.

[2] C. R. Xiong, J. F. Hu and Y. K. Hou, “Research and Design Based on DSP System of SOPC,” Microcomputer Information, Vol. 24, No. 6-2, pp. 206-208, June 2008.

[3] L. X. Guan and B. S. Shen, “Custom FFT Instructions for Nios Embedded Processor,” Microcomputer Information, Vol.22, No.11-2, pp. 10-12, November 2006.

[4] H.T. Zhou, “DSP Application----Programmable Digital Hearing Aid,” Journal of Fujian Teachers University (Natural Science), Vol. 18, No.4, pp.45-49, December 2002.

[5] J. V. Oldfield and R. C. Dorf, Field Programmable Gate Arrays-Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems, New York: Wwiley- Interscience Publication, 1995, pp 205-258.

[6] Altera Corporation, Nios II Software Developer’s Handbook, December 2004.

[7] Altera Corporation, Nios II Hardware Developer’s Handbook, December 2004.

The paper is supported by research item of Shanghai Normal University 2008. Number is SK200861

1898


design of portable hearing aid based on fpga

Documents