design of low power high speed digital vedic …
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DESIGN OF LOW POWER HIGH SPEED DIGITAL VEDIC MULTIPLIER
USING 13T HYBRID FULL ADDER
LEE SHING JIE
A thesis submitted in
fulfillment of the requirement for the award of the
Degree of Master of Electrical Engineering
Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia
JUNE 2018
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DEDICATION
Dedicated to my Saviour, Jesus Christ,
My beloved parents, all my family members and my fellow buddies.
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ACKNOWLEDGEMENT
Firstly, I would like to thank the LORD my God, Jesus Christ, for leading and
guiding me throughout my master journey. Without Him, this thesis would not come
to completion.
I would also like to dedicate my deepest gratitude to my supervisor, Associate
Professor, Siti Hawa Ruslan for all her valuable and much appreciated guidance and
advice that was generously given throughout this journey. Her guidance and
encouragement had motivated me to complete this master journey.
I am grateful to my beloved family members. Thank God for my
grandparents, parents and sister who unceasingly provides me with all my needs,
giving me their full support in terms of finance, care and love. Their encouragement
and motivation had driven me to complete this work with more confidence and
determination.
Besides, I would like to thank Mr. Sreedharan from Intelligent Circuit
Engineering Sdn Bhd who always helping me in solving problems regarding the
Synopsys software. Also I would like to extend my special appreciations to my
fellow buddy – Ann Debra Jaimin, for her companionship, prayer and moral support
throughout the years.
Last but not least, I would like to express my heartiest gratitude to all my
brothers and sisters in Christ. Thankful for all their support, encouragements and
prayers that helped sustained me in completing this project.
All glory to God. Thank you.
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ABSTRACT
The increment of demand for battery operated portable devices has laid emphasis on
the development of low power multiplier and high performance systems. Multiplier
is omnipresent in most common circuits; and adders act as the main block for the
multiplier to operate. Performance of full adder had direct impact in all arithmetic
circuits. In this thesis, a 4x4 bit Vedic multiplier has been successfully designed
using the combination of Urdhva Triyakbyam Sutras and 13 transistors (13T) hybrid
full adder (HFA). The Urdhva Triyakbyam algorithm satisfies the requirement of a
fast multiplication operation which reduced large number of partial products when
compared to others. Meanwhile the HFA is a new designed adder which is proposed
in this thesis is able to produce full output voltage swing output using low power
consumption (18.97 µW) and least delay (46.8 ps). The multiplier is designed and
simulated at the transistor level circuit and the layout circuit using Synopsys EDA
Tools with Process Design Kit (PDK) of 90 nm Complementary Metal Oxide
Semiconductor (CMOS) technology. With a 1 V voltage supply associated with load
capacitance of 0.1 pF, this 4x4 bit Vedic multiplier is able to produce an output with
the power consumption of 0.2015 mW, delay of 376 ps and a compact area which
only consumed 3100 µm2 (54.39 µm x 57.00 µm). The number of transistor for this
multiplier is only 356 transistors. Novelty SUM circuit that newly designed in this
project had a huge contribution in reducing the transistors count from 6T to 4T. With
the reduction of transistors count in this circuit, the overall power consumption, the
delay time and the layout had been reduced.
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ABSTRAK
Peningkatan permintaan terhadap peralatan yang beroperasi menggunakan bateri
telah membawa penekanan kepada pembangunan pendarab yang berkuasa rendah
dan sistem yang berprestasi tinggi. Pendarab boleh dijumpai dalam kebanyakan litar
yang ada sekarang dan penambah memainkan peranan sebagai blok utama bagi
pendarab untuk berfungsi. Prestasi penambah penuh memberi kesan secara langsung
terhadap semua litar aritmetik. Dalam tesis ini, pendarab Vedic 4x4 bit telah berjaya
direka menggunakan gabungan Urdhva Triyakbyam Sutras dan penambah penuh
hibrid (HFA) 13 transistor (13T). Algoritma Urdhva Triyakbyam memenuhi
keperluan operasi pendaraban yang cepat yang mengurangkan banyak hasil darab
separa berbanding dengan yang lain. Selain itu, HFA adalah reka bentuk baru
penambah penuh yang dicadangkan dalam tesis ini. Ia dapat menghasilkan hayunan
penuh voltan keluaran dengan penggunaan kuasa yang rendah (18.97 µW) dan
lengah masa yang paling singkat (46.8 ps). Pendarab ini direka dan disimulasi pada
litar transistor dan litar susun atur menggunakan Synopsys EDA Tools bersama
dengan kit proses rekabentuk teknologi semikonduktor pelengkap oksida logam
(CMOS) 90 nm. Dengan bekalan voltan 1 V dan kapasitor beban 0.1 pF, pendarab
Vedic bit 4x4 ini dapat menghasilkan keluaran dengan penggunaan kuasa 0.2015
mW, lengah masa 376 ps dan kawasan yang padat iaitu hanya 3100 μm2 (54.39 µm x
57.00 µm). Hanya sebanyak 356 transistor telah digunakan dalam pendarab ini. Litar
SUM yang baru diciptakan dalam projek ini mempunyai sumbangan yang besar di
dalam pengurangan bilangan transistor dari 6T ke 4T. Dengan pengurangan bilangan
transistor dalam litar ini, penggunaan kuasa keseluruhan, lengah masa dan kawasan
telah berjaya dikurangkan.
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CONTENTS
TITLE i
DECLARATION ii
DEDICATION iii
ACKNOWLEDGEMENT iv
ABSTRACT v
ABSTRAK vi
CONTENTS vii
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF SYMBOLS AND ABBREVIATIONS xiii
LIST OF APPENDICES xv
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Problem Statement 2
1.3 Objectives 3
1.4 Scope of Study 4
1.5 Thesis Outline 4
CHAPTER 2 LITERATURE REVIEW 6
2.1 Concept of Multiplier 6
2.2 Algorithm of Multiplier 7
2.3 Types of Multiplier 7
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2.4 Different Technique Used in Designing Multiplier 13
2.5 Comparison of Full Adder Used in Multiplier 15
2.5.1 Delay and Power Consumption in 1-bit Full Adder 15
Conclusions 17 2.6
CHAPTER 3 METHODOLOGY 18
3.1 Project Design Flow 18
3.2 Synopsys EDA Tools 20
3.3 Transistor Sizing 23
3.4 Urdhva Tiryakbyham Sutra 24
3.4.1 2-bit Binary Numbers Multiplication 24
3.4.2 4-bit Binary Numbers Multiplication 24
3.5 The Proposed Multiplier 26
3.5.1 Hybrid Full Adder 28
3.5.2 3T XOR Module 29
3.5.3 New SUM Module 30
3.5.4 Carry Generation Module 31
3.6 Conclusions 33
CHAPTER 4 RESULTS AND ANALYSIS 34
4.1 Basic Logic Gates Result 34
4.1.1 Inverter 34
4.1.2 NAND Gate 36
4.1.3 AND Gate 38
4.2 Hybrid Full Adder Result 41
4.2.1 Module I - XOR Gate 41
4.2.2 Module II – New SUM Circuit 44
4.2.3 Module III – Carry Generation Circuit 46
4.2.4 1-bit Hybrid Full Adder (HFA) 49
4.2.5 Delay and Power Consumption in 13T HFA 51
4.3 2x2 Bit Vedic Multiplier 52
4.3.1 Comparison of Different Types of Adders Used in
Vedic Multiplier 55
4.4 4-Bit Hybrid Carry Full Adder (4 bit HFA) 57
4.5 4x4 Bit Vedic Multiplier 59
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4.5.1 Comparison of 4x4 bit Vedic Multiplier using Different
Power Supply 64
4.6 8-Bit Hybrid Full Adder (8-bit HFA) 65
4.7 8-bits Binary Numbers Multiplication 67
4.8 8x8 Bit Vedic Multiplier 69
4.9 Conclusions 71
CHAPTER 5 CONCLUSION AND RECOMMENDATIONS 72
5.1 Achievement of First Objective 72
5.2 Achievement of Second Objective 73
5.3 Achievement of Third Objective 73
5.4 Recommendations for Future Research 74
5.5 Potential Contributions 74
5.6 Research Limitations 75
5.7 Conclusions 75
REFERENCES 77
APPENDICES 84
VITA 97
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LIST OF TABLES
2.1 Multiplication using Vedic Mathematics 12
2.2 Techniques in designing multipliers 14
2.3 Delay and power consumption in different full adders 16
3.1 Equations from P0 to P7 25
3.2 2x2 bit Vedic multiplier _1 27
3.3 2x2 bit Vedic multiplier _2 27
3.4 2x2 bit Vedic multiplier _3 27
3.5 2x2 bit Vedic multiplier _4 27
3.6 4-bit HFA _1 27
3.7 4-bit HFA _2 28
3.8 4-bit HFA _3 28
4.1 Truth table of inverter 35
4.2 Truth table of NAND 37
4.3 Truth table of AND 39
4.4 Truth table of XOR 42
4.5 Truth table of New SUM circuit 45
4.6 Truth table of Carry Generation circuit 47
4.7 Truth table for full adder 50
4.8 Delay and power consumption in 13T HFA 52
4.9 Truth table for 2x2 bit Vedic multiplier 54
4.10 Comparisons of different adders used in 2x2 bit Vedic multiplier 56
4.11 Comparison of different voltage supply for 4x4 Bit Vedic
Multiplier 65
4.12 Equations from P0 to P15 69
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LIST OF FIGURES
2.1 Algorithm of 4x4 bit unsigned multiplication 7
2.2 Structure of Wallace Tree [21] 8
2.3 Architecture of Booth multiplier [24] 9
2.4 Architecture of Radix 4 multiplier [24] 10
3.1 IC design flow of 4×4 bit Vedic multiplier 19
3.2 Overall project flow 22
3.3 Transistor sizing 23
3.4 Pictorial representation of 4x4 bit Vedic multiplier 25
3.5 Block diagram of the proposed multiplier 26
3.6 Block diagram for hybrid full adder 29
3.7 Module I 3T XOR circuit 29
3.8 Module II New Sum circuit 30
3.9 Module III COUT circuit 32
4.1 Inverter schematic diagram 35
4.2 Inverter instance symbol 35
4.3 Inverter timing diagram 36
4.4 Inverter layout 36
4.5 NAND schematic diagram 37
4.6 NAND instance symbol 37
4.7 NAND timing diagram 38
4.8 NAND gate layout 38
4.9 AND schematic diagram 39
4.10 AND instance symbol 39
4.11 AND timing diagram 40
4.12 AND gate layout 40
4.13 XOR schematic diagram 41
4.14 XOR instance symbol 42
4.15 XOR timing diagram 42
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4.16 XOR gate layout 43
4.17 New SUM schematic diagram 44
4.18 New SUM circuit instance symbol 45
4.19 New SUM circuit timing diagram 45
4.20 New SUM circuit layout 46
4.21 Carry Generation schematic diagram 47
4.22 Carry Generation circuit instance symbol 47
4.23 Carry Generation circuit timing diagram 48
4.24 Carry Generation circuit layout 48
4.25 Hybrid Full Adder schematic diagram 49
4.26 Full adder instance symbol 49
4.27 Full adder timing diagram 50
4.28 Hybrid Full Adder layout 51
4.29 2x2 bit Vedic multiplier schematic diagram 53
4.30 2x2 bit Vedic multiplier instance symbol 53
4.31 2x2 bit Vedic multiplier timing diagram 54
4.32 2x2 bit Vedic multiplier layout 55
4.33 4-bit hybrid full adder schematic diagram 57
4.34 4-bit hybrid full adder instance symbol 58
4.35 4-bit hybrid full adder timing diagram 58
4.36 4-bit hybrid full adder layout 59
4.37 4x4 bit Vedic multiplier schematic diagram 60
4.38 4x4 bit Vedic multiplier instance symbol 60
4.39 4x4 bit Vedic multiplier timing diagram example 1 62
4.40 4x4 bit Vedic multiplier timing diagram example 2 62
4.41 4x4 bit Vedic multiplier layout 63
4.42 4x4 bit Vedic multiplier post layout timing diagram 64
4.43 8-bit hybrid full adder schematic diagram 66
4.44 8-bit hybrid full adder instance symbol 66
4.45 8-bit hybrid full adder timing diagram 67
4.46 Pictorial representation of 8x8 bit Vedic multiplier 68
4.47 8x8 bit Vedic multiplier schematic diagram 70
4.48 8x8 bit Vedic multiplier instance symbol 70
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LIST OF SYMBOLS AND ABBREVIATIONS
ALU - Arithmetic Logic Unit
ASIC - Application Specific Integrated Circuit
CMOS - Complementary Metal Oxide Semiconductor
CSA - Carry Select Adder
DRC - Design Rule Check
DSP - Digital Signal Processor
ECRL - Efficient Charge Recovery Logic
EDA - Electronic Design Automation
ERC - Electrical Rule Check
FFT - Fast Fourier Transform
GDI - Graphics Device Interface
HFA - Hybrid Full Adder
IC - Integrated Circuit
iPDKs - Interoperable Process Design Kits
ISE - Integrated Synthesis Environment
L - Transistor Channel Length
LPE - Layout Parasitic Extraction
LSB - Least Significant Bit
LVS - Layout Versus Schematic
m - Meter
MSB - Most Significant Bit
MUX - Multiplexer
n - Nano = 10-9
p - Pico = 10-12
PDK - Process Design Kit
PFAL - Positive Feedback Adiabatic Logic
PP - Partial Product
PTL - Pass Transistor Logic
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RC - Resistors and Capacitors
s - Seconds
Soc - System on Chip
T - Transistors
V - Volt
VLSI - Very Large Scale Integration
VUE - Virtual Understanding Environment
W - Watt
W - Transistor Channel Width
µ - Micron = 10-6
% - Percent
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LIST OF APPENDICES
APPENDIX TITLE PAGE
A Custom Design Entry 85
B Algorithm flow for 4x4 bit Vedic Multiplier
using binary number 87
C Layout Versus Schematic (LVS) Results 91
D Layout Parasitic Extraction (LPE) for 4x4 bit
Vedic multiplier 95
E List of Publications 96
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CHAPTER 1
INTRODUCTION
This chapter stated the background of multiplier in different algorithm. The problem
statement, objectives and scope of study for this design are presented in this chapter
too.
1.1 Background
In recent years, the growth of personal computing devices such as portable
computers and real time multimedia applications, coupled with wireless
communication systems had made power dissipation the most critical design
parameter for digital system. The need for low power design is also becoming a
major issue in high performance digital systems such as microprocessor, digital
signal processor and other applications. For these applications, multiplier is the major
core block [1]. It functions as a fundamental operation in most signal processing
operation.
A multiplier is an indispensable element in the processors and contributes
substantially to the total power consumption of the system. Using complementary
metal oxide semiconductor (CMOS) logic circuits in various digital signal processors,
an efficient high speed, low power and small size integrated circuit (IC) can be
designed [2]. Furthermore, the rapid growth of very large scale integration (VLSI)
chips has led to rapid and innovative development in low power design.
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There are many multiplication algorithms which can be used to design the
multiplier, for instance, carry-select adder (CSA) and Wallace Tree method [3]. Each
of these algorithms has its own advantages in terms of speed, power consumption,
layout regularity and area. Although there are many multiplication algorithms, Vedic
algorithm [4] claims to be the most interesting algorithms. It works based on the
natural principles on which the human mind works.
Vedic mathematics propose simple approaches compared to the normal
mathematical operations. The word “Vedic” derived from the word “Veda” which
means the store house of the knowledge. Vedic mathematics is an ancient
methodology of the Indian mathematics. It has the unique technique of calculation
based on the 16 sutras (formulae) [5]. It covers several modern mathematical terms
including arithmetic, geometry, trigonometry, quadratic equations, factorization and
even calculus. The implementation of the Vedic algorithm in the multiplier is based
on the Urdhva Triyakbhyam Sutra [4–6] which is a general multiplication formula
applicable to all cases of multiplication. This algorithm satisfied the requirement of a
fast multiplication operation because of the vertical and crosswise architecture from
the Urdhva Triyakbyam Sutra [7]. The algorithm reduced the number of partial
products compared to the conventional multiplication algorithm. By using the Vedic
mathematics, less number of steps are required for multiplication, thus the multiplier
will be more power efficient, faster and small in size. It is one of the feasible
techniques implemented in VLSI design to overcome the power dissipation issue as
the number of transistors increased according to Moore’s law.
1.2 Problem Statement
Moore's Law states that the number of transistors in the integrated circuit will
increase exponentially by a factor of 2 for every 18 to 24 months [8]. Nowadays, as
the scale of integration keeps growing, designers had come out with compact chips
with higher number of transistors. The prolific growth in semiconductor device
industry had led to the development of high performances portable systems with
enhanced reliability in data transmission [9], [10] and VLSI chips have led to rapid
and innovative development in low power design in recent years.
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The demands for the high fidelity portable devices have laid emphasis on the
development of low power and high performance systems. In the next generation
processors, the low power design has to be incorporated into fundamental
computation units, such as multipliers. CMOS is the dominant technology which is
used to construct these types of integrated circuits. The three most widely accepted
parameters to measure the quality of a circuit or to compare various circuit styles are
area, delay and power [2].
Multiplier is the most common circuit in digital devices, and multiplication is
known as the fundamental operation in most signal processing algorithms [11], [12].
A processor spent a significant amount of time to perform multiplication for digital
signal processing (DSP) applications such as Fast Fourier Transform (FFT) and
convolution. Therefore, low performance multiplier increases the propagation delay
or lowers the speed of an electronic device. Moreover, multiplier dissipates higher
amount of heat due to heavy workloads that execute the multiplication operation
[13]. A poor multiplier is not only affects the speed of a device, power consumption
and power dissipation, it also affects the usage duration and the lifespan of the
device. Therefore, there is a need to implement a suitable multiplication algorithm to
optimize the multiplication process and a suitable technology to reduce the amount
of power consumed by the multiplier. Thus, this project is embarked to design a low
power high speed multiplier which is an important part in VLSI system.
1.3 Objectives
The objectives for this project are:
1. To design a 4x4 bit multiplier using new adder and Vedic algorithm.
2. To design a low power, high speed and small area multiplier.
3. To verify the functionality of the 4x4 bit multiplier.
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1.4 Scope of Study
The scopes for this project that related to the objectives are:
1. Design a 4x4 bit multiplier using a novel hybrid full adder design based on
Urdhva Tiryakbyham Sutra algorithm.
2. Reduce the number of transistor for the multiplier to the range of 1424
transistors which ultimately will reduce the power dissipation and area of the
multiplier. Vertical and crosswise technique in Vedic mathematics is used to
reduce the rise and fall delay time of the design.
3. The CMOS technology used to verify the functionality of the 4x4 bit
multiplier is 90 nm Process Design Kit (PDK) with 1V power supply. The
software used is Synopsys EDA tools.
1.5 Thesis Outline
This thesis basically includes 5 chapters. Each chapter will cover all the information,
result, analysis and discussion about this project. Brief descriptions for all the
chapters are given as follow:
1. Chapter 1
This chapter describes about the introduction, objective and scope of
this project.
2. Chapter 2
This chapter contains the literature of study that involved in this
project. It also describes the theory of logic gate design in the multiplier and
the technique used for the multiplier.
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3. Chapter 3
This chapter shows the method and approach being used and the
software used which is Synopsys EDA tool. It shows the step to design the
4x4 bit multiplier circuit starting with transistor level to layout level.
4. Chapter 4
The concept of multiplier design is described in this chapter. It shows
the basic logic gates used and the operation of the 4x4 bit multiplier. The
result obtained is shown in this chapter. This chapter starts with compilation
of the results, followed by design synthesis, place and routing, and full layout
of the multiplier circuit. Analysis on the result is discussed in this chapter.
5. Chapter 5
This chapter states the conclusion and recommendation for future
improvement of the project.
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CHAPTER 2
LITERATURE REVIEW
This chapter describes the multiplier concept that function as the major block in
digital signal processor. The concept of basic multipliers, Vedic mathematics
multiplier and full adder will also be explained. Related and previous works that had
been carried out by other researchers were analysed and presented in this chapter.
Concept of Multiplier 2.1
Typical DSP applications such as digital filtering, digital communications and
spectral analysis play an important role in signal processing [6]. In most of the DSP,
multiplier is one of the key hardware blocks. Since multipliers are rather complex
circuits, with advances in technology, many researchers have tried and are still trying
to design multipliers which offer either the following design targets – high speed,
low power consumption, regularity of layout and hence less area or even a
combination of them in one multiplier thus making them suitable for various high
speed, low power and compact VLSI implementation.
A multiplier is a circuit which the output state is produced by arithmetic
product of two input signals. The most common multiplication method is “add and
shift” algorithm. In parallel multipliers, the number of partial products to be added is
the main parameter that determines the performance of the multiplier [14]. It consists
of a multiplicand (M), multiplier (Q) and product (P). The result is the product of the
multiplier and multiplicand (P = M * Q).
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Algorithm of Multiplier 2.2
Figure 2.1 shows an example of the basic hardware of 4x4 bit unsigned
multiplication by using multiple adders and logic gates. The multiplication of A0 and
B0 which produces a partial product (PP) B0A0 can be obtained by using an AND
gate. All other PPs are also obtained using AND gates. For example, see PP11, PP12,
PP13 and PP14 in Figure 2.1. The final result is obtained by summing up the columns
of partial products and propagating the carries from the right to the left [15]. This
type of multiplication takes time and has a long delay. In term of hardware
implementation using CMOS technology, it will involve a lot of transistors, and will
consume more power.
(MSB) (LSB)
A3 A2 A1 A0
× B3 B2 B1 B0
C B0A3 B0A2 B0A1 B0A0
+ B1A3 B1A2 B1A1 B1A0
C PP14 PP13 PP12 PP11 PP10
+ B2A3 B2A2 B2A1 B2A0
C PP25 PP24 PP23 PP22 PP21 PP20
+ B3A3 B3A2 B3A1 B3A0
P7 P6 P5 P4 P3 P2 P1 P0
Figure 2.1 Algorithm of 4x4 bit unsigned multiplication
Types of Multiplier 2.3
Multipliers can be classified into three different architectures: serial, parallel and
serial-parallel multipliers. In serial multiplier, both operands entered into the
multiplier in a serial form thus the delay time is longer. The strengths of this
architecture are minimum amount of area and hardware is required [16]. The second
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multiplier is parallel multiplier which is able to carry out high speed mathematical
operations. But the drawback is the relatively larger chip area consumption [17].
Third is serial-parallel multiplier which compromise speed to achieve better
performance for area and power consumption [18]. Beside architecture, the
techniques used in multiplier also play an important role over speed, power
consumption, layout regularity and area. A few examples are described at the next
section.
2.3.1 Wallace Tree
Chris Wallace introduced a different way of parallel addition of the partial product
bits using a tree of carry save adders, which is known as “Wallace Tree” [19]. There
are three steps involved in these techniques. Firstly, AND array is used to compute
the partial product. Then, a carry save adder is used to reduce the partial product into
two row of matrix. Lastly, a ripple carry adder is used to add up the remaining two
rows [2, 20]. The structure of Wallace tree is shown in Figure 2.2.
Figure 2.2 Structure of Wallace Tree [21]
Wallace Tree technique is considerably fast [2] due to the non-linearity of its
structure. However the wiring of Wallace tree is less regular and more complicated,
thus it has a complex circuit [3] which leads to a larger silicon area.
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2.3.2 Booth Algorithm
Booth multiplier is known as the standard technique used in many chip designs [22].
These algorithm multiples two numbers in 2’s complement form. The numerically
larger number is designated to be the multiplier and the other to be the multiplicand
[23]. Firstly, initial guess is created for the product, which is zeros followed by the
multiplier on the right half of the product. Then, two right most bits of the product in
Booth algorithm is used to determine whether add and shift or merely shift in the
following step. Meanwhile, the partial products are obtained if shifted right or left,
depending on the starting bit and then addition process is done. This step is
performed by partial product generators together with several adders that operate in a
parallel form. The remaining of the sum is the final result of the multiplication [24].
The architecture of booth multiplier is shown in Figure 2.3.
Figure 2.3 Architecture of Booth multiplier [24]
In Booth multiplier, two bits of the multiplier are considered at the same time
by using the encoding algorithm, thus number of partial products can be reduced
[17]. However, this conventional array multiplier required large silicon area. Larger
silicon area is required to remove the heat generated due to large complex logic
power consumption [24], thus it had a high delay time.
Multiplier Multiplicand
Partial Product
Generator
Adder
Accumulator
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2.3.3 Radix 4
The architecture of Radix 4 multiplier is shown in Figure 2.4. It consists of 2
multiplexers (MUX), carry select adder (CSA) and adder. In this 4 bit Radix 4
multiplier, the multiplication process starts by appending a zero to the right of x0
(LSB). Then the first two bits of the MUX will determine the successive partial
product. Two partial products are generated in using Radix 4 multiplier which is old
cumulative partial product and new cumulative partial product [25]. The cycle flow
is fastened by using CSA that could reduce the number of addition [24]. Next, the
adder circuit groups multiplicand by three bits and encoding them into one [26]. The
advantages of using this method are high speed, lower area, low propagation delay
[25], but the main drawbacks are high cost and low utilization [10].
Figure 2.4 Architecture of Radix 4 multiplier [24]
2.3.4 Adiabatic Logic Circuit
The word “Adiabatic” refers to a change of state without heat loss or gain and thus
no heat is dissipated. During adiabatic switching, all the nodes conserve charge at a
constant current to reduce power dissipation [28].
Old Cumulative
Partial Product
New Cumulative Partial Product
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REFERENCES
[1] D. Krishnaveni and T. G Umarani, “VLSI Implementation of Vedic Multiplier
With Reduced Delay,” International Journal of Advanced Technology &
Engineering Research (IJATER), vol. 2, no. 4, pp. 10–14, 2012.
[2] K. Linet, P. Umarani, and T. Ravi, “Design of Multipliers Using Low Power
High Speed Logic in CMOS Technologies,” International Journal of
Advanced Research in Electrical, Electronics and Instrumentation
Engineering, vol. 3, no. 5, pp. 9417–9424, 2014.
[3] J. Sharma and S. Kumar, “Digital Multipliers : A Review,” International
Journal of Science and Research (IJSR), vol. 3, no. 6, pp. 741–743, 2014.
[4] R. Tr and R. Saligram, “Design of High Speed Low Power Multiplier using
Reversible logic : A Vedic Mathematical Approach,” 2013 International
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