design of low power digital hearing aid chip
TRANSCRIPT
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MS Thesis
Design of Low Power Digital Hearing Aid Chip
Jin Kyung KimDecember 23, 2003
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Outline
• Introduction• Design of Digital Hearing Aid
– Specifications– Building Blocks
• Simulation Results• Conclusion and Further Work
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Outline
• Introduction• Design of Digital Hearing Aid
– Specifications– Building Blocks
• Simulation Results• Conclusion and Further Work
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Motivation• Hearing Problem is Serious!
– 10 % of population have difficulties in hearing.
0
100
200
300
400
500
600
700
800
900
1995 2005 2015 2025
# of people[Million]
Years
440
560
700
900
Increase of Hearing Problem
11%
45%14%
30%
Hearing Loss Ratio
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Design Considerations
Small Size
(One-chip)
Low Power
(<500uW)
Programmability
LowPowerDigital
HearingAid!
LowPowerDigital
HearingAid!
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Previous Work
JSSC 1989[Centre Swisse]
JSSC 1997[Philips]
JSSC 2002[TI]
Power Consumption 2.1mW 2.1mW400uW
@ no signalBandwidth 8kHz 8kHz 10kHz
Number of Channels - 4 2Total Harmonic Distortion - -45dB -40dB
Process 3um CMOS 0.8um CMOS 0.6um CMOSArea 35mm2 35mm2 12mm2
Misc.
4-chips,10 external
passive elements,EEPROM
IR remote control receiver,
TelecoilEEPROM
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Outline
• Introduction• Design of Digital Hearing Aid
– Specifications– Building Blocks
• Simulation Results• Conclusion and Further Work
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Specifications• Power < 500uW
– Battery lasts for 1 week at least. (16hr/day use)
• Supply Voltage = 1V
Lifetime
EMF1.1V
1.4V1.3V
[Zinc-Air Battery]
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Specifications (Cont’d)
• Programmable 2 Channel DSP– Compensation for ‘ski-slope’ loss
• Acceptable Sound Quality– 12-bit Resolution
4-bit 12-bit16-bit
f
Gain
f
Gain
@ 16kHz Sampling Frequency
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Specifications (Cont’d)
• Bandwidth – 8kHz
• Total Processing Time < 5ms– To avoid confusion with lip-reading
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Overall Architectures
Microphone
Receiver
Preamp. ADC
DSP
ROMDAC
1.024MHz
32kHz
2.048MHzRing Oscillator
Preamplifier ReceiverDriver
[Digital Hearing Aid System]
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Preamplifier• Microphone Specification
– Differential Output Gain 4.43V/V up to 100dB input– For A/D Converter Differential Input 140mV
Microphone
Receiver
Preamp. ADC
DSP
ROMDAC
Preamplifier ReceiverDriver
Input [dB SPL] Output [mV] Example
30~40 0.01 ~ 0.03 Ambient room noise/ Whisper
50~70 0.1 ~ 1 Conversation
80~90 3.16 ~ 10 Feature film in theater
90~11010 ~ 31.6
(@ 100dB)Bar with music
110 ~ 120 100 ~ Rock concert
130 ~ 140 Painful sound
※ Spec. for Knowles Inc. EM series Microphone
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Preamplifier (Cont’d)
• Opamp. with MOS Resistive Circuit (MRC)– Small Area– Ease of Tunability
for Future AGC
MRC1
MRC2
vo
VG1 VG2
V'G1 V'G2
vi
1
2
3
4
VG1 VG2
T1
T2
T3
T4
I1
I2
)V(VLWK
RG2G1P
MRC−
=1
RMRC
RMRC
V1 V3
V2 V4
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Preamplifier
Frequency Spectrum for 1kHz 1mV Input
• THD = -70dB @ 1kHz, 1mV input • THD = -52dB @ 10mV input• PowerMAX = 35uW
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Analog-to-Digital Converter• Oversampling A/D Converter
– 12-bit Resolution A/D Converter • SNR > 72dB
– 1-bit 2nd Order Modulator with 64 Oversampling Ratio (fs/2f0)
Microphone
Receiver
Preamp. ADC
DSP
ROMDAC
Preamplifier ReceiverDriver
1/Z
1-bit DAC
1-bit ADC1/Z OSR
Delta-Sigma ModulatorDelta-Sigma Modulator Decimator
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ADC Modulator
• SNR: 72dB (@ 1kHz)• Power: 89uW (Modulator: 82uW, Decimator: 7uW)
Frequency Spectrum for 1kHz 26mV Input
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Digital Signal Processor• Specifications
– 2 Channel• Compensation for Ski-slope Loss
– 6 Programmable Parameters• P, G0, K, G1, G2, VC
– Serial Interface & Parameter ROM
Output
Freq.
Output
Input@High Freq.P
G0
K
G1
G2
Microphone
Receiver
Preamp. ADC
DSP
ROMDAC
Preamplifier ReceiverDriver
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Parameter ROM
ROM Core
P K G0 G1 G2 VC
10 0000000100000000 1101 0110 0001 1000
Wor
d Li
ne D
ecod
er
Column Buffer
BL1
RippleCounterROM_SEL
2 416 4 44
P[1:0] K[15:0] G0[3:0] VC[3:0]G1[3:0] G2[3:0]
ROMCell
WL1
WL2
WL2
WL1
WL1
WL1
BL1
BL0
ColumnBuffer
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DSP Frequency ResponseP G0
G1, G2 VC
G0 = 1/ 64, G1 = 32
1
23
P = 3, G1 = 32
2
1/2G0 = 1/ 64
P3 = 3, G0 = 1/ 64
64
32
16
P = 3, G0 = 1/ 64G1 = 32, G2 = 8
4
2
VC = 1
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Digital-to-Analog Converter• Oversampling D/A Converter
– 12-bit Resolution D/A Converter• SNR > 72dB
– 1-bit 2nd Order Modulator with 128 OSR
Microphone
Receiver
Preamp. ADC
DSP
ROMDAC
Preamplifier ReceiverDriver
u(n)OSR
Interpolation Filter
1/Z
Decoder
1-bit DAC1/Z
Delta-Sigma ModulatorDelta-Sigma Modulator
y(t)
Analog LPF
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Filter Coefficient OptimizationFilter Coeff.
“31”
2’s C
omp. CSD
0 1 1 1 1 1 1 0 0 0 0 1# of P.P. = 5# of INV = 0
# of P.P. = 2# of INV = 1
Filter Coeff.“3”
2’s C
omp. CSD
0 1 1 1 0 1# of P.P. = 2# of INV = 0
# of P.P. = 2# of INV = 1
WINNERWINNER
CSD Not Always Superior to 2’s Comp.
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Decision AlgorithmFilter Coeff. Representation
1. Less P.P. (Adder)2. Less Inverter
Comparison
SharingSame Coeff.
2’s Comp. CSDfs Z-1
+
+
+
2fs
fs Z-1
+
+
+
2fs
Sharing Coeff.
19% Power Reduction Compared to CSD(28% to 2’s Comp.)
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DAC
• SNR: 80dB @1kHz • Power: 65uW
Frequency Spectrum for 1kHz 26mV Input
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Receiver DriverMicrophone
Receiver
Preamp. ADC
DSP
ROMDAC
Preamplifier ReceiverDriver• H-Bridge– High Efficiency– Low Power Dissipation
INP INNt
V
t
V
Knowles Inc. BPHF series Receiver
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Outline
• Introduction• Design of Digital Hearing Aid
– Specifications– Building Blocks
• Simulation Results• Conclusion and Further Work
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Total Simulation Results
• SNR: 70dB @ 1kHz • THD: -45dB
Frequency Spectrum for 1kHz 23mV Input
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Total Simulation Results (Cont’d)
100 1000
Frequency (Hz)
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
500 4K 8K
Out
put A
mpl
itutd
e (d
B)
-14
-11
-2
-17
Vin=1mV (P=3, G0=1/2, G1=32, G2=8, VC=1, K=1)
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Total Processing Time
Input(4kHz)
Output860usec (< 5msec)
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Power Consumption
Preamp12.73%
ADC32.36%
DSP 4.00%
DAC23.64%
H - Bridge14.55%
Ring Osc.12.73%
Total Power275uW
Power Dissipation
Blocks Power (uW)
Preamplifier 35
ADC 89
DSP 11
DAC 65
H-Bridge 40
Ring Oscillator 35
Total 275uW
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Power Comparison
0
500
1000
1500
2000
2500
Philips TI This Work
275
Power (uW)
Centre Swiss
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Summary of Performance
Vdd 1V
Power Consumption 275uW
Number of Channels 2
Maximum Input Signal ~30mV
SNR D/A (@1kHz) 80dB
Temperature Range 0-100℃
Bandwidth 8kHz
SNR A/D (@1kHz) 72dB
SNR Audio Path (@1kHz) 70dB
THD Audio Path(@ 1kHz, 23mV input)
-45dB
Low Threshold 0.18um CMOS Process
Preamp. ADC
DAC
Preamplifier
ReceiverDriver
DSP
ROM
Receiver
Microphone
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Outline
• Target• Building Blocks• Simulation Results• Conclusion and Further Work
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Conclusion• A 1V 275uW Digital Hearing Aid Chip is Designed.
– Preamplifier with MRC• THD = -70dB @ 1kHz, 1mV input
– 1-bit 2nd Order ADC • OSR=64, SNR=72dB
– Programmable 2 channel DSP• 6 Programmable Parameters• Serial Interface & Parameter ROM
– 1-bit 2nd Order DAC • OSR=128, SNR=80dB• Coefficient Optimization of Interpolation Filter
– H-Bridge
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Further Work• Implementation• Quality Improvement• H-Earphone (Healthy Earphone)
– Hearing aid with additional function• Noise cancellation, etc…
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Supplementary
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Delta-Sigma Modulator
INN
INP
CLK CLK
CLK CLK
CLKB CLKB
CLKBCLKB
CLK
CLK
CLK
CLK
CLKB
CLKB
CLKB
CLKB
CLKB
CLKB
CLKB
CLKB
CLK
CLK
CLK
CLK
CLKD
CLKD
CLKB
D
D
Q
Q
OUTN
OUTP
700pF
700pF
700pF
700pF
3pF
3pF
1pF
1pF
100fF
100fF
100fF
100fF
1st integrator
2st integrator
Comparator (1-bit ADC)
D-F/F
1-bit DAC
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Decimation Filter
∏=
−+=4
0
32 )1()(i
i
zzH
2-1z -1z -1z -2z -2z -2z
2
2
-4z z z -8z z z
2-4 -4 -8 -8
2
z z z-16-16-16
1.024MHz1-bit
16-bit32kHz
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Block Diagram
FIRBandSplitFilter
High-BandChannel
Low-BandChannel
Serial Interface CoefficientROM
VolumeControl
LEDATA
CK
DSP_OUT[15:0]
DSP_IN[15:0]
ROM_SEL
CK(32kHz)
Digital Signal Processor
16 16
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Two-Band DSP Algorithm
DSPInput
DSPOutput
P
K
Hp
Lp
BandSplitFilter
1
0
G0
G2
G1
VC
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Serial Interface
4-BitShift Register
LE
DATA
CK
2
P[0:1] K[0:15] G0[0:3] VC[0:3]
4-BitShift Register
4-BitShift Register
16-BitShift Register
4-BitShift Register
2-BitShift
Register
4-BitRegister
4-BitRegister
4-BitRegister
16-BitRegister
4-BitRegister
2-BitRegister
16 4 4 4 4
G1[0:3] G2[0:3]
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DSP Performance SummaryI/O Type 2’s Complement 16-bit
High-Band Knee Point (K) 16-bit
Volume Control (VC) 4-bit
DSP 10 µWSerial Interface 1 µW
Clock Frequency 32 kHzChannel 2
Filter Type FIR FilterProgrammable Coefficients
Band Split (P) 2-bit
Low-Band Gain (G0) 4-bitHigh-Band Low-Level Gain (G1) 4-bit
High-Band Compression Ratio (G2) 4-bit
Power Dissipation
Active Area 0.3 x 0.3 mm2
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Multiplication with Adders & Shifters
• 2’s Complement vs. Canonical Signed Digit (CSD)
Integer 2’s Complement CSD3 011 110
0
x15 x14 x1 x0
X 22
a1 a0a15 a14b1 b0b16 b15
+a0b0
c0
s0
+a1b1
s1
c1c2+a15b15
c15
s15
c16+b16
s16
c17+b17
s17
b17
x15 x14 x1 x0
X -2
(b)
x15 x14 x1 x0
X 20
x15 x14 x1 x0
X 21
a1 a0a15 a14b1 b0b16 b15
+a0b0
c0
s0
+a1b1
s1
c1c2+a14b14
c14
s14
a15
c15+b15
s15
c2+b16
s16s17
(a)
Implementation of ‘X * 3’ using (a) 2’s Complement (b) CSD
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Ring Oscillator• CLK
– 2.048MHz, 1.024MHz, 512kHz, 256kHz, 128kHz, 64kHz, 32kHz
Delay DelayBias
Ring Oscillar
Divider
DividerDividerDividerDivider
2.04
8MH
z
1.02
4MH
z
64K
Hz
32K
Hz