design of cmos flip flop using floating gates

Design of cmos flip flop using floating gates

1. INTRODUCTION

An ever increasing problem associated with modern CMOS processes is the demand for digital

CMOS gates operating at low supply voltages. When the supply voltage is decreased the speed of the

logic circuits will be reduced due to reduced effective input voltage to the transistors. When the

threshold voltage is reduced the off current running through transistors which are switched off will

increase and thereby increase static power consumption and reduce noise margins. Voltage scaling

reduces the active energy and unfortunately speed as well. Low voltage applications are often dominated

by low speed and low energy requirements, typical battery-powered electronics. The optimal supply

voltage for CMOS logic in terms of EDP is close to the threshold voltage of the nMOS transistor Vtn

for the actual process, assuming that the threshold voltage of the pMOS transistor Vtp is approximately

equal to −Vtn . Several approaches to high speed and low voltage digital CMOS circuits have been

presented .

Floating-gate (FG) CMOS gates have been proposed for ultra low-voltage (ULV) and low power (LP)

logic . However, in modern CMOS technologies there are significant gate leakages which undermine

non-volatile FG circuits. FG gates implemented in a modern CMOS process require frequent

initialization to avoid significant leakage. By applying floating capacitances to the transistor gate

terminals the semi-floating-gate (SFG) nodes can have a different DC level than provided by the supply

voltage headroom

There are several approaches to FG CMOS logic .The ULV logic gate can be operated at a clock

frequency more than 10 times than the maximum clock frequency of a similar

complementary CMOS gate operating at the same supply voltage. Alternatively, the ULV logic may

operate at a lower supply voltage than complementary CMOS assuming similar clock frequency, i.e.

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the reduced supply voltage and the reduced output swing may be utilized in a low power application. For

high clock frequencies, the switching energy consumed by the ULV gate will be reduced compared to a

complementary gate.

The ULV logic offers a significant reduction in energy delay product (EDP) for ultra low supply

voltages compared to standard CMOS logic . In addition, all gate terminals of the active transistors in the

evaluation phase are determined by the input transitions. cmos gates have been proposed for ultra low

voltage and low power logic .the floating gate structure is similar to a traditional mos device , except that

an extra ploysilicon strip is inserted between the gate and channel.this strip is not connected to anything

and is called “floating gate.” The ULV gates applied offer increased speed compared to other CMOS

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logic styles for low supply voltages. ULV logic gates can be operatedat a clock frequency more than 10

times than the maximum clock frequency of a similar complementary CMOS gate operating at the same

supply voltage. Floating-gate (FG) CMOS gates have been proposed for ultra low-voltage (ULV) and

low power (LP) logic]. However, in modern CMOS technologies there are significant gate leakages

which undermine non-volatile FG circuits. FG gates implemented in a modern CMOS process require

frequent initialization to avoid significant leakage. By applying floating capacitances to the transistor

gate terminals the semi-floating-gate (SFG) nodes can have a different DC level than provided by the

supply voltage

In this paper we present a high speed ultra low-voltage and flipflop based on ULV CMOS logic.

Simulated data for latch in a 65nm CMOS process is provided. In section II the ULV flip-flop is

presented and simulated results for different supply voltages are

presented in next section .

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2.BASIC STRUCTURE OF CMOS FLOATING GATE

Recently, there has been a tremendous amount of interest in using multiple-input floating-

gate MOS (FGMOS) transistors to build circuits that process information by linearly summing a number

of input voltages on the floating-gate via a capacitive voltage divider .Nearly all such FGMOS circuits

have been developed in CMOS processes with two levels of polysilicon. Unfortunately, the second poly

layer results in significantly higher fabrication costs; consequently, this option is now found in only a

small percentage of current commercial processes. Our motivation for this work is to demonstrate that

we can build high-performance, floating-gate memories and circuits in digital CMOS processes that

have only one layer of polysilicon. The primary issue is whether or not we can obtain adequate control-

gate linearity with MOS capacitors. Current research in a similar vein for switched-capacitor circuits

gives us reasonable hope of similar results for FGMOS circuits

Fig 2

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3. HIGH SPEED ULTRA LOWVOLTAGE FF

The original ULV logic style , shown in Fig. 1, resembles CMOS precharge logic and is characterized

by two modes of operation:

• Recharge. The nMOS floating-gate is recharged to VDD and the pMOS floating-gate is recharged to

VSS = gnd while the output and input are precharged to VDD/2 = (VDD − VSS)/2. The output will be

forced to VDD/2 due to a reversed biased inverter. The static current running through the ULV logic

when the output is close to the precharge level is insignificant due to the low gate source voltage of the

evaluating transistors, i.e. Vgs ≈ VDD/2.

• Evaluate. The output will be pulled to VDD if a negative transition, ΔVin = −VDD/2 , occurs and to

VSS if there is a positive transition, ΔVin = VDD/2, applied at the input.

The ULV gates used in the ULV FF are different than the original ULV logic in terms of precharged

output value during there charge phase and the inputs and outputs are binary signals which can be used

in any digital low voltage CMOSdesign.

The high speed ULV FF (ULVFF) is shown in Fig. 3 and consists of three different parts;

1.level to edge converter (LEC)

2. high speed edge processing inverter

3. an output stage.

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Fig 3 The high speed ultra low voltage flip-flop

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3.1 Level To Edge Converter

The level to edge converter (LEC) converts a dc value at the input D (and D) to an edge where the

orientation of the edge is dependent on the value of D. The two LEC circuits, located on each side of the

ULV FF, produce edges either at a1 and b1 or a2 and b2. The transistors connected to the input must be

strong to determine the precharge level of the LEC circuits. In addition the edges occurring at one of the

a outputs will be inverse of the

edge occurring at one of the b outputs. This is due to the inverted input signals D and D. When φ = 1 the

gate terminals of the LEC circuits are recharged, i.e. the gate terminal of the nMOS transistors driving

the LEC outputs will be recharged to VDD and the gate of the pMOS transistors will be recharged to 0V.

When the negative clock edge occurs one and only one of the outputs of each LEC converter will switch

as shown in TABLE I. The outputs will be differential, i.e. inverted, when φ = 0. By adding the two

inputs through floating capacitors the effect will be an edge synchronous with the negative clock edge

where the edge direction is determined by the D input right before the clock edge arises. The ULV logic

is only susceptible to edges and by applying the outputs of the LEC we may trigger an ULV inverter.

There are significant problems with the LEC; firstly the clock load is very large and secondly the input is

connected to a gate terminal and will pull current from the gates driving the input signals. However, the

focus in this paper is on speed rather than power. In terms of power delay product the ULV FF is

comparable to most conventional flip-flops.

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3.2 High Speed Edge Processing Inverter

The high speed edge processing inverters (U) inverts the edges provided by the LEC circuits. An

invariant of the LEC circuits is that the edge occurring at one of the a outputs will be inverse of the edge

occurring at one of the b’s. Accordingly the outputs of the U inverters will provide a differential signal,

i.e. ULV = D and ULV = D. When φ = 1 the U inverters will recharge in a similar manner as the LEC

circuits. In the recharge mode the U inverters are not susceptible to inputs provided by the LEC’s. The

outputs of the U inverters are not determined and will not affect the output stage due to the pass

transistors of the output stage. It is crucial that the time required to provide a valid output signal of the U

inverters determined by the value of D and D when φ switches from 1 to 0. The delays from the clock

edge to the U inverters have to be significantly less than the delay through the pass transistor to prevent

glitches. Simulated data from the Spectre simulator show that only 10% of the total delay from the clock

edge to outputs Vout and Vout is due to the LEC and U circuits. After the U inverters have responded

they will not be affected by changes in the inputs D and D, or more precisely any changes in the inputs

will only strengthen the LEC outputs.

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3.3 Output stage

The output stage consists of two nMOS pass transistors and two inverters. The outputs of the U

inverters are not significant in the hold phase due to the pass transistors that are turned OFF. The nMOS

pass transistors may be replaced by transmission gates if the delay of the outputs needs to be balanced.

Furthermore, the pass transistors must be able to provide more current than the cross coupled inverters

when turned on in order to change the outputs.The cross coupled inverter replaced by cmos floating gate

inverters. The transistors used in the ULV FF are minimum with sized the exception of the pass

transistors that are four times the minimum width.

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Fig 4.ULV FF In The Recharge Phase

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Fig 5. ULV FF In The Evaluate Phase

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3.4 ULV FF operation

The ULV FF in the recharge phase is shown in Fig. 4. In this phase the input stage or the level to edge

converter (LEC) will follow the input signal. The ULV inverters will recharge and are not susceptible to

any changes in the input stage. The outputs of the ULV inverters will be close to VDD/2 and hence

turning of the pass transistors further. The cross coupled inverters in the output stage may be designed

using minimum sized transistors. The significant constraint is that the output of the LEC circuits are

sufficiently close to their respective inputs. The FF is not susceptible to transparency problems due to

non-transparency between the LEC circuit and ULV inverters and between the ULV inverters and the

output stage. A critical situation producing glitches may occur if the delay of the, recharged circuits, i.e.

LEC’s and the ULV inverters, are too large compared to the delay of the pass transistors. The delay of

the recharged circuits is typically less than 10% of the CMOS pass transistor or a CMOS inverter. The

ULV FF in the evaluate phase, assuming that D = 1, is shown in Fig. 5. When the clock signals arrives,

that is a negative φ edge, one of the alternative outputs of each LEC circuits will inverts the clock edge

like a complementary inverter. The delay is very small compared to a complementary inverter due to the

boost imposed by the clock signals. The responses of the LEC circuits are always synchronous with the

clock signals applied. In this case the ULV inverters are ready to respond to a voltage change of the LEC

outputs. The ULV inverters will respond quickly due to a floating precharged level of VDD/2 and the

boost gained from the input, i.e. LEC output. The pass transistors are turned on and the latched value

will be available at the output. The pass transistors have to be strong enough to override the cross-

coupled inverters. An alternative will be to use clocked CMOS in the output stage or additional pass

transistors or transmission gates. Note that the FF appears as transparent as long as the clock signal φ is

low. However, this is not the case due to the inherent characteristics of the ULV logic:

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4.Future work:

The cmos floating capacitance applied in the simulation are equal to 800 pf.

Design of registers using Cmos flip flops.

Power consumption and speed is noted and compared with the cmos floating gate D flip flop

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REFERENCES

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[9] Y. Berg, O. Mirmotahari, P.A. Norseng and S. Aunet: “Ultra Low Voltage CMOS gates”, In Proc.

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design of cmos flip flop using floating gates

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