EE323: DESIGN OF A BJT OP-AMP 1

Design of a Discrete BJT Operational AmplifierMichael Jones, Student Member, IEEE, Audio Engineering Society

Abstract—The operational amplifier consists three basic stages.• High Impedance, Differential Input Amplifier• Voltage Amplification Stage• Single-Ended Low Impedance Output

The components, and stages of an integrated circuit op-ampare direct-coupled. Direct coupling presents many challenges tothe designer. These challenges will be explored, as a simple,three stage discrete BJT op-tamp will be designed, simulated,characterized, and finally implemented.

I. INTRODUCTION

Many of the design restrictions, and challenges in analogIC design arise from limited chip size. Therefore, resistancesare kept low, and the use of capacitors is limited. Otheractive devices, such as inductors, are impractical due to theirsize. Transistors, due to their small size, are called upon toprovide many functions in the integrated circuit; includingresistance (active-loads), current/voltage amplification, and thecreation of current sources, i.e.current mirrors, for biasing.Transistors are the most numerous component in any IC.Another challenge in IC design comes from the direct couplingof transistors. Transistors must be biased so that they providetheir intended functionality, while properly biasing transistorsthey are directly coupled to. This biasing point of a transistoris also called the quiescent operating point, Q-point, or DCoperating point. A BJT transistor can be biased with a current,or a voltage. Proper biasing is one of the most important stepsin the design of integrated circuits. An IC op-amp is a direct-coupled high-gain amplifier, usually consisting of one or moredifferential amplifiers, followed by a DC level shifter, and alow impedance output stage [1]. The following paper presentsthe design, analysis, and implementation of a discrete BJToperational amplifier, using direct coupling, and no capacitors.

II. CIRCUIT TOPOLOGY

A. Differential Input StageThe first stage of the op-amp is a differential amplifier with

high input impedance, see figure 1. A Darlington Pair at theinput increases the input impedance by a factor of !. The inputimpedance of the op-amp is equal to the input impedance ofthe first stage. It is calculated with equation 1

Zin = 2!Q1!Q2(re!2 + RE1) (1)

A cascode current mirror was designed to sink 1mA. Thiscurrent biases the first stage. The 1mA current gets dividedequally between transistor pairs, Q1,2, and Q3,4, see AppendixA. The cascode current mirror was chosen for it’s large outputimpedance, ro!, see equations 2, 3. This impedance reduces thecommon mode gain, eq. 5, and increases the common moderejection ration, (CMRR), eq. 6.

ro! =|VA|Ibias

(2)

ro!cascode = !(ro!) (3)

Avdb =!Rc

re! + Re(4)

Acm =!Rc

re! + Re + 2ro!cascode

(5)

CMRR =Avdb

Acm=

re! + Re + 2ro!cascode

re! + Re(6)

Emitter degeneration, RE1, and RE2, was used as a formof negative feedback for this stage. The addition of theseresistors reduces the gain of the stage, eq. 4, and increases theinput impedance, eq. 1. However, emitter degeneration helpsto reduce non-linear distortion, and increase the large-signaltransfer characteristic [2], [3]. The value for RE1, and RE2was determined using equation 7, [2].

Re =40VT

Ibias(7)

A comparison of figures 2, and 3 demonstrates the effectemitter degeneration has on the linear operating range. RC1and RC2 are used to drop a third of the supply voltage at thenodes Vout1, and Vout2. These collector resistors also affectthe final gain of the stage, eq. 4. Table I lists these parametervalues. The experimental output of the first stage circuit canbe viewed in figure 4.

B. Voltage Amplification StageThis stage is designed for large amounts of gain. An active

load is used to achieve a large resistance value, eq. 2. The PNPtransistors used have an early voltage, VA, equal to 120V. Thetransistors are being biased with 2mA; therefore, the activeload is equivalent to 60k!. Active loads make large gainspossible, without taking up too much ”real estate”. The gain ofthe second stage can be calculated with eq.8. A cascode currentmirror was chosen to bias transistors Q9, Q10, Q11, and Q12.However, unlike the first stage, eq.9 is used to calculate theCMRR.

Avds =ro!

2(re! + Re)(8)

CMRR =Avds

Acm=

re! + Re + 2ro!cascode

2(re! + Re)(9)

VOUT3 = (IcQ12 ! IcQ10)ro!Q12

(10)

EE323: DESIGN OF A BJT OP-AMP 2

Emitter degeneration was used again to increase linearity,and reduce distortion [2]. The biasing of the output, Vout3, ofthis stage is not as straight forward as the biasing of the firststage’s output. The impedance the amplifier sees looking intothe collector of Q12 is not the same impedance the current seeslooking into the emitter of that transistor. This voltage dropcan be estimated by using equation 10, [5]. This equation stillgives you a ”ballpark” figure. It is also worthwhile to note thatthis voltage drop is current dependent. One has to keep in mindthat an increase in current causes a decrease in ro’. The finetuning of R2 allows one to see the effect that the bias currenthas on the operating point of V out3. Figures 5, and 6 showthe experimental, and SPICE output waveforms for this stage.Both figures display output distortion.This distortion is due tothe lack of headroom at Vout3. The voltage amplification stageprovides a gain of " 60. See table I.

C. DC Level Shifter and Class A-Output StageThe last two stages of the op-amp are composed of a PNP

common emitter (CE) amplifier, and a NPN emitter follower,[2]. The PNP acts as a DC level shifter, and as the last gainstage for the op-amp, eq.11,

ACE =!Rc3

re! + Re5(11)

The +0.7V shift from V out3 to the emitter of Q17 allowsthe the PNP to be biased with a current of the designer’schoosing. This current, IQ17 will be:

IQ17 = V pp"VE17RE5

A current of " 1.1mA was chosen. The additional 100uAaccounts for the base current of transistor Q18 . This basecurrent was calculated as follows.

Ibase = Ibias!Q18

The voltage at node VC17 is selected to be " +0.7Vabove the desired output value. Node VC17 was biased at 1V .The resistor RC3 accomplishes this biasing, and it’s value iscalculated as follows:

RC17 = 1V "VNNIRC3

Note: RE5, and RC3 must be carefully selected, as each affectsthe biasing of Q17, and the output voltage offset. The emitterfollower, Q13, is biased with a cascode current mirror thatsinks 11.3mA of current. The emitter resistance for the NPNemitter follower is ro!Q20

. This stage is a class A output stage.An amplifier in which the transistor is on for the entire outputcycle is called ”class A” [3]. This output was chosen for it’ssimplicity, and it’s linearity [3]. The output node V out hasa final theoretical offset of 0.3V , see Appendix A. Figure7, and 8 shows the SPICE, and experimental output of thediscrete BJT operational amplifier. It is not possible to attainan input voltage in the laboratory that is low enough to obtainan accurate open loop gain of the operation amplifier. Hence,the voltage output in fig.8 is ”railing”. The linearity of theoperational amplifier can be seen in figure 9, which shows theoffset of the output, at +358mV input. Figure 9 also shows

that the op-amp will behave linearly for a voltage input of-2mV to 1mV.

III. CHARACTERIZATION

Table II shows various characterization parameters for thesimulated circuit. The input bias current can be found bymeasuring the base currents of transistors, Q1, andQ3 [1]. Theinput offset current can be found by calculating the folllowing:

Ioffset = |IBQ1 ! IBQ2|

The input offset voltage is defined as the voltage that mustbe applied at the input to null the output [1]. This value wasfound by grounding the inverting input, and sweeping the DCsource of the non-inverting. The frequency response of thesimulated circuit is shown in figure 10. Figure 10 was usedto find the value for ft, and fBOL. It is worth noting thatthe fBOL for a µ741A is around 10Hz. The low fBOL for aµ741A is due to the presence of a small, " 30pF , frequencycompensating capacitor in the circuit [4]. The slew rate of theop-amp was tested with the circuit in figure 13. This circuittests how fast the op-amp can track the input voltage. The slewrate is defined in equation 12. Similar to the fBOL, the slewrate is higher for an amplifier without a capacitor. Equation13 shows the relationship between slew rate and capacitance.Capacitance reduces slew rate [4]. The value obtained duringthe SPICE simulation is highly dependent on the accuracy ofthe model for the transistors used. The accuracy of the valueobtained is questionable, see table II.

SR =dVout

dt|maximum (12)

dVout

dt=

I

C(13)

It is interesting to view the common mode output as afunction of frequency, figure 14. The CMRR of this op-ampdegrades after 10kHz, at an average rate of about "20dB

dec .

IV. NEGATIVE FEEDBACK CIRCUITS

The op-amp was placed in Inverting, and Non-Inverting cir-cuit configurations to test it’s operation in negative feedback,figure 15. Figure 10 displays the effect closed loop gain hason the frequency response of the op-amp. Notice, as ACL,decreases,fBCL increases. This relationship is well defined,and is termed the Gain!Bandwidth Product, see equation14.

ft = AOLfBOL = ACLfBCL (14)

Figure 16 shows the simulated output of the op-amp whenplaced in non-inverting configuration. The design behaves, asexpected. Figure 11 shows the experimental output when thecircuit is configured as a non-inverting voltage follower. TableIII displays the gain calculated from figure 11.

EE323: DESIGN OF A BJT OP-AMP 3

V. EXPERIMENTAL RESULTS

The op-amp circuit designed was built, and tested stage,by stage in the laboratory. The first stage performed well.The bias voltage, and currents were comparable to theoretical,and SPICE values. However, the first stage of gain wasless than expected. The second stage performed as expected.Figures 5, and 6 display the similarity between simulated, andexperimental results. Table I shows the gain of the secondstage varies from both SPICE, and theoretical. However, thecumulative gain

Avd1 #Avd2

is 505 for SPICE, and 497, for experimental. These resultsare very close. The last stage did show clipping, in responseto the smallest input that could be obtained in the laboratory," 10mV , see figure 8. This result was expected. The exper-imental circuit behaved erratically when placed in negativefeedback. The circuit would work as a voltage follower;however, fine tuning of resistors RE5, and RC5, along withchecking, and re-checking the bias points, and currents ofthe PNP CommonEmitter stage was required. It was notpossible to obtain results for closed loop gains higher than one.These difficulties made further experimental characterizationof the device nearly impossible. During troubleshooting, Itwas found that DC bias point of node VC17 was higher thanexpected. It was also found that the output of the BJT op-ampwas biased at -2.8V. Standard troubleshooting measures weretaken; including, checking wiring, breadboard functionality,and signal chain continuity. Additional emitter resistance wasadded to Q18, in an attempt raise the DC offset at output. Thisresistance was shown to raise output voltage offset in SPICE;however, it did not change the offset value in the laboratory.

VI. DISCUSSION AND CONCLUSION

The obvious flaw in the design of this discrete operationalamplifier lies in the output stage. The implementation ofa CE/CC output stage is difficult. Inherent difficulties liein choosing values for RC3, and RE5 that will create theproper bias current for the PNP , and provide the properlevel shift for the desired output voltage. This type of outputstage does not provide any temperature compensation. Voltageoffset at the output will drift with temperature changes. Furtherinvestigation into output stage, topology and negative feedbackis required to obtain a stable operational amplifier.

Fig. 1. Discrete BJT Operational Amplifier Circuit Topology

Fig. 2. Transfer Characteristic of First Stage without Emitter Degeneration

Fig. 3. Transfer Characteristic of First Stage with Emitter Degeneration

TABLE IDEVICE PARAMETERS FOR BJT OPERATIONAL AMPLIFIER

Device Paramaters SPICE Theoretical ExperimentalZin 9.50M! 21M! 20.8M!

Zout 230! 136! xAvd1 6.4 9.6 4.36Avd2 79 63.4 114Avd3 12.2 12.8 x

Total Avd 6723 6513 870Acm1 -61dB -66dB -14dBAcm2 -38db -44dB x

AcmTotal -77dB -110dB xCMRR 153.5dB 186dB 73dB

EE323: DESIGN OF A BJT OP-AMP 4

Fig. 4. Output of Differential Input Stage

Fig. 5. Gain and DC Offset of Voltage Amplification Stage

Fig. 6. SPICE Simulated Output of Voltage Amplification Stage

Fig. 7. SPICE Simulated Maximum OutputSwing of Operational Amplifier

Fig. 8. Experimental Maximum OutputSwing of Operational Amplifier

Fig. 9. SPICE Generated Voltage Transfer Characteristic of BJT Op-Amp

Fig. 10. Frequency Response of BJT Operational Amplifier

EE323: DESIGN OF A BJT OP-AMP 5

Fig. 11. BJT Op-Amp Configured as Non-Inverting Voltage Follower

Fig. 12. Test Circuit used to Determine SlewRate

Fig. 13. Output of Voltage Follower used to Determine Slew Rate

Fig. 14. Frequency Response of Common Mode Output

APPENDIX ADC BIAS POINT ANALYSIS

Bias Point SPICE Theoretical Experimental UnitsVout1 9.98 10.00 9.9 VVout2 9.97 10.00 9.9 VVout3 12.84 13.00 12.6 VVout 0.36 0.30 -2.8 VJ1 -1.63 -1.40 -1.54 VJ2 8.34 9.30 8.3 V

VE17 13.50 13.70 13.2 VVC17 1.55 1 5.3 VVm1 -13.69 -13.60 -13.6 VVm2 14.33 14.30 14.3 VVm3 -13.61 -13.60 -13.6 VVm4 -13.52 -13.60 -13.6 V

Ic(Q1): 4.64E-06 5.50E-04 x AIb(Q1): 1.04E-07 5.00E-08 x AIe(Q1): -4.7E-06 -5.0E-06 x AIc(Q2): 4.8E-04 5.0E-04 x AIb(Q2): 4.7E-06 5.0E-06 x AIe(Q2): -4.8E-04 -5.0E-06 x AIc(Q3): 4.6E-06 5.0E-04 x AIb(Q3): 1.0E-07 5.0E-08 x AIe(Q3): -4.7E-06 -5.0E-06 x AIc(Q4): 4.8E-04 5.0E-04 x AIb(Q4): 4.7E-06 5.0E-06 x AIe(Q4): -4.8E-04 -5.0E-06 x AI(Rc1): 5.0E-04 5.0E-04 x AI(Rc2): 5.0E-04 5.0E-04 x AI(R1): 1.0E-03 1.0E-03 x AIc(Q5): 9.9E-04 1.0E-03 x AIb(Q5): 1.0E-05 1.0E-05 x AIe(Q5): -1.0E-03 -1.0E-03 x AIc(Q6): 9.7E-04 1.0E-03 9.80E-04 AIb(Q6): 1.1E-05 1.0E-05 x AIe(Q6): -9.8E-04 -1.0E-03 x AIc(Q7): 9.8E-04 1.0E-03 x AIb(Q7): 9.9E-06 1.0E-05 x AIe(Q7): -9.9E-04 -1.0E-03 x AIc(Q8): 9.8E-04 1.0E-03 x AIb(Q8): 9.9E-06 1.0E-06 x AIe(Q8): -9.9E-04 -1.0E-03 x AIc(Q9): 1.9E-03 2.0E-03 x AIb(Q9): 1.8E-05 2.0E-05 x AIe(Q9): -1.9E-03 -2.0E-03 x A

Ic(Q10): 1.9E-03 2.0E-03 x AIb(Q10): 2.4E-05 2.0E-05 x AIe(Q10): -1.9E-03 -2.0E-03 x A

EE323: DESIGN OF A BJT OP-AMP 6

APPENDIX BDC BIAS POINT ANALYSIS CONT.

Bias Point SPICE Theoretical Experimental UnitsIb(Q11): -1.9E-05 -2.0E-05 x AIe(Q11): 1.9E-03 2.0E-03 x AIc(Q12): -1.9E-03 -2.0E-03 x AIb(Q12): -1.9E-05 -2.0E-05 x AIe(Q12): 1.9E-03 2.0E-03 x AI(R2): 4.0E-03 4.0E-03 x A

Ic(Q13): 3.9E-03 4.0E-03 x AIb(Q13): 3.8E-05 4.0E-05 x AIe(Q13): -4.0E-03 -4.0E-03 x AIc(Q14): 3.9E-03 4.0E-03 4.00E-03 AIb(Q14): 3.0E-05 4.0E-05 x AIe(Q14): -3.9E-03 -4.0E-03 x AIc(Q15): 3.9E-03 4.0E-03 x AIb(Q15): 3.7E-05 4.0E-05 x AIe(Q15): -3.9E-03 -4.0E-03 x AIc(Q16): 3.9E-03 4.0E-03 x AIb(Q16): 3.7E-05 4.0E-05 x AIe(Q16): -3.9E-03 -4.0E-03 x AIc(Q17): -1.2E-03 -1.1E-03 x AIb(Q17): -1.1E-05 1.1E-05 x AIe(Q17): 1.2E-03 1.1E-03 x AI(Re5): 1.2E-03 1.1E-03 1.80E-03 AI(Rc3): 1.1E-03 9.0E-04 1.70E-03 A

Ic(Q18): 1.9E-02 2.0E-02 x AIb(Q18): 1.8E-04 2.0E-04 x AIe(Q18): -1.9E-02 -2.0E-02 x AI(R3): 1.1E-02 11..3e-3 x A

Ic(Q19): 1.9E-02 2.0E-02 x AIb(Q19): 2.2E-04 2.0E-05 x AIe(Q19): -2.0E-02 -2.0E-02 x AIc(Q20): 1.1E-02 1.1E-02 1.13E-02 AIb(Q20): 1.8E-05 2.0E-05 x AIe(Q20): -1.1E-02 -1.1E-02 x AIc(Q21): 1.9E-02 2.0E-02 x AIb(Q21): 2.2E-04 2.0E-04 x AIe(Q21): -1.9E-02 -2.0E-02 x AIc(Q22): 1.9E-02 2.0E-02 x AIb(Q22): 2.2E-04 2.0E-05 x AIe(Q22): -1.9E-02 -2.0E-02 x A

REFERENCES

[1] R. Gayakwad , Op-Amps and LInear Integrated Circuits, 3rd ed. En-glewood Cliffs, New Jersey: Prentice Hall, 1993.

[2] A. Hambley , Electronics, 2nd ed. Upper Saddle River, New Jersey:Prentice Hall, 2000.

[3] B. Rasavi , Fundamentals of Micro-Electronics, 2nd ed. Hoboken, NJ:Wiley, 2008.

[4] R. Pease(editor), M. Thompson, Analog Circuits-Chapter3, 2nd ed.Hoboken, NJ: Wiley, 2008.

[5] C. Crespo, Transistor Study Guide, 1st ed. Portland, OR: OIT, 2009.

Fig. 15. Negative Feedback Amplifiers

Fig. 16. Non-Inverting Amplifier with a ACL of 10

TABLE IICHARACTERISTICS OF BJT OPERATIONAL AMPLIFIER

Characteristics SPICE UnitsInput Bias Current 142 nA

Input Offset Current 4 pAInput Offset Voltages 47uV uV

ft 35 MHzfbol 60 kHz

SlewRate 20 kVus

TABLE IIIGAIN-BANDWIDTH OF BJT OP-AMP

Circuits Acl fbcl Actual GainNon-Inverting 1000 557kHz xNon-Inverting 500 1.2MHz xNon-Inverting 100 5.7MHz xNon-Inverting 10 14.7Mhz xNon-Inverting 1 26MHz 0.57

Inverting -1000 539kHz xInverting -500 1.2MHz xInverting -100 5.6MHz xInverting -10 14.4MHz xInverting 1 24MHz x