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Design Kit Development

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Advanced Design System 2011

September 2011Design Kit Development


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© Agilent Technologies, Inc. 2000-20115301 Stevens Creek Blvd., Santa Clara, CA 95052 USANo part of this documentation may be reproduced in any form or by any means (includingelectronic storage and retrieval or translation into a foreign language) without prioragreement and written consent from Agilent Technologies, Inc. as governed by UnitedStates and international copyright laws.

AcknowledgmentsMentor Graphics is a trademark of Mentor Graphics Corporation in the U.S. and othercountries. Mentor products and processes are registered trademarks of Mentor GraphicsCorporation. * Calibre is a trademark of Mentor Graphics Corporation in the US and othercountries. "Microsoft®, Windows®, MS Windows®, Windows NT®, Windows 2000® andWindows Internet Explorer® are U.S. registered trademarks of Microsoft Corporation.Pentium® is a U.S. registered trademark of Intel Corporation. PostScript® and Acrobat®are trademarks of Adobe Systems Incorporated. UNIX® is a registered trademark of theOpen Group. Oracle and Java and registered trademarks of Oracle and/or its affiliates.Other names may be trademarks of their respective owners. SystemC® is a registeredtrademark of Open SystemC Initiative, Inc. in the United States and other countries and isused with permission. MATLAB® is a U.S. registered trademark of The Math Works, Inc..HiSIM2 source code, and all copyrights, trade secrets or other intellectual property rightsin and to the source code in its entirety, is owned by Hiroshima University and STARC.FLEXlm is a trademark of Globetrotter Software, Incorporated. Layout Boolean Engine byKlaas Holwerda, v1.7 http://www.xs4all.nl/~kholwerd/bool.html . FreeType Project,Copyright (c) 1996-1999 by David Turner, Robert Wilhelm, and Werner Lemberg.QuestAgent search engine (c) 2000-2002, JObjects. Motif is a trademark of the OpenSoftware Foundation. Netscape is a trademark of Netscape Communications Corporation.Netscape Portable Runtime (NSPR), Copyright (c) 1998-2003 The Mozilla Organization. Acopy of the Mozilla Public License is at http://www.mozilla.org/MPL/ . FFTW, The FastestFourier Transform in the West, Copyright (c) 1997-1999 Massachusetts Institute ofTechnology. All rights reserved.

The following third-party libraries are used by the NlogN Momentum solver:

"This program includes Metis 4.0, Copyright © 1998, Regents of the University ofMinnesota", http://www.cs.umn.edu/~metis , METIS was written by George Karypis([email protected]).

Intel@ Math Kernel Library, http://www.intel.com/software/products/mkl

SuperLU_MT version 2.0 - Copyright © 2003, The Regents of the University of California,through Lawrence Berkeley National Laboratory (subject to receipt of any requiredapprovals from U.S. Dept. of Energy). All rights reserved. SuperLU Disclaimer: THISSOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSEARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF SUCH DAMAGE.

7-zip - 7-Zip Copyright: Copyright (C) 1999-2009 Igor Pavlov. Licenses for files are:7z.dll: GNU LGPL + unRAR restriction, All other files: GNU LGPL. 7-zip License: This libraryis free software; you can redistribute it and/or modify it under the terms of the GNULesser General Public License as published by the Free Software Foundation; eitherversion 2.1 of the License, or (at your option) any later version. This library is distributedin the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the impliedwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

http://www.xs4all.nl/~kholwerd/bool.html

http://www.xs4all.nl/~kholwerd/bool.html

http://www.mozilla.org/MPL/

http://www.mozilla.org/MPL/

http://www.cs.umn.edu/~metis

http://www.cs.umn.edu/~metis

http://www.intel.com/software/products/mkl

http://www.intel.com/software/products/mkl


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Lesser General Public License for more details. You should have received a copy of theGNU Lesser General Public License along with this library; if not, write to the FreeSoftware Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.unRAR copyright: The decompression engine for RAR archives was developed using sourcecode of unRAR program.All copyrights to original unRAR code are owned by AlexanderRoshal. unRAR License: The unRAR sources cannot be used to re-create the RARcompression algorithm, which is proprietary. Distribution of modified unRAR sources inseparate form or as a part of other software is permitted, provided that it is clearly statedin the documentation and source comments that the code may not be used to develop aRAR (WinRAR) compatible archiver. 7-zip Availability: http://www.7-zip.org/

AMD Version 2.2 - AMD Notice: The AMD code was modified. Used by permission. AMDcopyright: AMD Version 2.2, Copyright © 2007 by Timothy A. Davis, Patrick R. Amestoy,and Iain S. Duff. All Rights Reserved. AMD License: Your use or distribution of AMD or anymodified version of AMD implies that you agree to this License. This library is freesoftware; you can redistribute it and/or modify it under the terms of the GNU LesserGeneral Public License as published by the Free Software Foundation; either version 2.1 ofthe License, or (at your option) any later version. This library is distributed in the hopethat it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU LesserGeneral Public License for more details. You should have received a copy of the GNULesser General Public License along with this library; if not, write to the Free SoftwareFoundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Permission ishereby granted to use or copy this program under the terms of the GNU LGPL, providedthat the Copyright, this License, and the Availability of the original version is retained onall copies.User documentation of any code that uses this code or any modified version ofthis code must cite the Copyright, this License, the Availability note, and "Used bypermission." Permission to modify the code and to distribute modified code is granted,provided the Copyright, this License, and the Availability note are retained, and a noticethat the code was modified is included. AMD Availability:http://www.cise.ufl.edu/research/sparse/amd

UMFPACK 5.0.2 - UMFPACK Notice: The UMFPACK code was modified. Used by permission.UMFPACK Copyright: UMFPACK Copyright © 1995-2006 by Timothy A. Davis. All RightsReserved. UMFPACK License: Your use or distribution of UMFPACK or any modified versionof UMFPACK implies that you agree to this License. This library is free software; you canredistribute it and/or modify it under the terms of the GNU Lesser General Public Licenseas published by the Free Software Foundation; either version 2.1 of the License, or (atyour option) any later version. This library is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITYor FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License formore details. You should have received a copy of the GNU Lesser General Public Licensealong with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St,Fifth Floor, Boston, MA 02110-1301 USA Permission is hereby granted to use or copy thisprogram under the terms of the GNU LGPL, provided that the Copyright, this License, andthe Availability of the original version is retained on all copies. User documentation of anycode that uses this code or any modified version of this code must cite the Copyright, thisLicense, the Availability note, and "Used by permission." Permission to modify the codeand to distribute modified code is granted, provided the Copyright, this License, and theAvailability note are retained, and a notice that the code was modified is included.UMFPACK Availability: http://www.cise.ufl.edu/research/sparse/umfpack UMFPACK(including versions 2.2.1 and earlier, in FORTRAN) is available athttp://www.cise.ufl.edu/research/sparse . MA38 is available in the Harwell SubroutineLibrary. This version of UMFPACK includes a modified form of COLAMD Version 2.0,originally released on Jan. 31, 2000, also available athttp://www.cise.ufl.edu/research/sparse . COLAMD V2.0 is also incorporated as a built-infunction in MATLAB version 6.1, by The MathWorks, Inc. http://www.mathworks.com .COLAMD V1.0 appears as a column-preordering in SuperLU (SuperLU is available athttp://www.netlib.org ). UMFPACK v4.0 is a built-in routine in MATLAB 6.5. UMFPACK v4.3is a built-in routine in MATLAB 7.1.

Qt Version 4.6.3 - Qt Notice: The Qt code was modified. Used by permission. Qt copyright:Qt Version 4.6.3, Copyright (c) 2010 by Nokia Corporation. All Rights Reserved. Qt

http://www.7-zip.org/

http://www.7-zip.org/

http://www.cise.ufl.edu/research/sparse/amd

http://www.cise.ufl.edu/research/sparse/amd

http://www.cise.ufl.edu/research/sparse/umfpack

http://www.cise.ufl.edu/research/sparse/umfpack

http://www.cise.ufl.edu/research/sparse




http://www.mathworks.com

http://www.mathworks.com

http://www.netlib.org

http://www.netlib.org


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License: Your use or distribution of Qt or any modified version of Qt implies that you agreeto this License. This library is free software; you can redistribute it and/or modify it undertheterms of the GNU Lesser General Public License as published by the Free SoftwareFoundation; either version 2.1 of the License, or (at your option) any later version. Thislibrary is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITYor FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License formore details. You should have received a copy of the GNU Lesser General Public Licensealong with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St,Fifth Floor, Boston, MA 02110-1301 USA Permission is hereby granted to use or copy thisprogram under the terms of the GNU LGPL, provided that the Copyright, this License, andthe Availability of the original version is retained on all copies.Userdocumentation of any code that uses this code or any modified version of this code mustcite the Copyright, this License, the Availability note, and "Used by permission."Permission to modify the code and to distribute modified code is granted, provided theCopyright, this License, and the Availability note are retained, and a notice that the codewas modified is included. Qt Availability: http://www.qtsoftware.com/downloads PatchesApplied to Qt can be found in the installation at:$HPEESOF_DIR/prod/licenses/thirdparty/qt/patches. You may also contact BrianBuchanan at Agilent Inc. at [email protected] for more information.

The HiSIM_HV source code, and all copyrights, trade secrets or other intellectual propertyrights in and to the source code, is owned by Hiroshima University and/or STARC.

Errata The ADS product may contain references to "HP" or "HPEESOF" such as in filenames and directory names. The business entity formerly known as "HP EEsof" is now partof Agilent Technologies and is known as "Agilent EEsof". To avoid broken functionality andto maintain backward compatibility for our customers, we did not change all the namesand labels that contain "HP" or "HPEESOF" references.

Warranty The material contained in this document is provided "as is", and is subject tobeing changed, without notice, in future editions. Further, to the maximum extentpermitted by applicable law, Agilent disclaims all warranties, either express or implied,with regard to this documentation and any information contained herein, including but notlimited to the implied warranties of merchantability and fitness for a particular purpose.Agilent shall not be liable for errors or for incidental or consequential damages inconnection with the furnishing, use, or performance of this document or of anyinformation contained herein. Should Agilent and the user have a separate writtenagreement with warranty terms covering the material in this document that conflict withthese terms, the warranty terms in the separate agreement shall control.

Technology Licenses The hardware and/or software described in this document arefurnished under a license and may be used or copied only in accordance with the terms ofsuch license. Portions of this product include the SystemC software licensed under OpenSource terms, which are available for download at http://systemc.org/ . This software isredistributed by Agilent. The Contributors of the SystemC software provide this software"as is" and offer no warranty of any kind, express or implied, including without limitationwarranties or conditions or title and non-infringement, and implied warranties orconditions merchantability and fitness for a particular purpose. Contributors shall not beliable for any damages of any kind including without limitation direct, indirect, special,incidental and consequential damages, such as lost profits. Any provisions that differ fromthis disclaimer are offered by Agilent only.

Restricted Rights Legend U.S. Government Restricted Rights. Software and technicaldata rights granted to the federal government include only those rights customarilyprovided to end user customers. Agilent provides this customary commercial license inSoftware and technical data pursuant to FAR 12.211 (Technical Data) and 12.212(Computer Software) and, for the Department of Defense, DFARS 252.227-7015(Technical Data - Commercial Items) and DFARS 227.7202-3 (Rights in CommercialComputer Software or Computer Software Documentation).

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About Design Kit Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ADS Design Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Design Kits versus Component Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supported Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supporting Multiple ADS Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Support for Additional Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ADS Design Kit Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Design Kit Standard Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Updating Non-Standard Design Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Understanding the ADS Design Kit File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overview of the File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Potential Directories in an ADS Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Understanding the Directory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Basic Parts of an ADS Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Design Kit Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Library Definition File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Components in a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Model Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 The eesof_lib.cfg Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AEL Code for Loading a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 The about.txt File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 The Example Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Design Kit Development for Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Demonstration Design Kit (SampleKit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 General Process for Adding Artwork to a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Specifying Technology File Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Adding Layout Artwork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Testing the Artwork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Adding DRC Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Configuring Design Kit Components for use with ADS Netlist Exporter . . . . . . . . . . . . . . . . . . 84

Additional Parts for ADS Design Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Adding Simulation Data to a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Parameter Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Netlist Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Creating Design Kit Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Layers and Preferences Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Adding Custom Fill Patterns to a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Advanced Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Completing the Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Verifying a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Assigning a Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Packaging for Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Supporting a Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

ADS Design Kit Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Tutorial Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Building the Basic Design Kit Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Accessing the Supplied Sample Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Design Kit Development for RFIC Dynamic Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 RFIC Dynamic Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Design Kits for RFIC Dynamic Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Generic Add-on Toolbar Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Adding the Generic Add-On Toolbar to your Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Removing the Generic Add-On Toolbar from your Workspace . . . . . . . . . . . . . . . . . . . . . . . . 158 Using the Generic Add-on Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158


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About Design Kit DevelopmentAdvanced Design System ( ADS) from Agilent Technologies is a tool used by engineers fora variety of design applications, such as RFIC, System, MMIC, Hybrid or Board leveldesign. In order to effectively use the design environment and to take advantage of itspowerful simulation capabilities, designers must have a library of components that arelinked to model files or simulation data.

For IC designers, the components and models are typically distributed by a foundry in theform of a design kit. A unique design kit is created for each process and each CAD tool.This kit is provided to the foundry customer to use when designing their circuit. To help ICdesigners become more successful with our Electronic Design Automation (EDA) software,Agilent Technologies has been working with popular foundries to provide ADS componentsand translated model files for distribution by the foundry to the IC designer. Variouscustomers are also creating design kits on their own.

Design kits in ADS are not only beneficial to IC designers. This library structure can beused for any technology or process to package and distribute a reusable set ofcomponents. With the information provided in this document, anyone can create designkits for use in ADS.

This section educate and assist you to develop a design kit for the first time using astandard methodology. In addition to provide assistance to first time design kitdevelopers, this section also provides information to aid in troubleshooting problems with legacy design kits and updating these kits to the new standard.

A design kit combines functionality and features of various parts of ADS. Therefore, thissection contains various cross-references to other ADS topics. Familiarity with ADS, aswell as prior experience with ADS Application Extension Language (AEL), improves yourunderstanding of this section and the process of creating a design kit. At a higher level,understanding this document and the concepts presented in it will guide you in thedevelopment of an integrated design flow using ADS.

The final intent of this section is to encourage standardization of ADS design kits. Thisincludes formalizing the structure, as well as the file formats and naming conventions, fordesign kits used in, but not limited to, the ADS Front End Design Flow and RFIC DynamicLink Flow. It is absolutely imperative that your design kit follows this structure to avoidconflicts with other kits. For more information, refer to Supported Design Flows.

NoteFor ADS 2011 releases prior to ADS 2011.10, the recommended way to create a design kit was bycreating the design kit, as usual, in ADS 2009U1, and then upgrading it to be ADS 2011 compatible. Theprocedure outlined in this document, guides you to create a design kit natively in ADS2011.10. Note thatthese kits created in ADS2011.10 are not backward compatible. If you have design kits createdusing ADS 2009U1, you can still upgrade them to be ADS2011 compatible following the process describedin ADS 2011 PDK Upgrade.

ADS Design Kits An ADS Design Kit is a logical grouping of files related to a set of ADS components. Thedesign kit structure is self-contained to provide easy transfer between different users orcomputer platforms. All component information needed by Advanced Design System isstored within the design kit.

At a minimum, a design kit must include a component definition file, schematic symbolfiles (unless built-in generic symbols are used), and information for the circuit simulator inthe form of a model file, data file, or a schematic or netlisted subcircuit. Additionally,other optional files can be provided to extend the functionality of the design kit.

A design kit has a directory structure that is recognized by ADS and is similar to thedirectory structure for the ADS installation. All files are stored in specific directoriesdepending on the type of file. Your ADS design kit must follow this structure, as defined


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in Understanding the ADS Design Kit File Structure. Any deviation from this pre-definedstructure can lead to serious complications with your design kit, including an inability tosimulate your designs in ADS. Custom extensions within design kits can also interferewith built-in tools in ADS and cause them to fail.

The simplest way to build a design kit is to follow the tutorial steps in ADS Design KitTutorial of this document to create a sample design kit. You can then use the informationin Basic Parts of an ADS Design Kit and Additional Parts for ADS Design Kits to tailor yourkit for your specific application. A copy of all files developed in the tutorial is provided withADS for your convenience.

Design Kits versus Component Libraries Before you start building your design kit, make sure that a design kit is really what youneed. A design kit is a complex form of a component library. ADS offers various ways tocreate component libraries of reusable parts.

You can view a DesignGuide as a component library, although the purpose is different. ADesignGuide is a complete study of an application topic (for example, amplifiers, mixers,and oscillators), in the form of typical simulation schematics, data displays, and detailedreference designs.Following table lists the criteria that you can use to decide what type of component libraryyou should create.

Criteria Options

Design engineers uses technology (orprocess) internally or externally.

A design kit is required for external distribution.For internal use, a component library or DesignGuide issufficient.

Simulation methods (netlist, subcircuit, user-defined, data).

If user-defined models, data files or model cards, orsubcircuit models in a netlist files are used, a design kit isrecommended.If the library consists strictly of schematic subcircuits, acomponent library or DesignGuide is sufficient.

Whether component library include customApplication Extension Language ( AEL)code. AEL code is used in ADS to add parameter callbacks, layout menus and custom menus.

Once you decide to write custom code, it is no longer asimple component library. A design kit is better suited tohandle custom AEL code.

Simulation templates Both Design Kits and DesignGuides includes simulationtemplates. However, the emphasis on a design kit istypically related more to the models. If providing simulationtemplates is your main objective, ADS DesignGuides arerecommended as a better method.

Size of your company or the staffingmodel of the design department.

For a large company with various CAD tools and processesto support, and a full time CAD manager supporting variousdesigners, design kits are recommended. These areinstalled in a controlled system location that is accessible toall.For medium or small companies with no full time CADmanager, who just need to share subcircuits amongdesigners, a simple component library or DesignGuide issufficient.

For more information on ADS DesignGuides, refer to the Applications menu in the ADSdocumentation set.

For more information on custom component libraries, refer to Customization andConfiguration.

Supported Design Flows ADS is a flexible tool that can be used on its own or in conjunction with other CAE tools ina variety of design flows. Following are the supported design flows:


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Front to Back: Enables you to enter a design in a ADS schematic editor and uses theADS simulator for analysis. You can create the layout automatically by generating itfrom the schematic or manually. Export tools are provided to transfer the layout tothird party manufacturing tools.Front End: Enables you to enter a design in a ADS schematic editor and uses the ADSsimulator for analysis. The design is then re-entered in a separate layout tool. Tovalidate the integrity of the layout, the ADS Netlist Exporter is used to create anetlist for layout vs. schematic comparison. For more information on Front EndDesign Flow, refer to Netlist Exporter.RFIC Dynamic Link Flow: Enables you to enter a design in Cadence VirtuosoSchematic Capture. The design is then dynamically linked via inter-processcommunication (IPC) for simulation in ADS.

The GoldenGate simulator provides a tightly integrated EDA solution that enablesRF/mixed-signal IC designers to simulate their designs directly in the Cadenceenvironment using the GoldenGate RF simulator. This enables the RF/MS IC customer totake advantage of complementary features provided by both Agilent Technologies andCadence Design Systems. For more information on GoldenGate, refer to the GoldenGatedocumentation set at:

http://www.agilent.com/find/eesof-docs/

This documentation is generally focused on the ADS Front to Back and Front End designflows. For more information on the RFIC Dynamic Link flows, refer to Design KitDevelopment for RFIC Dynamic Link.

Supporting Multiple ADS Versions Design kits developed on ADS 2011 are not supported on prior releases of ADS. The entirearchitecture of the design kit has been changed. For more information refer Basic Parts ofan ADS Design Kit

Support for Additional Capability If you are creating a design kit that needs some capability that is not included in thisdocument or is not supported by Advanced Design System, the ADS Design Kit team atthe factory would like to understand the situation. There might be a solution that has notyet been documented or we may choose to add it based on a demonstrated need andmutual, widespread benefit.

For more information, contact your Agilent Technologies sales representative or technicalsupport with a request to submit a suggestion to the ADS Design Kit team at the factory.




9

ADS Design Kit StandardThe information in this section provides a summary of the ADS Design Kit Standard aswell as how to update design kits that were developed before the standard was released.

Design Kit Standard SummaryThis section describes general information related to the design kit standard for AdvancedDesign System.

Directory Structure and Content

A design kit directory should conform to the structure shown in ADS Design Kit StandardDirectory Structure.

ADS Design Kit Standard Directory Structure


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NoteThe name design_kit_name as the top level directory name is a generic name supplied for this illustration.This name should be replaced by the actual name of your design kit.

<adsptolemy>

OptionalThe <design_kit_name>/adsptolemy directory is not currently used by standard design kitsoftware, however, it may be used by specific or custom design kit software.

<design_kit_name>

RequiredThis directory should have the same name as the design kit. The name must be uniquewithin the ADS system and it cannot contain any spaces. The design kit name shouldcontain the name of the company or foundry, and the name and/or version of the process.

<design_kit_name>/bin/

OptionalIndividual files do not reside in this directoryThis directory consists of one sub-directory for each currently supported platform of ADS.For the 2011 release, the subdirectories should be: win32_VS2008, win32_64_VS2008,sun_sparc_64_SS12, linux_x86_GCC442 and linux_x86_64_GCC442. Each sub-directorycontains a platform-specific version of a custom simulator executable. If an executableexists for one platform, it should exist for all current platforms.

<design_kit_name>/circuit/

RequiredIndividual files do not reside in this directory

<design_kit_name>/circuit/ael/

RequiredThe ael directory contains design kit component definitions (.ael and .atf files).

<design_kit_name>/circuit/artwork/

OptionalADS layout macro (.ael) files belong in the artwork directory. All layout macro files mustbe loaded by the boot.ael file in the de/ael directory.

<design_kit_name>/circuit/bitmaps/

_Required if design kit components will be available from a component palette. Bitmapsshould be created as 32x32 pixels and 16 color bitmaps.

<design_kit_name>/circuit/config/

OptionalThe config directory contains an ADSlibconfig file with #uselib statements for encoded


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model files.

<design_kit_name>/circuit/data/

OptionalAll data files (e.g. .ds, .mdf, .s2p, .cti) should be placed in the data directory.

<design_kit_name>/circuit/models/

OptionalADS netlist files (\.net) and other model files (\.scs etc) should be placed in this directory.

<design_kit_name>/circuit/records/

Required if design kit components will be available from the Library BrowserThe records directory contains the design kit's library-related files. Any .ctl, and .rec filesbelong here. There can be only one .ctl file. Every .rec file that exists should be referencedin the .ctl file.

<design_kit_name>/circuit/templates/

OptionalData display templates (.ddt) reside here.

<design_kit_name>/circuit/templates/library

OptionalSchematic templates reside here in the form of cells and views.

<design_kit_name>/de/

Individual files do not reside in this directory

<design_kit_name>/de/ael/

Required if design kit components will be available from a component paletteThe design kit's boot.ael file should be placed here. The boot.ael file is used to load palettefiles, as well as every component in the circuit/ael directory if dynamic component loadingis not used. The file is also used to load other AEL files or define global variables, globalfunctions, or other custom AEL code specific to the design kit.

Palette files (.ael) should be placed in the de/ael directory. If using only one palette file,the recommended name is palette.ael. Every palette file should be loaded by boot.ael.

<design_kit_name>/de/defaults/

_Required if any design kit contains a *.via file to achieve the auto via insertion feature.


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<design_kit_name>/doc/

RequiredA design kit's documentation resides in the /doc directory.

An about.txt information file is also required and belongs in this directory. This file shouldcontain the design kit's name, version, data, description, creation date, revision history,support and contact information, process and component information, and informationabout whether the models were translated from another library. Other information can beplaced in this file as desired.

Additional documentation including any user documentation(in the form of html files) andhelp server index (hs*_index) files can be added to the doc directory.

<design_kit_name>/drc/


<design_kit_name>/drc/rules/

OptionalAny rules files (.ael) for the Design Rule Checker should be placed in the drc/rulesdirectory.

<design_kit_name>/examples/

RequiredAn archived ADS sample workspace that was created with the design kit belongs in the/examples directory.

<design_kit_name>/expressions/


<design_kit_name>/expressions/ael/

OptionalExpressions (.ael files) and the expressions_init.ael file should be placed in this directory.The dk_defined_fun.ael file which contains AEL expressions that can be copied into aschematic or data display for processing before or after simulation also goes in thisdirectory.

<design_kit_name>/netlist_exp/

OptionalFiles for the Netlist Exporter can be placed in this directory.

<design_kit_name>/netlist_exp/ael/

OptionalLayout versus schematic information belongs in the netlist_exp/ael directory.


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<design_kit_name>/netlist_exp/components/

OptionalComponents for LVS are placed here.

<design_kit_name>/netlist_exp/config/

OptionalConfiguration information belongs in the netlist_exp/config directory.

<design_kit_name>/scripts/

OptionalIf the design kit uses any scripts (e.g. .ksh, .pl, .bat), they should be placed here.

<design_kit_name>/utilities/

OptionalAny auxiliary code can be put in the utilities directory.

<design_kit_name>/verification/

OptionalThis directory contains files that are used fo verification of the design kit.

<design_kit_name>/veriloga/

OptionalThis directory contains the verilog-A model files required in the design kit.

Design Kit Completeness

The design kit must include at least one component definition file.

The kit must include schematic symbols, unless built-in ones are used instead.

There must exist a .defs file to add the kit to a workspace

There must be information for the circuit simulator in the form of a model file, data file, ora schematic or netlisted sub-circuit. To supply simulator information, use information fromone of the following directories:

circuit/models and netlist fragmentscircuit/data and MDIF files, etc.bin/$SIMARCH and .dll, .sl, and .so filessub-circuits in the form of <design_kit_lib>/schematic cell views

Components

Now design kit components can have same name as in other PDK or of ADS system. The


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name cannot be an ADS reserved word. Component names may only use legal charactersfor ADS names (alphanumeric +-=^`@#&), although it is strongly recommended thatonly alphanumeric and underscore characters are used. In addition, design kit componentnames should be prefixed with an identifier that links them to the design kit; this identifiershould be in the form:

<design kit name>_<design kit version>

Each component must have a symbol view.

Each component must be referenced by a palette, and/or library browser. The LibraryView is an alternative to this.

If a component's parameters require callbacks, there can be one callback for eachcomponent parameter or a single callback for all of the component's parameters. Acallback for a component definition, form definition, or formset definitions belongs in oneof two places:

A separate AEL file that will be loaded (i.e. available) at runtime. Place a callback in aseparate file if it is used by more than one definition.The same file as the definition that references it. Place a callback in the same file if itis used by only one definition.

Symbols

A symbol is required for every design kit component. Each component of the design kitmust have schematic view in its cell.

Design kit symbols should be more meaningful than the simple ones that are created bythe symbol generator. Typical ADS symbols are 1 inch wide from the left pin to the rightpin. Pin 1 is usually the uppermost left pin. Pin 1 is also usually defined as thecomponent's origin.

Palettes

Each component palette title should contain the name of the design kit and whateverother information is appropriate. Spaces are allowed in palette titles.

A component palette requires an AEL function, either de_define_palette_group(), toconnect each bitmap to its component and to load the palette definition into the system.

Any custom process or include component that is required by other components in thedesign kit should be placed at the top of the design kit palette.

The design kit's boot.ael file must load each file containing palette definitions.

Bitmaps

Bitmaps are only required for a component if it is made available through a palette.

A component palette bitmap must have .bmp files of 32x32 size and 16 colors.

Each design kit bitmap should be referenced in a design kit palette. A bitmap createdusing the Bitmap Editor of the DesignGuide Developer Studio can be used on bothWindows and Linux platform.


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Libraries

Design kit library and sub-library names in library browser need not to match the designkit library name as defined in eesof_lib.cfg.

By default ADS2011 displays all cells in the available libraries, in the library browser .Thisway all the component cells are displayed in library browser whether the components areadded or not using the rec/ctl files.

To customize design kit components available through the Library Browser, create acontrol file (.ctl) and record files (.rec) in the circuit/records directory.

Models

All variables and components in a model file must be unique within the ADS system.

When creating a schematic sub-circuit model, the following need to be added:

A new item definition (created automatically)The new component to the library files (if relevant)The new component to the component palette (if relevant)New bitmaps (if using component palettes)

Use the ITEM_UNIQUE attribute code when defining a netlist include component.

The netlist file name can be hard-coded into a custom component. The name of anincluded file, as listed on a process or include component, cannot be a variable reference.

Data Files and File References

For the simulator to find an externally referenced file, a design kit needs a customNetlistInclude component which will automatically specify the file name.

If the design kit contains schematics with included components (e.g. SnP, S2P, MDIF,ADS_FET, DataAccessComponent), the pointer to these external data files should haveany full path removed.

Names of data files must be unique in order to ensure that the simulator finds only onefile with the given name. It is a good idea to prefix the name with the company andprocess names.

Custom AEL

Due to all Libraries having a unique name space, custom functions and global variablesinside the libraries must have unique names. The recommended way for ensuringuniqueness is to prefix function and global variable names with the company or foundryname and/or process.

Updating Non-Standard Design KitsMany design kits in use with ADS today were created before the standard ADS2011 design


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kit structure was developed. This section describes the process for standardizing an ADSdesign kit that does not currently meet the standard, please refer to the ADS 2011 PDKUpgrade.

Design Kit Distribution

After you have modified your design kit to conform to the standard structure, and haveassigned names which include a unique identifier to all parts of the design kit, reviewCompleting the Design Kit to understand the recommended procedures for packaging,distribution and support of your design kit. Distributing your design kit as a simple .zip fileis recommended. This will ensure that it works with the ADS Design Kit installation code.Complex installation scripts are not recommended as they have caused problems in thepast which can easily be avoided.

Kits that do not conform to the Standard

Finally, if you have found that some parts of your design kit just do not conform to thestandard structure, please contact the Agilent EEsof-EDA Design Kit Team. The team canreview your needs and recommend the best way to solve your problem. The standarddesign kit structure may need to be extended to cover your needs.


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Understanding the ADS Design Kit FileStructureThis section describes the details of the ADS design kit file structure. To learn how to builda design kit, refer to ADS Design Kit Tutorial. The tutorial describes the procedure tocreate the basic files and test the design kit as it evolves. A copy of the sample kit isprovided with the ADS design kit infrastructure software. Refer to Basic Parts of an ADSDesign Kit and Additional Parts for ADS Design Kits to understand and customize thedesign kit.

Contents

Overview of the File StructurePotential Directories in an ADS Design KitUnderstanding the Directory Contents

Overview of the File Structure An ADS design kit is a group of files related to a set of ADS components, which is self-contained for ease of transfer. The files in a design kit reside in specific sub directories,under a directory that bears the name of the design kit itself. For distribution, the files arepackaged in an archive file (.zip) format.

Various directories are required for all design kits, no matter what technology is servedand various directories are required depending on the technology or configuration of thedesign kit. Additionally, there are other directories, which are optional and provideadditional functionality within the design kit.

This section includes an overview of all directories and files, including help documents todecide, which files and directories are required for your design kit. Basic Parts of an ADSDesign Kit provides detail information about the required directories and files andAdditional Parts for ADS Design Kits provides detail information about various optionaldirectories and files. ADS Design Kit File Structure for Component Palette and SimulationData in Model Files and ADS Design Kit File Structure for Library Browser Access andSimulation Data in Data Files in this section illustrate the structure of two simple designkits. Comprehensive Listing of Potential Directories in an ADS Design Kit is acomprehensive structure of all possible design kits directories defined at this time andDesign Kit File Structure lists the types of files found in each directory.

ADS is a system with capabilities for extensive customization. Design kits need to co-existwith each other and with all the tools in the system, so they must conform to ADSstandards. Agilent Technologies needs to be kept aware of the extensions that are madefor individual design kits, those that are developed by Agilent Technologies, as well asthose that are not, so that as technology advances are made, this documentation and theinfrastructure software can be extended to cover new areas.

The following table lists the directories and files required for all design kits:

circuit/ael Component definition

<PDK's main library> Component Cells and Views, eesof_lib.cfg file

doc about.txt Information file

lib.defs file Library Definition File

Additionally, directories described below are required to complete a minimal kit.

In ADS, components are selected from a palette on the schematic page, the librarybrowser window, and the Library View tab on the ADS Main Window. The palette includesbitmaps so a component can be selected quickly. The library browser presents moreinformation to the user and includes the ability to search for a component based on itscharacteristics. A component in a design kit can be presented in the palette or in thelibrary browser or both. Additionally, a design kit may consist of some components that


18

are only in the palette and some that are only in the library browser.

The following table lists the directories and files available from various components:

Components Available From Directories/Files Description

Component palette circuit/bitmaps Bitmap files

de/ael Boot files to enablepalette

Library browser circuit/ records Library browser files

Verilog-A files veriloga Verilog-A files

A design kit contains information needed by the simulator to perform calculations. Thisinformation may be supplied as model cards or subcircuit models in a netlist fragment.RFIC foundry kits often include SPICE model files translated from another simulator.Completion of a design kit containing these translated model files will include a verificationprocess that involves creating circuits in both simulators and comparing the data.

Additional topics related to inclusion of simulation data are discussed in Adding SimulationData to a Design Kit. For example, if the model used by the design kit is a user-compiledmodel, you will need to supply the custom simulator executable in the bin directory of thedesign kit. Additionally, schematic subcircuits may be the form that models are deliveredin. A final method of including simulation data is to include the raw simulation data in theform of an mdif, s2p or citi file. For more information on the mdif, s2p or citi file types,refer to Working with Data Files.

To supply simulation data, the following files need to be provided in the specifieddirectory:

Type of Simulation Data Directory Files

If simulation data is in the form of modelcards or subcircuit models.

circuit/models netlist fragments

If simulation data is in raw data form. circuit/data mdif, etc.

If a user-compiled model is included as adynamically linked library (.dll) or sharedlibrary (.sl or .so).

bin/$SIMARCH$COMPILER_VER .dll (win32_VS2008 andwin32_64_VS2008).so (sun64_sparc_SS12).so (linux_x86_GCC442 andlinux_x86_64_GCC442)deviceidx.db

If simulation data is in verilog-A form. veriloga .va files

NoteTo see the value for $SIMARCH and $COMPILER_VER, choose Tools > Configuration Explorer from theADS Main window. Locate SIMARCH and COMPILER_VER in the ADS Configuration Explorer window'sStatus pane (you may need to scroll to locate it). Example values for $SIMARCH are: win32, win32_64 ,sun64_sparc, linux_x86,linux_x86_64 and for $COMPILER_VER are: _VS2008, _SS12, _GCC442.

ADS Design Kit File Structure for Component Palette and Simulation Data in Model Filesshows the directory structure of a design kit that provides a component palette and modeldata in the form of model cards or subcircuit models in a netlist file. This is a typicalsimple RFIC design kit. Additionally, it could include a circuit/records directory to enablethe library browser and veriloga directory (under design_kit_name directory to keep theVerilog-A files.)

ADS Design Kit File Structure for Component Palette and Simulation Data in Model Files


19

NoteThe name design_kit_name as the top level directory name is an example for illustration. This nameshould be replaced by the actual name of your design kit. Similarly, the name design_kit_lib_name anddesign_kit_tech_lib_name should be replaced by the name of PDK's Main Library and Technology Library.Generally the PDK's main library is named after the PDK, and the PDK's technology Library is named with_tech appended to the PDK's name.

ADS Design Kit File Structure for Library Browser Access and Simulation Data in Data Filesshows the directory structure of a design kit that provides access to components via thelibrary browser and includes simulation data in the form of a data file.

ADS Design Kit File Structure for Library Browser Access and Simulation Data in Data Files

Potential Directories in an ADS Design KitThis section lists the Potential Directories in an ADS Design Kit, the comprehensivestructure of all possible design kit directories defined. If your design kit needs directoriesthat are not listed in the complete structure shown here, it is recommended that you workwith the ADS Design Kit Infrastructure team at Agilent EEsof EDA.

Comprehensive Listing of Potential Directories in an ADS Design Kit


20

Design Kit File Structure lists all of the possible subdirectories, as shown inComprehensive Listing of Potential Directories in an ADS Design Kit, as well as the typesof files that will reside in those directories. Note that the last column in Design Kit FileStructure denotes whether the files are autoloaded (AL) or not.

Design Kit File Structure

Directories Subdirectories Files Description AL

bin/ $SIMARCH$COMPILER_VER/ .dll (win32_VS2008,win32_64_VS2008),.so(sun_sparc_64_SS12),.so (linux_x86_GCC442,linux_x86_64_GCC442),deviceidx.db†

User-compiled model indynamically linked libraryor shared library.

Y

circuit/ ael/ <prefix>_<item>.ael Component Definition -create_item()

N*

artwork/ *.ael macro files for ADS layout N

bitmaps/ <prefix>_<item>.bmp Component Bitmap N

config/† ADSlibconfig #uselib lookup table Y

data/ *.ds simulations/measurements N

*.mdf MDIF files generated byICCAP

Y


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*.s2p Touchstone S-parameterfiles

Y

*.cti CITIFILE files Y

models/ *.net spice/spectre translatornetlists

N

*.library encoded libraries Y

records/ <prefix>_<lib>.ctl control file Y

<prefix>_<lib>.rec record file Y

templates/† *.ddt dds templates Y

templates/library/schematic/ master.tag, sch.oa schematic template library Y

de/ ael/ boot.ael this file gets loaded firstinto ADS.

N*

palette.ael Generic file to definepalette.

N

defaults/ *.via this file is used to insertvias while adding tracesautomatically

N*

design_kit_lib_name/ <cell_name>/symbol/ master.tag, symbol.oa ADS internal files. Not tobe edited by user.

Y

<cell_name>/schematic/ master.tag, sch.oa ADS internal files. Not tobe edited by user.

Y

<cell_name>/layout/ master.tag, layout.oa ADS internal files. Not tobe edited by user.

Y

<cell_name>/ itemdef.ael Component definition filerequired for demandloading.

Y

.oalib ADS internal files. Not tobe edited by user.

Y

eesof_lib.cfg Contains environmentvariables

Y

layout.prf Layout preferences Y

schematic.prf Schematic preferences Y

tech.db Technology database file Y

design_kit_tech_lib_name/ .oalib ADS internal files. Not tobe edited by user.

Y

display.tech Contains display order forlayers.

Y

LayerMap.map Contains layer mappinginformation.

Y

library.tech Technology for library. Y

materials.matdb Contains properties ofmaterial.

Y

sample.subst Contains substrateinformation.

Y

tech.db Technology database file. Y

doc/ readme.txt installation info N

about.txt design kit info N

index† lookup file N

<prefix>_<lib>.html† component info N

drc/ rules/† *.ael DRC rules N

examples/ *.7zap archived ADS workspace N

expressions/ ael/† dk_defined_fun.ael Design Kit expressions aelfile

Y

*.ael expressions N

adsptolemy/† adsptolemy dir N

lvs/† ael/ layout vs. schematic N

components/ N

scripts/† *.pl scripts N

*.ksh, *.bat N


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utilities/† *.ael any auxiliary code N

verification/† verification info N

veriloga/† *.va Verilog-A files Y

AL = Files Autoloaded (Y/N)?* Note that <prefix>_<item>.ael is loaded only if specified in boot.ael or if stored asitemdef.ael in the component's cell. Also, boot.ael is loaded only when specified ineesof_lib.cfg.† Optional part. For more information, refer to Additional Parts for ADS Design Kits.

Understanding the Directory ContentsThis section briefly describes the files in each sub-directory of the complete ADS design kitstructure. For a full description of each section, refer to the expanded discussion in BasicParts of an ADS Design Kit or Additional Parts for ADS Design Kits.

The naming convention for some of the items in these tables is <prefix>_<item>.ael or<prefix>_<lib>.ael. The <prefix> name is a unique identifier that should include thefoundry name and the process name. The <item> name refers to a component name andthe <lib> name refers to a library name. For more information on naming conventions,refer to Component Name. Note that all names within angled brackets (< >) are placeholders and will be replaced by a real name in your design kit.

The <design_kit_name> Directory

The <design_kit_name> directory is the ADS Design Kit directory name. For moreinformation on naming directories, refer to Design Kit Name.

The bin/$SIMARCH$COMPILER_VER/ Directory

The bin/$SIMARCH/$COMPILER_VER directory contains platform dependentsubdirectories, where $SIMARCH = sun64_sparc, linux_x86, linux_x86_64, win32 orwin32_64 and $COMPILER_VER is _VS2008, _SS12, _GCC442 The directories containdynamically linked libraries or shared libraries (*.dll/*.so) and the device index file(deviceidx.db). The value of $SIMARCH can be determined by running the command:$HPEESOF_DIR/bin/hpeesofarch

For more information, refer to User Compiled Models.

The 'circuit' Directory

For each design kit, there are quite a few possible subdirectories in circuit that contain thefiles specific to a particular process. Details on the files in these subdirectories, areprovided in The circuit Subdirectories.

The circuit Subdirectories


23

Subdirectory Description

ael Component definition filesThe files in this directory are AEL files containing 'create_item()' statements, which are theitem definitions for each component. Each component may be in a separate file or they maybe combined into one file. The file may also contain global variable declarations, formdefinitions, or callback functions needed for each component.Files: <prefix>_<item>.ael

artwork Macro files for Component ArtworkThis directory is provided for AEL artwork macro files for ADS layout.Files: *.ael

bitmaps Component bitmap filesAll files can have the .bmp extension, which cannot be given when the file is referenced in aelcalls to dk_define_palette_group().Files: <prefix>_<item>.bmp

config† Component configuration files

The ADSlibconfig is a lookup file for locating a special type of ADS library. It is referencedby the simulator when a #uselib statement is encountered. A template version ofADSlibconfig can be placed in this directory when creating a design kit with encodedmodels or circuits (see "The RF IP Encoder and Design Kits").The ADSlibconfig will be read by ADS from the following location. The design kit's includedADSlibconfig contents will be merged with the$HOME/hpeesof/design_kit/circuit/config/ADSlibconfig file automatically when the userloads the design kit into ADS.The variable DKIT_ADSLIBCONFIG_PATH will be set in the user's$HOME/hpeesof/config/hpeesofsim.cfg file to $HOME/hpeesof/design_kit/circuit/configafter the design kit is loaded by the user and the$HOME/hpeesof/design_kit/circuit/config/ADSlibconfig file is automatically updated withthe design kit's ADSlibconfig file contents upon loading. |

data Component data filesThese files are an optional way to define simulation data. The typical way is to provide model files.This directory is provided to store ADS simulator dataset files (*.ds), MDIF files (*.mdf), CITIFILES(*.cti) and Touchstone files (*.s2p).Files: *.ds, *.mdf, *.cti, or *.s2p

models Component model filesThis is the typical way to provide model data to the simulator. It is a file or set of files containingprocess variables and model cards or subcircuit model descriptions.Encoded libraries generated by the RF IP Encoder are also stored in this location. For moreinformation, refer to "The RF IP Encoder and Design Kits".Files: *.net, *.scs, *.library

records Component records files

There are two types of files in the records directory. The .ctl file lists the names of thecomponent libraries in an XML file format. It also includes the name of a .rec file to readfor each component library. The .rec file is also in XML format and it lists specificinformation about each component in the component library. These two files are used tobuild the library and component lists in the Library Browser. Only one .ctl file should beincluded and it can refer to multiple .rec files.The records directory is added to the LIB_BROWSER_CTL search path when a design kit isloaded. This variable is referenced by DESIGN_KIT_BROWSER_PATH inhpeesofbrowser.cfg.Files: <prefix><lib>.ctl; <prefix><lib>.rec |

templates† Component template filesThis directory can include templates for simulation or for data display. The path variableTEMPLATES_DIRECTORY is extended to include this directory when a design kit is loaded. Thispath variable is referenced by DESIGN_KIT_TEMPLATE_BROWSER_PATH in hpeesofbrowser.cfg.Files: <prefix>_<item>.ddt or Cells for Template designs

† Optional part. For more information, refer to Additional Parts for ADS Design Kits.


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The 'de' Directory

Subdirectory Description

ael AEL filesThe <design_kit_name>/de/ael directory is to be used for AEL files that apply to the design kitin general, as opposed to the component specific files in circuit/ael. Some examples of files inthis directory are boot.ael and palette.ael. These files contain commands used by the systemto load the design kit and configure the component palette. More information about these filesis included in Basic Parts of an ADS Design Kit. Sample versions of these files are included inthe ADS Design Kit Tutorial.Other AEL files may be put in this directory if the design kit requires custom AEL code. The utilities directory is also available for auxiliary AEL functions. ADS must be instructed to loadthese AEL files from boot.ael, as shown in Creating the boot.ael File, and boot.ael must bespecified in the template eesof_lib.cfg file.Files: <prefix>_<item>.ael

defaults *.via filesUsed to insert the vias automatically while drawing the trace

The 'PDK Main Library'

Directory Description

<design_kit_lib_name> The <design_kit_name>/<design_kit_lib_name> directory contains cells, views andalso item definitions of components (if required to be demand loaded). This directoryalso contain some other files. For details see below:

<cell_name>/symbol/, <cell_name>/schematic/ and <cell_name>/layout/directories contain the files generated while creating a new cell.<cell_name>/itemdef.ael contain the create_item()of the component requiredfor demand loading..oalib - ADS internal file. Not to be edited by user.eesof_lib.cfg - Contains the configuration variables.layout.prf - Contains layout preferences.schematic.prf - Contains schematic preferences.tech.db - Technology database file. Not to be edited by user.

The 'PDK Technology Library'

Directory Description

<design_kit_tech_lib_name> The <design_kit_name>/<design_kit_tech_lib_name> directory contains thefollowing technology files:

.oalib - ADS internal file. Not to be edited by user.display.tech - Contains display order of layers.LayerMap.map - Contains layer mapping information.library.tech - Contains technology for process.materials.matdb - Contains properties of material.sample.subst - Contains substrate information.tech.db - Technology database file. Not to be edited by user.

The 'doc' Directory

The <design_kit_name>/doc directory contains all of the user documentation associatedwith the design kit. HTML files may also be included and merged into ADS documentation.For more information on the about.txt file, refer to The about.txt File. For moreinformation on adding HTML documentation to the system, refer to Creating Design KitDocumentation.


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The 'drc' Directory

The <design_kit_name>/drc/rules directory contains ael files which define drc rules forthe Design Rule Checker (DRC) tool in ADS. For more information on DRC in ADS, refer toADS Desktop Design Rule Checker.

The 'examples' Directory

Each design kit must include at least one sample design. This can be used by yourcustomer or by Agilent Technologies support engineers to ensure that the design kit isinstalled correctly before they start a new design. You can use this as a method todemonstrate special features of the design kit such as a process component that must beplaced in any design using the design kit. It is especially helpful if a design kit includes acustom version of the simulator to verify that the correct simulator is being used. Formore information, refer to Adding Simulation Data to a Design Kit. The workspace orworkspaces containing the sample design(s) are archived and then stored in the<design_kit_name>/examples directory.

The 'expressions' Directory

The <design_kit_name>/expressions/ael directory contains the file dk_defined_fun.aelwhich contains AEL expressions that can be copied into a schematic or data display forprocessing before or after simulation. For more information, refer to Expressions.

The 'adsptolemy' Directory

The <design_kit_name>/adsptolemy directory is not currently used by standard design kitsoftware, however, it may be used by specific or custom design kit software.

The 'netlist_exp' Directory

The <design_kit_name>/netlist_exp directory contains all files needed by the ADS NetlistExporter. By providing rules files for each component in a design kit, the Netlist Exportercan output netlists in the proper form for many LVS tools. For more information onincorporating the appropriate LVS information into a design kit, refer to ConfiguringDesign Kit Components for use with ADS Netlist Exporter.

The 'scripts' Directory

The <design_kit_name>/scripts directory contains any custom shell or perl scripts thatyou have developed for use with your design kit. For more information on incorporatingthese scripts into your design kit, refer to Additional Parts for ADS Design Kits.

The 'utilities' Directory

The <design_kit_name>/utilities directory contains any custom AEL scripts that areauxiliary in nature. Other AEL scripts that are used directly with the design kit are storedin de/ael or circuit/ael as described in The 'de' Directory and The 'circuit' Directory. Formore information on incorporating these scripts into your design kit, refer to Additional


26

Parts for ADS Design Kits.

The 'verification' Directory

The <design_kit_name>/verification directory contains files that are used by the ADSDesign Kit Model Verification scripts (if any) to create a verification suite. These files areappropriate to ship along with the design kit. For more information on the verification tool,refer to Verifying a Design Kit.

The 'veriloga' Directory

The <design_kit_name>/veriloga directory contains the Verilog-A files provided by thefoundry.


27

Basic Parts of an ADS Design Kit

This section details the basic parts of an ADS design kit. ADS Design Kit Tutorial guidedyou step by step through building a design kit with each of the parts described in thissection. As described in Understanding the ADS Design Kit File Structure, the basic partsof a design kit are those that define the components, the simulation data, as well as asimple file to identify the design kit to ADS, and the AEL files required to load the designkit.

Design Kit NameEach design kit must have a unique name and the name cannot include spaces. Since anADS user may have multiple design kits loaded, from different sources, the design kitname should be informative. It should contain the name of the company or foundry aswell as the name and/or version of the process.

The name of the design kit is only used in a couple of places. It is the name of thedirectory that all the other subdirectories are stored under, as illustrated in Understandingthe Directory Contents . The design kit name is entered into the eesof_lib.cfg file. Fromthe eesof_lib.cfg file, it becomes visible in the dialogs for end users. The Design Kit'sname should ideally be the default name of your PDK's main library. These dialogs areused to load and set up the design kits that are accessible in ADS. For more informationon the user interface, refer to Design Kit Installation and Setup .

A design kit name may also be shown on the component palette, if a palette is provided,but this is not an automatic correlation. The palette title is set in a different location thanthe design kit name. A design kit may contain multiple palettes. Each palette shouldcontain the name of the design kit in addition to whatever other information isappropriate. Palette titles can have spaces in them. The palette is the location where theuser will most often see the name of the design kit because the palette is visible at alltimes in the schematic window. The list of default system palettes, plus the examplepalette from the design kit tutorial, are shown in Design Kit Tutorial Palette Name.

Design Kit Tutorial Palette Name

Library Definition FileTo include a library or a PDK to a workspace, the user needs to point to the library


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definition file of the library. This is the file with the .defs extension. A Design kit cancontain two library definition files - lib.defs and for_editing_pdk.defs.

lib.defs - If you want to add a library in read-only mode, you need to select thelib.defs file while adding your PDK to the workspace. The PDK added can't be editedby the user, so it is recommended that if you don't want the user of your design kitto make changes to the design kit, provide this file with your design kit. To include alibrary in your workspace through lib.defs, add the following lines to your lib.defs file-

DEFINE <Library Name> <Relative path to Library>ASSIGN <Library Name> libMode readOnly

e.g.DEFINE SampleKit ./SampleKitASSIGN SampleKit libMode readOnlyDEFINE SampleKit_tech ./SampleKit_techASSIGN SampleKit_tech libMode readOnly

For kits with their own Technology, both the kit's Main library and Technology library needto be added as shown in the above example.

for_editing_pdk.defs - If you would like to add your kit in editable mode, you need toselect the for_editing_pdk.defs file while adding your PDK to the workspace. The PDKadded can be modified by the user. So provide this file only if the user should havethe ability to edit the kit. Generally foundries should remove this file before providingthe kit to their customers. To include a library in your workspace throughfor_editing_pdk.defs, add the following lines to your for_editing_pdk.defs file -

DEFINE <Library Name> <Relative path to Library>ASSIGN <Library Name> libMode shared

e.g.DEFINE SampleKit ./SampleKitASSIGN SampleKit libMode sharedDEFINE SampleKit_tech ./SampleKit_techASSIGN SampleKit_tech libMode shared

For kits with their own Technology, both the kit's Main library and Technology library needto be added as shown in the above example.

Components in a Design KitDefining a component in ADS requires entries in a number of files. Information must beprovided to control the behavior of the component when used in a schematic or layout orwhen processed by the simulator. The component definition AEL file contains much of thisinformation.

Components can be presented to the user through component palette or in theComponent Library browser or both. Symbols are required for schematic view in both ofthese methods.From ADS2011 on-wards, when a kit is added to a workspace, the components in that kitare automatically accessible to the user from the Library View in the ADS main windowand component library browser.

Bitmaps are only required for the component palette. Additionally, you can set your designkit components up to be loaded on demand. For kits with large numbers of components,this reduces the impact on ADS startup time.

The items that must be defined for each component in a design kit are explained in thefollowing sections:


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Component Cell and View

Component Name

Item Definition

Schematic Symbol

Component Palette vs. Component Library Browser

Component Cell and View

From ADS2011 onwards, Design Kits behave just like Libraries. Each Design Kit has 2Libraries - the Main library and the Technology library.The name of the Main library should ideally be the same as the name of the Design Kitmentioned in eesof_lib.cfg.This library contains cells for each component. The cells in turn contain different types ofviews - Schematic, Layout and Symbol; depending on the type of the component.Components can have more than 1 view of the same type.

A cell may also contain a file called itemdef.ael, if it is required that this component beDemand Loaded as explained in Demand Loaded Components.

Component Name

Component names are a unique identifier of each component loaded in ADS at any giventime. The name is visible in the balloon help that is displayed when you hold your cursorover a palette tile. It is also visible on the ADS schematic after you have placed thecomponent. Eventually, the component name is passed to the simulator in the netlist.

Since in ADS2011 each library has a unique namespace, components in different librariescan have the same name without having any side-effects. So if you create a componentnamed R in your PDK, it will not clash with the ADS built-in component R.

You can test a new component name by entering it in the Component History field asshown in below.

ADS Component History


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If you receive the error Could not find cell "Component1" in any open library , whereComponent1 is the name of the component that you entered in the Component History,after entering your new component name, this is an indication that the name is notcurrently being used in ADS. To ensure that your component names are completelyunique, you should prefix each component name with an identifier which links it back tothe design kit. For example, the name of an RFIC foundry component would include:

The name of the foundryThe specific foundry processThe common device type identifier

Separate the words in your component name with an underscore to make it morereadable.

Example:

<foundry>_<process>_<device type>

Another advantage of prefixing each component with a string such as the design kit nameis that sometimes a design that was built with design kit components will get sent tosomeone who does not have that particular design kit loaded. In this case, when thedesign is opened, a generic message indicating that the component was not found is allthat the user would see. Then, when they look at the schematic, there will be a skeletalsymbol with only pins and the component name. Seeing the component name will helpthem determine the library that the component came from.

NoteA component name in ADS cannot contain spaces.

Using Valid ADS Characters

The legal character set for Advanced Design System names is:

alphanumeric

_

+

-

=

^

`

@

#

&

$

Note that, other than alphanumeric and underscore characters, all other legal charactersrequire special handling in ADS. It is highly recommended that you use only alphanumeric


31

and underscore characters in any part of your design kit.

Reserved Words

There is also a list of reserved words in ADS which cannot be used for component names.For more information on reserved words in ADS, refer to ADS Reserved Words -Alphabetical List.

Item Definition

All components that exist in ADS are added by calling an AEL function calledcreate_item(). Each component can have a number of parameters, which are added to thesystem by calls to the function create_parm() inside create_item() . The combination ofthese calls is referred to as the item definition. A user interface is provided to set up someof this information, but it also usually requires some additional manual editing. Thetutorial gave an example of this process.

In addition to parameters and their default values, the item definition in ADS containsinformation about a component that is necessary for display on the schematic. There isalso information included that is needed for simulation. The following section describes thesyntax and the arguments of the create_item() function that are important for design kits.

The syntax for the create_item() command is shown here. The square brackets indicateoptional parameters, but are not entered in the actual function call.

create_item(name, desc, prefix, attrib, priority, iconName, dialogCode,

dialogData, netlistFormat, netlistData, displayFormat,

symbolName,artworkType, artworkData [, extraAttribute, cbList,

parameterN]);

An example similar to that in the tutorial is repeated here for reference. The callback andcreate_parm() information is incomplete but is sufficient for demonstration purposes. Theparameter descriptions are included in The create_item() Parameter Descriptions.

create_item("sample_fet", "FET", "M", 0,

NULL, NULL, standard_dialog, NULL,

CmpModelNetlistFmt, NULL, ComponentAnnotFmt, NULL, NULL, NULL,

ITEM_PRIMITIVE_EX, list(callback1, callback2, etc),

create_parm("parm1",...), create_parm("parm2",...));

The create_item() Parameter Descriptions


32

Argument Description

name Name of the component. It must be completely unique in the system. For design kits, it shouldinclude a company and/or process reference.

desc Description of the component. 80 character limit. This shows up in the edit component dialogas well as in the balloon help when the cursor is positioned over the component in the palette.

prefix The prefix is typically 1-3 characters but can be longer. It is used to create a unique ID whenthe component is placed in a schematic.

attrib This is a special attribute code. AEL contains a list of codes in create_item() Attribute Choices.Each code has a numerical value assigned to it. Use of these codes is explained below. A valueof 0 or NULL indicates that no special codes are set.

priority Not used from ADS2011.01 onwards. Set it to NULL .

iconName Not used for design kit components .Set it to NULL.

dialogCode This tells the system which dialog to open for editing of parameters and other componentattributes. It is usually set to standard_dialog, which is a constant value. A constant value is aspecial value that the system knows about. It is not a string. Do not put it in quotes.

dialogData Not used for design kit components - set it to "".

netlistFormat This tells the system what format to use when the component is output to a netlist. Twoconstant values are defined that should be sufficient for most design kit components. Theseare not strings so do not put them in quotes. These netlist format values are:ComponentNetlistFmt and CmpModelNetlistFmt

netlistData This is a string; Can be used in conjunction with the netlist format string.

displayFormat This tells the system how to display the component annotation on the schematic. Componentannotation consists of the component name and unique ID. For design kit components, use thevalue ComponentAnnotFmt. This is a constant known to the system, not a string. Do not putquotes around it.

symbolName Not used from ADS2011.01 onwards. Set it to NULL.

artworkType Not used from ADS2011.01 onwards. Set it to NULL .

artworkData Not used from ADS2011.01 onwards. Set it to NULL .

extraAttribute This is another attribute code. AEL contains a list of these codes in create_item() ExtraAttribute Choices. Each code has a numerical value assigned to it. Use of these codes isexplained below. A value of 0 or NULL indicates that no special codes are set.

cbList List of netlist callbacks. See Netlist Callbacks for details.

parameterN All parameters of the component, each defined by a separate call to create_parm(). These arenot presented in the AEL list() syntax like the callbacks are. Instead they are just listed oneafter the other, separated by a comma, as if they were regular arguments. See Thecreate_parm() Parameter Descriptions for details on the create_parm() function.

How to Use Attribute Codes

There are two arguments in the create_item() function that contain attribute codes. In thesyntax example above, one is called attrib and the other is called extraAttribute. Eachattribute is actually a combination of a number of individual attribute codes, addedtogether. To determine the value to set in the call to create_item(), add the numericalequivalent of all desired codes. An example is shown below with the few codes that mightbe used in design kit components.

For a more complete list of the commonly used attribute codes, use the codes and valuesfrom create_item() Attribute Choices to set the attrib argument. Use create_item() ExtraAttribute Choices to set the extraAttribute argument. These are stored in separatearguments because the size of the number that can be stored in memory is limited andwould be exceeded if the codes from both attributes were stored in one location. Do notmix values from the different tables.

Attribute Code Examples

For the attrib argument, the attribute code most applicable to design kit components isthe code called ITEM_UNIQUE. This is used for the process include component and itmeans that only one instance of this component can be placed in a schematic page.


33

From create_item() Attribute Choices, the numerical value of that code is 8. Therefore,the create_item() function call for a process include component will have the value 8 forthe attrib argument. For better documented code, you might choose to use the moredescriptive code and set the value to ITEM_UNIQUE, from the first column increate_item() Attribute Choices.

NoteThe descriptive attribute codes are actually hexadecimal codes inside the program. Because of this, morethan one item attribute can be combined with the ' | ' symbol ( OR ) when the code name is used and notthe decimal equivalent. It is beyond the scope of this document to teach hexadecimal arithmetic. Justremember that you must use the OR symbol if you are using the descriptive codes. Only add the numberstogether if you are using the decimal equivalents.

All other design kit components should not generally need any of the attributes fromcreate_item() Attribute Choices, so the value 0 or NULL or ITEM_NORMAL should be set.ITEM_NORMAL is not shown in the AEL documentation.

For the extraAttribute argument, set ITEM_PRIMITIVE_EX to indicate to the simulator thatthe component is a native component in the simulator. ITEM_CKT_MODEL_EX would beset for a user-compiled model for Analog/RF. ITEM_SP_MODEL_EX indicates a user-compiled model for DSP. Other common codes for the extraAttribute argument are givenin create_item() Extra Attribute Choices.

Parameter Definition

This section describes the syntax and arguments for the create_parm() function, which isused as an argument in the create_item() function, described above. More information isincluded in Component Definition Functions in the AEL documentation.

The syntax for the create_parm() command is shown here. The square brackets indicateoptional parameters, but are not entered in the actual function call.

create_parm(name, desc, attrib, formSet, unitCode, defaultValue [,cbList]);

An example similar to that in the tutorial is repeated here for reference. The callbackinformation is incomplete but is sufficient for demonstration purposes. The parameterdescriptions are included in The create_parm() Parameter Descriptions.

create_parm("model", "model name", 0, "sample_formset_fet1_model", UNITLESS_UNIT,

prm("model11"),

list(callback1, callback2, etc));

The create_parm() Parameter Descriptions


34

Argument Description

name Name of the parameter.

desc Description of the parameter. This text is seen by the user in the edit parameter dialog whenplacing a component or modifying its parameter values.

attrib Special attribute code. See "How to Use Attribute Codes" above. The list of commonly usedparameter attributes is given in AEL in the create_parm() section. If your Design Kit componentsdo not need a special attribute code, set the value to 0.One attribute that may be useful in design kits is PARM_NOT_EDITED. This will prevent the userfrom modifying the parameter and is typically used for dependent parameters whose values areset by callbacks.The code for PARM_NOT_ON_SCREEN_EDITABLE may be used in conjunction with formsets. Thiswill prevent the user from typing in a value that is not in the preset list, but it will also preventthe user from using the up/down arrows to scroll through the values on-screen.

formSet Forms are used as a way to present the user with a list of values. A parameter value is thenlimited to those defined in a form set. List the name of the form set here. See Forms andFormsets, or Creating New Component Definitions.

unitCode The following is the list of unit types for ADS components.STRING_UNIT = -2UNITLESS_UNIT = -1FREQUENCY_UNIT = 0RESISTANCE_UNIT = 1CONDUCTANCE_UNIT = 2INDUCTANCE_UNIT = 3CAPACITANCE_UNIT = 4LENGTH_UNIT = 5TIME_UNIT = 6ANGLE_UNIT = 7POWER_UNIT = 8VOLTAGE_UNIT = 9CURRENT_UNIT = 10DISTANCE_UNIT = 11TEMPERATURE_UNIT = 12DB_GAIN_UNIT = 13

defaultValue defaultValue is optional. If specified, it needs to be in the form of a value returned from theprm() function. The prm() function generates an acceptable default value for parameters withdifferent form sets. If a formset is not set for the parameter, use "StdForm" as in the exampleprm("StdForm", "BJTM1");.

cbList List of parameter callbacks. See Parameter Callbacks for details.

Saving the Item Definition

It is recommended that you always present the code in this order - global variables, formsand formsets, netlist and parameter callbacks, and item definition. The fileSAMPLE_NETLIST_INCLUDE.ael, which is shown in the Adding a Netlist IncludeComponent, is a good example of this format and can be used as a template fordevelopment of item definition files. You also learned in the tutorial that item definitionscan be combined in one file or be kept separate with one component per file.

Forms and Formsets

The file SAMPLE_NETLIST_INCLUDE.ael in Example Process Component with Forms andFormsets introduces an important topic not covered in the tutorial. It is the use of formsand formsets. This is a method of making user-defined lists that can be presented to theuser when they are placing a component on the schematic. The syntax for the functioncalls to create a formset and a constant form are both very simple. Look at the codesample in Example Process Component with Forms and Formsets and the syntax listedbelow. More information is available in Component Definition Functions in AEL. Othertypes of forms are available as well.

create_constant_form(name, desc, attribute, netlistFormat, displayFormat);where:

name is a string representing the form name.


35

desc is a description of the form.attribute is an integer, usually 0 for this type of form.netlistFormat is the format string to netlist the parameter value as.displayFormat is the format string to display in a schematic.

create_form_set(name, formName1, formName2, ....formNameN);where:

name is the name of the form set. This is used by the create_parm()function.formName is one or more form names, such as the "name" parameter inthe create_constant_form() function above.

Schematic Symbol

When a component is selected from the Component Palette List or the Component Librarywindow, an instance of the component is attached to the cursor and an outline of thecomponent symbol is displayed as the mouse is dragged across the screen. When themouse is clicked in the schematic window, an instance of the symbol is drawn on thescreen. As a design kit creator, you must create the symbol graphics that are displayed onthe schematic.

From ADS2011.01, components' symbols are stored as symbol views. Typical ADSsymbols are one schematic inch wide from the left most pin to the right most pin. Thetraditional location for pin 1 is on the left. If there is more than one pin on the left side ofthe symbol, the upper most pin is usually pin 1. Pin 1 is also typically defined as theorigin, which is the point where the cursor is when then symbol is dragged across theschematic page.There are several ways to create a symbol for your design kit.

Drawing a New Symbol describes one way of creating a symbol view using the ADSSymbol Generator.

Copying an Existing Symbol is another way to create and modify a symbol fromanother design kit or library.

Drawing a New Symbol

To draw a new symbol view for your design kit component:

Choose File > New > Symbol.... In the dialog box that comes up, enter the library,1.view and cell name of the component for which you want to create the symbol view.The View name should generally be named as 'symbol'.


36

Or in the ADS main window, right click on the component for which you want tocreate the symbol view and choose New Symbol

A symbol view opens up and the Symbol Generator dialog box appears.2.


37

Close the Symbol Generator dialog and draw the symbol by hand.3.

For more information on creating symbols in ADS, refer to Drawing a Custom Symboland/or ADS Schematic Symbol & Bitmap Creation.

NoteUse of the Symbol Generator is not appropriate for design kit development because the symbols that areautomatically generated by the system are just box-like symbols intended for representing a hierarchicaldesign in ADS. For design kits, you will want to create a more meaningful symbol that properly representsthe component for which it is a symbol.

Copying an Existing Symbol

To copy a symbol view from an open library for your design kit component:

In the ADS main window, right click on the symbol view you want to copy and select1.Copy or Copy View.If you selected Copy, simply right click on the component where you want to copy2.this symbol to, and select Paste.If you selected Copy View, choose the component where you want to copy this3.symbol to, in the dialog box that appears.

Detailed steps on this process are provided in the tutorial in ADS Design Kit Tutorial.

For more information on creating symbols in ADS, refer to Drawing a Custom Symboland/or ADS Schematic Symbol & Bitmap Creation.

Component Palette vs. Component Library Window

You must decide if your design kit components will be accessed from the componentpalette, the Component Library window, or both. You must also decide if your componentswill be loaded only when used (demand-loaded), to save time at ADS startup, or if theparts will be loaded into memory when the library is loaded.

For a design kit with a limited number of components, selecting a component from the


38

palette is quick because the palette is a permanent part of the schematic window andthere are pictures that enable quick identification of the components.

Finding a component on a palette is not efficient if the design kit has a large number ofcomponents. In this case, use the Component Library window. The disadvantage is thatthe Component Library is a separate window from the schematic page. A distinctadvantage is that the Component Library window has search capabilities. When definedwith control files, the Component Library window has other advantages, listed below.

For defining components in the Component Library window, the method uses ComponentLibrary window control and record files to give more functionality, including the ability togroup components in sub-libraries. From ADS2011.01 onwards, all cells in the Design Kitare displayed in the library browser. The top level is grouped by the actual library and notthe ‘category’ field in the rec/ctl files.

The benefits of using the Component Library window with the control and record files are:

It allows for a multiple-tier library presentation (library/sub-library/sub-library etc.).It allows access to additional fields in the Component Library window.It allows for selected components to appear in the Component Library window whena schematic is open, but not when a layout is open, or vice-versa.The functions mentioned above are defined in the sections below, and the ADSDesign Kit Tutorial provides specific examples of each method.

Accessing Design Kit components from the ADS main window

From ADS2011.01 onwards, there is another way to access Design Kit components. TheLibrary View tab in the ADS main window, also shows the components(along with theirdifferent views) in all open Libraries in the Workspace. So you can simply drag and dropthe Design Kit components onto the schematic or layout windows from this tab.

Component Palette

To define a component palette, use a function call to the ADS design kit infrastructurefunction dk_define_palette_group() in a file called palette.ael. This file should be saved inthe de/ael directory of your design kit directory structure.

Note that the syntax for the function call dk_define_palette_group() is exactly the sameas the function de_define_palette_group().

dk_define_palette_group(winType, dsnType, groupName, groupLabel, position,

item1name, item1label, item1bitmap name[, item2name, item2label, item2bitmap

name, ...] );

Has the same syntax as:

de_define_palette_group(winType, dsnType, groupName, groupLabel, position,

item1name, item1label, item1bitmap name[, item2name, item2label, item2bitmap

name, ...] );

The square brackets indicate that the number of items in the palette is variable. The groupof three parameters, item1name, item1label, and item1bitmap, are a set and all threehave to be defined for each component in the palette. Do not include the bracket in yourAEL code. For more information on function syntax and usage, refer to ComponentDefinition Functions in AEL.

The following values are used for this application:winType = SCHEM_WIN or LAYOUT_WIN

dsnType = "analogRF_net" or "sigproc_net"

groupName = name of palette


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groupLabel = descriptive label for palette

position = position is an integer that indicates where the new palette is added in the listof palettes:-1 -alphabetically sort the list of palettes after adding the new palette.

-2 - append the new palette at the end.

>0 - insert the new palette in the specified position in the list of palettes.

item<n>name = name of component as registered in create_item() call

item<n>label = description of component

item<n>bitmap = path to bitmap for the palette button.

NoteThe bitmap name must not include the file name extension (.bmp) or it will fail on some platforms. Alsonote that the second parameter in dsnType, used in dk_define_palette_group(), is a quoted string.

The function de_define_library_palette() can also be used for creating a palette. Note thatthis function has been newly introduced in ADS2011.01The SampleKit that ships along with ADS shows the use of this function to create apalette.

Bitmaps

The bitmap file referenced in the palette definition is a file located in the circuit/bitmaps orcircuit/bitmaps subdirectory of the design kit directory structure. The bitmap is used tomake the picture icon on the palette, to enable quick selection of a component by visualidentification. In addition to a picture, the bitmap can contain a few short words to identifythe component and the design kit to which it belongs.

There are different ways to create a bitmap. Windows programs like Paint can be used.The ADS DesignGuide Developer Studio can also be used and is recommended as it givesaccess to sample bitmaps and is designed to create bitmaps specifically for use in ADS.The DesignGuide Developer Studio is shipped with ADS and can be used without a license.

Bitmaps should be created as 32x32 pixels and saved as 16 color bitmaps. Using theDesignGuide Developer Studio, you can use the bitmap editor to save a single bitmapwhich can be used on both Windows and Unix platforms.

The .bmp extension can be used for the bitmaps. More information is included in ADSDesign Kit Tutorial.

NoteThe bitmap name as listed in the call to dk_define_palette_group() cannot contain a filename extensionsuch as .bmp. The bitmap file name can however include the full path. The presence of a file extension willcause display of the bitmaps to fail on some platforms.

Component Library Window

The way to define a library for the Component Library window is by setting up control andrecord files in the circuit/records subdirectory of your design kit as defined in the nextsection. This method provides the functionality listed in the section Component Palette vs.Component Library Window. All library control files (.ctl) in the <design_kit_name>/circuit/records directory will be loaded automatically when the library is activated. Recordfiles will be called by the control file when they are required. The control file defines thelibraries and the record files list the components in each library.

Exiting the Component Library

To exit the component library, click "X" button.


40

The Control File

The control file creates the multi-tier presentation (library/sub-library) in the ComponentLibrary window. The control file uses the Extensible Markup Language (XML) format. Thesyntax of the control file is shown below. All words and characters shown are requiredtokens (except the dots). Dots indicate where the information is filled in for each library.The indentation shown below is not required, but it is useful to ensure that XML key wordsare properly nested.

<?xml version="1.0" ?>

<LIBRARIES>

<LIBRARY>

<NAME>...</NAME>

<CATEGORY>DL</CATEGORY>

<SUBLIBRARY>

<NAME>...</NAME>

<RECORD_FILES>...</RECORD_FILES>

</SUBLIBRARY>

<SUBLIBRARY>

<NAME>...</NAME>


</SUBLIBRARY>

<SUBLIBRARY>

<NAME>...</NAME>


</SUBLIBRARY>

<SUBLIBRARY>

<NAME>...</NAME>


</SUBLIBRARY>

</LIBRARY>

</LIBRARIES>

Valid library categories for the <CATEGORY></CATEGORY> argument include DL (VendorComponent Device Library), CKT (Analog/RF Library), and DSP (ADS Ptolemy Library).The DL category is recommended for design kits.

Sub-libraries are optional; but if not used, then RECORD_FILES must be defined for thelibrary. You can also put sub-libraries into sub-libraries to several levels of depth. Multiplerecord files can be specified on one line, separated by a space.

The following optional fields can be defined for each library or sub-library.

<URL>...</URL>

Enter any appropriate web address where the user can find information on the library orcomponent.

<AVAILABILITY>...</AVAILABILITY>

Valid settings are Available, Obsolete, and Not Available.

<PLACEMENT>...</PLACEMENT>

The PLACEMENT tag indicates where the component can be used. Valid settings are Both,Layout, Noschematic, and Nolayout. This line is optional and the default value is Both.

NoteThe library/sub-library names used in the library control files do not have to match the name of the designkit, as defined in eesof_lib.cfg. For the Component Library window, they can be more descriptive.

The Record File

A record file lists all of the components in a sub-library. Each record file must have theextension .rec. The format for the record file is similar to that of the control file.


<COMPONENTS>


41

<COMPONENT>

<NAME>...</NAME>

<DESCRIPTION>...</DESCRIPTION>

<VENDOR>...</VENDOR>

<LIBRARY>...</LIBRARY>

<PLACEMENT>...</PLACEMENT>


<URL>...</URL>

</COMPONENT>

</COMPONENTS>

Multiple component sections can be defined between the beginning and endingCOMPONENTS tags.

Multiple record files can be specified on one line, separated by a space.

The PLACEMENT tag indicates where the component can be used. Valid settings are Both,Layout, Noschematic, and Nolayout. This line is optional and the default value is Both.

The following optional fields can be defined for each library or sub library.

<URL>...</URL>

Enter any appropriate web address where the user can find information on the library orcomponent.


Valid settings are Available, Obsolete and Not Available.

For more information on setting up Component Library window files for a design kit, referto Adding Components to the Component Library Window.

Example


<COMPONENTS>

<COMPONENT>

<NAME>Diode23</NAME>

<VOLTAGE>15</VOLTAGE>

...

</COMPONENT>

</COMPONENTS>

The Library Definition File

This file is optional and is new for ADS 2008 Update 2. With this file new columns ofinformation can be added to a library and shown in the Component Library window.


<LIBRARYDEFINITION>

<COLUMN>

<NAME>...</NAME>

<TAG>...</TAG>

</COLUMN>

<COLUMN>

<NAME>...</NAME>

<TAG>...</TAG>

</COLUMN>

</LIBRARYDEFINITION>

Enter the name of a new column. This will be the name shown at the top of the column inthe Component Library window. If another library is using the same name that you plan touse, use the same name as the other library. This will avoid having separate columnsadded for each library.

<NAME>...</NAME>

Enter the tag for the new column. The new tag can then be used as an XML tag in a recordfile between the COMPONENT tags.


42

<TAG>...</TAG>

When naming the library definition file, ensure that you include .lbd as the suffix. Storethe library definition file in the same directory that the control and record files.

Example


<LIBRARYDEFINITION>

<COLUMN>

<NAME>Voltage</NAME>

<TAG>VOLTAGE</TAG>

</COLUMN>

</LIBRARYDEFINITION>

Library Compatibility

Several new feature were added to the Component Library window configuration files inADS 2008 Update 2. These features are:

Using multiple levels of hierarchy with SUBLIBRARY tagsAdding new columns using the Library Definition File and Record Files.Using the LIBRARY and SUBLIBRARY tags interchangeably

When using ADS 2008 Update 2, these features are available with libraries created withprior ADS versions. To use the ADS 2008 Update 2 Component Library window features,create both a <name>.ctl and a <name>.ctl2 control file. The <name>.ctl file will befound by older versions of ADS. It should not contain any of the new features and itshould not reference any *.rec files with new columns of information. Newer versions ofADS will check for the existence of a <NAME>.ctl2 file when any <NAME>.ctl file isprocessed. The .ctl2 file will be used instead of the .ctl file. The ctl2 file can contain thenew features and reference record files with added columns of information.

NoteIf you have both .ctl and .ctl2 files in a library and decide you no longer need to support older versions ofADS, you should delete the .ctl file and rename the .ctl2 file to .ctl. If you had record files that were onlyreferenced by the original .ctl file, delete these also.

Demand Loaded Components

ADS startup time can be reduced if components in a very large library are not loaded untilthey are needed. This is called demand-loading. To accomplish this, the item definitionand the variables, forms and formsets needed by this item definition file need to reside inan itemdef.ael file inside the cell of the component. The item definition shouldn't be loadedfrom anywhere else in the design kit if they are required to be demand loaded.

If the item definition for a component has already been loaded from the library’s boot file,then the itemdef.ael will be ignored. So the itemdef.ael file shouldn't contain any functionsthat are not related to the item definition.

Adding Demand Loaded Components includes an example of creating the itemdef.ael file.

NoteWhen the item definition is modified from the Design Parameters dialog box, the itemdef.ael file getsoverwritten. No functions, comments, declarations, global variables, formatting, etc. are preserved. Also,the Design Parameter dialog box does not support editing of custom item definitions. So this demandloading technique should only be used for read-only libraries.


43

Model FilesModel files are one way to include simulation data in a design kit. Refer to Understandingthe ADS Design Kit File Structure to determine what form your simulation data will be in.Other methods for including simulation data are discussed in Additional Parts for ADSDesign Kits. The ADS Design Kit Tutorial includes an example of using a model file, themost common method for RFIC foundry kits.

Model files can be translated from Hspice or Spectre formats. The ADS SPICE or SpectreNetlist Translator can be used to perform these translations. Please note that ADS isHSPICE and Spectre compatible, so these translations are not mandatory.

In the design kit structure, model files are stored in the circuit/models directory. Thesemodel files contain process variables and model cards or subcircuit models in netlistformat which are referenced by the components in the schematic and need to be availableto the simulator.

To give the simulator access to these model files, a netlist include component or a customprocess component is placed in the schematic. The section on Adding a Netlist IncludeComponent included an example of creating this type of component. When this componentis encountered during netlisting, a #include statement is written into the netlist.

The #include statement is called a pre-processor statement. When the simulator pre-processor reads the #include statement, it reads the referenced netlist file and loads theprocess variables and models which are in the netlist file. Netlist Include and customprocess components as well as pre-processor statements are discussed in depth in thefollowing sections.

Another pre-processor statement commonly used in model files is the #define statement,and the corresponding #ifdef and #endif statements. These are used to define cornercases for process variations. Corner cases may also be referred to as sections. In a modelfile, a section is started with a #ifdef statement and ended by a matching #endifstatement. A model file or set of model files will include a number of sections withdifferent process variables and model parameters. To enable a section, a netlist mustcontain a #define statement before the #include statement. These pre-processorstatements are also covered in the next section.

If the model files also include verilog-A files, these verilog-A files should be moved to theveriloga directory in the main design kit directory.

Netlist Include or Process Component

As mentioned above, the best way to connect the model to the netlisted schematic parts isthrough the use of a Process or Include component placed on the schematic. Thiscomponent does not have any connectivity information but can be used to specifyinformation such as corner cases, as well as the name of the model file to be used for thesimulation. A netlist callback on this component will generate a #include statement in theoutput netlist. A netlist callback is an AEL function that is executed during netlisting, theprocess of traversing a schematic and outputting a file for the simulator. Netlist callbacksare addressed in Netlist Callbacks.

The Netlist Include component is available from the Data Items palette. This component ismentioned here to give you an introduction into how the include components work. Youcan use this while testing your model files, but for your final design kit, it is recommendedthat you create a custom component to assist your users in attaching the proper file. Thiswas demonstrated in the tutorial in Adding a Netlist Include Component.

To use the NetlistInclude component, click the component bitmap in the Data Itemspalette and place it on the schematic. Alternatively, you can just type NetlistInclude in thecomponent history field on the schematic toolbar. Double-click the component in the


44

schematic to display the dialog box. The dialog that is used to enter the parameters forthe component is shown in Netlist File Include Dialog.

Netlist File Include Dialog

The NetlistInclude component as placed in a schematic window is shown in Netlist IncludeComponent.

Netlist Include Component

For this application, only one parameter on the component needs to be filled out. This isthe IncludeFiles parameter. In the NetlistInclude component dialog, select this parameterwith the cursor. On the right hand side of the dialog is a browser button. To demonstratehow this works, use this browser to navigate to the fet1.net file that you created in thetutorial. If you did not complete that part of the tutorial, the file can be found in your ADSinstallation at $HPEESOF_DIR/examples/DesignKit/SampleKit/circuit/models. If youcannot find this path, it is ok for this example to create an empty file called fet1.net.

When you have browsed to a model file and selected it, note that the IncludePath field isautomatically filled in for you. You can also manually type in a path or add more paths tothe existing one. Each directory can be listed in the same field, separated by space.

Sometimes more than one model file will be included in a design kit. To add more files tobe included, select the IncludeFiles parameter again and click the Add button at thebottom of the Select Parameter list box. A parameter called IncludeFiles[2] will be addedto the parameter list in the dialog.

The preceding section introduced the concept of a corner case. This is also sometimes


45

called a section. A model file will typically be divided up into multiple sections, eachrepresenting a process variation that needs to be simulated. It is not possible in thesimulator today to automatically simulate all corners in batch mode, so they must bespecified individually on the include or process component for each simulation. In theNetlistInclude component edit parameter dialog, type the word FAST into the Section fieldon the right hand side of the dialog.

In order to understand the whole picture, let us now create the netlist fragment that willrepresent the information on this component. To create the netlist without actuallyinvoking a simulation, open the Command Line window from the ADS Main window byselecting Tools > Command Line . In the Command field of the command line windowtype the following code -

decl context = de_get_current_design_context();

// Generate the netlist for the given design context.

decl netlistH = de_netlist_create(context);

// Get the string text from the netlist object.

decl strText = de_netlist_get_text(netlistH);

// Save the netlist to a file.

de_netlist_save(netlistH, "netlist.log");

In a text editor, open the netlist.log file in your workspace directory. It should look similarto the following:

#define FAST FAST

#ifndef

inc_C__Agilent_ADS2011_10_examples_DesignKit_SampleKit_circuit_models_fet1_net

#define inc_C_

Agilent_ADS2011_10_examples_DesignKit_SampleKit_circuit_models_fet1_net \inc_C

_Agilent_ADS2011_10_examples_DesignKit_SampleKit_circuit_models_fet1_net

#include

"C:\Agilent\ADS2011_10\examples\DesignKit\SampleKit\circuit\models\fet1.net"

#endif

#undef FAST

The commands that start with the # sign are all pre-processor commands. You can seehow the information from the edit parameter dialog gets used in the netlist file. Thespecified corner case or section is turned on by a #define statement and the model filegets referenced by a #include statement. It is a good practice to use #undef to turn offthe section after the file that uses it has been read.A sample process component which uses forms and formsets to define corner cases bywriting #define statements to the netlist is include below. Pre-processor commands willbe described in more depth in the section following the sample process component.

Example Process Component with Forms and Formsets

The following AEL code can be copied and modified to create your own custom processcomponent. Read the comments after the file for more information on how the file works.

NotePlease note that the actual Process Include Component used in the SampleKit that comes with ADS, isdifferent. This example has been provided to enable customers to create their own Process Componentsthat use Forms and Formsets

/*----------------------------------------------------------------------------+/

FILE : samplekit_process.ael

COMMENTS : Component definition :

[ global variables ]

[ forms and formsets ]

[ netlist callback function ]

[ parameter callback functions ]


46

item definition

/+----------------------------------------------------------------------------*/

/*--- global variables -------------------------------------------------------*/

/*--- forms and formsets -----------------------------------------------------*/

/*--- corner cases ---*/

create_constant_form("samplekit_form_process_best",

"Best", 0, "", "Best");

create_constant_form("samplekit_form_process_typical",

"Typical", 0, "", "Typical");

create_constant_form("samplekit_form_process_worst",

"Worst", 0, "", "Worst");

create_form_set("samplekit_formset_process_corners",

"samplekit_form_process_best",

"samplekit_form_process_typical",

"samplekit_form_process_worst");

/*--- netlist callback function ----------------------------------------------*/

defun samplekit_process_netlist_cb

(

cbP,

cbData,

instH

)

{

decl net;

decl parmH, parmName, parmFormName;

decl modelFileList;

decl corner;

/*--- #ifdef ---------------------------------------------------------------*/

net = "#ifndef SAMPLEKIT_PROCESS\n#define SAMPLEKIT_PROCESS\n";

/*--- corner case/resistance -----------------------------------------------*/

parmH=db_create_param_iter(instH);

for ( ; db_param_iter_is_valid(parmH); parmH = db_param_iter_get_next(parmH) )

{

parmName = db_get_param_name(parmH);

if (parmName == "CornerCase")

{

net = strcat(net, "; ac resistance\n");

parmFormName = db_get_param_form_name(parmH);

if (parmFormName == "samplekit_form_process_best")

{

net = strcat(net, "#define SAMPLEKIT_BEST_SECTION\n");

}

else if (parmFormName == "samplekit_form_process_worst")

{

net = strcat(net, "SAMPLEKIT_WORST_SECTION\n");

}

else

{

net = strcat(net, "#define SAMPLEKIT_TYPICAL_SECTION\n");

}

}

}

/*--- device models --------------------------------------------------------*/

net = strcat(net, "; models\n");

modelFileList = get_dir_files(sprintf("%s/circuit/models",

SAMPLEKIT_PATH),

"net");

while (is_list(modelFileList))

{

net = strcat(net, sprintf("#include \"%s/circuit/models/%s\"\n",

SAMPLEKIT_PATH,

car(modelFileList)));

modelFileList = cdr(modelFileList);

}

/*--- #ifdef ---------------------------------------------------------------*/

net = strcat(net, "#endif\n");

/*--- return to calling function -------------------------------------------*/

return(net);

}

/*--- item definition --------------------------------------------------------*/

create_item(

"SAMPLEKIT_PROCESS", // name

"Process Include", // description label

"SAMPLEKIT_PROCESS", // prefix

ITEM_UNIQUE|ITEM_GLOBAL, // attributes

NULL, // priority

NULL, // iconName

standard_dialog, // dialogName

NULL, // dialogData

ComponentNetlistFmt, // netlist format string

NULL, // netlist data

ComponentAnnotFmt, // display format string

NULL, // symbol name

NULL, // artwork type

NULL, // artwork data

ITEM_PRIMITIVE_EX // extra attributes

,list(dm_create_cb(ITEM_NETLIST_CB, "samplekit_process_netlist_cb",

"", TRUE)) // netlist callback


47

,create_parm( // parameter

"CornerCase", // name

"Corner case selection", // label

PARM_DISCRETE_VALUE, // attrib

"samplekit_formset_process_corners", // formSet

UNITLESS_UNIT, // unit code

prm("samplekit_form_process_typical") // default value

)

);

The process component shown here only has one parameter, for corner case selection.The three corners are Best, Nominal and Worst. A form set and three constant forms areused to define the list of possible values that are presented to the user when thecomponent is placed in the schematic window. The selected case is used to output theproper #define statement in the netlist. This corresponds to a section of the model file,which must be offset by a #ifdef / #endif block.

Model File Sample is the skeleton of the models file and the netlist file that are producedby the netlist callback samplekit_process_netlist_cb(). Inside of the section of the modelfile will be process parameters and the model with the parameters corresponding to thenominal case. Similar sections will be defined in the model file for the best and worstcases.

Model File Sample

model file samplekit_models.net

#ifdef SAMPLEKIT_NOMINAL_SECTION

.

.

.

#endif

netlist file from schematic

.

.

.

#define SAMPLEKIT_NOMINAL_SECTION

#include "samplekit/circuit/models/samplekit_models.net"

.

.

.

Note that the model file in this example is hard coded as samplekit_models.net. This file isnot present in the SampleKit that comes with ADS, and is used here only as an example.This would be changed to represent the model file or files in your design kit. The globalvariable SAMPLEKIT_PATH is a path variable that will have to be defined with AEL code.

NoteThe NetlistInclude component in the SampleKit that comes with ADS, has been used as the DefaultDesign. So it is not required to include it explicitly in your simulations. It will be netlisted by default in alldesigns that use any component from SampleKit.Note that this technique is useful only if you don't have parameters or cornercases in your NetlistIncludecomponent, otherwise you will receive a re-declaration error if you use the NetlistInclude component asyour default design and place it in your designs too.

The #include Pre-processor Command

To understand how pre-processor commands work, it is helpful to understand the wholesimulation process. When you click the Simulate menu pick, three things happen.

First, the schematic is traversed in a process called netlisting and a netlist file iswritten in the workspace directory. This file is saved with the name netlist.log.Next the simulator pre-processor reads the netlist file. If any pre-processorcommands such as #include or #define are found, they are processed before thenetlist is passed to the simulator. So the simulator never actually sees the #includestatement. Instead, the contents of the file are read and passed to the simulator. Itis especially important to understand this with respect to the #define statement andfor the discussion of limitations of the pre-processor commands.The final step is the actual simulation of the information that is now loaded into the


48

simulator.

The #include statement is fairly easy to understand. A path and filename are suppliedand when that statement is read, the file is read and passed to the simulator. Thefollowing list of limitations should be read and understood before you continue.

If the design kit user is attempting to do remote simulation or parallel simulation, theincluded files need to be present on the remote machine in the same location thatthey are on the local machine. This can be accomplished by NFS mounting the disks,which will avoid potential problems caused by copying files around, such as losingedits made in the remote location. If NFS mounting is not possible, a netlist callbackcould be written that would read the referenced file and output it directly into thenetlist, instead of writing the #include line into the netlist.If an included file has subcircuit models or subcircuits of any type (which start withthe command define ), the process or include component that generates the#include statement must be placed at the top level of the hierarchy in the design.Nested defines are not allowed, and placing this type of component into a lower levelof hierarchy will result in a define statement within a subcircuit definition. If anincluded file contains model cards and variables only, the file can be included fromany level of hierarchy.The name of an included file, as listed on a process or include component, cannot bea variable reference.No tuning, sweeping, optimization or yield can be performed on the data in theincluded file. Additionally, the information in an included file is not available for backannotation on a schematic or other similar functions. This is an acceptable limitationsince this information can be thought of as read-only.The order of included files cannot be controlled if multiple separate includecomponents are placed. The component called NetlistInclude is designed to enforcethis restriction. Only one NetlistInclude component can be placed, but it takes a listof files and retains the order of the files when outputting a #include line to thenetlist.

The #ifdef and #define Pre-processor Commands

As introduced above, #ifdef is used to define a corner case or section in a model file. Asection can contain process variables, model cards, subcircuit definitions or a combinationof these, to represent a process variation. Typical names for corner cases are FAST,NOMINAL and SLOW. A model file containing these sections would look like this:#ifdef NOMINAL

[process variables and model parameters for the NOMINAL case would be included here]#endif

#ifdef FAST

[the same process variables and model parameters would be included here, but withdifferent values to simulate the FAST process variations.]#endif

#ifdef SLOW

[the same variables and models would be included here again, but with values to simulatethe SLOW process variations.]#endif

Remember from above that the netlisted schematic that would include this model filecontains the lines shown below. Note that the sample fet1.net file does not actuallycontain these sections at this time.#define FAST

#include

"C:\Agilent\ADS2011_10\examples\DesignKit\SampleKit\circuit\models\fet1.net"

#undef FAST

The order in which all this information is processed is as follows:

Netlist file netlist.log is created from the schematic. The #define and #include1.


49

statements are generated from the include component.The simulator pre-processor reads the netlist.log file. FAST is defined and the include2.file fet1.net is read.When the model file is read, the NOMINAL and SLOW sections are completely3.disregarded. Only the FAST section is read.

It was mentioned above that corner cases cannot be swept automatically in the simulator.This is because, based on what was shown in step #3 above, the simulator only hasknowledge of one corner section at a time. The others are filtered out by the pre-processor. The user has to turn on each section individually and save the datasets forcomparison.

The last concept that needs to be explained is how to use a custom process includecomponent to make it easier for the design kit user to perform these simulations. First ofall, the netlist file name can be hard-coded into a custom component. In other words, theuser will not have to enter any file name. The path is known because the model file existsin the circuit/models directory of the design kit and the file name is written into the AELcode that generates the netlist. This AEL code is called a netlist callback and is explainedin Netlist Callbacks.

In order to make it easier for the customer to select which corner case to simulate, thesection names are presented to the user in a list, of which one at a time can be selected.To generate this list, a form set is defined in AEL code and then referenced in the itemdefinition, also AEL code. Forms and formsets are defined in Forms and Formsets. Itemdefinitions are covered in Item Definition. The best way to complete your understanding ofthese concepts is to return to the ADS Design Kit Tutorial, where two examples of customprocess include components are given.

Any custom process or include component, that is required by other components in adesign kit, should be listed at the top of the palette, since the user must place it in theschematic when using any other components in the design kit. In fact, it is so essentialthat this process component be included in a schematic, that some design kit developerswill add a netlist callback to any device component that refers to a model in the netlistmodel file. This callback can traverse the schematic and warn the user if a processcomponent has not been placed, or it can simply place the process componentautomatically.

Model Naming Limitations

All components and variables in a model file must be unique, to avoid colliding withanother with the same name if another file is included at the same time. This can happen,for example, when designing a multi-chip module if components from more than onedesign kit are used in the same design.

This requirement applies to model names, subcircuit names and global variable names inthe models. Components or variables (parameters) inside of a subcircuit are consideredlocal and are protected automatically. <foundry> _ <process> _ <name> is therecommended naming convention for all global items in an RFIC foundry design kit. At thepresent time, the netlist translators do not facilitate this process, so it must be donemanually or with a script run on the model file after the translation is complete.

Functions for Spectre and Hspice Compatibility

There were a number of Spectre/Hspice compatibility functions added into design kits inthe 2003A release that can help you maintain your equations as is between differentsimulators. The simulator team at Agilent Technologies has added some of these functionsinto the simulator itself. If you have made your own compatibility functions, you will needto remove these functions because they will now produce a redefinition error.


50

The functions implemented in 2003A were:

asinh() fmod()

atan() hypot()

ceil() log10()

floor() pow()NoteFor a list of available simulator functions, refer to Simulator Expressions.

The eesof_lib.cfg TemplateThe eesof_lib.cfg file is a coniguration file that contains information on the variousvariables that are related to design kits. e.g. the location of associated model files,simulation data, library browser control files, and other important files. A template of thisfile must be included in the design kit's main library. When a design kit is added to aworkspace, the various configuration variables from this file are used by ADS. To editthese variables, the library must be added in editable mode to the workspace, by choosingfor_editing_pdk.defs instead of lib.defs.

For details on the various configuration variables in this file and how to edit them, seeConfiguration Variables.

NoteThe eesof_lib.cfg file should be updated only using Library Configuration Editor.

AEL Code for Loading a Design KitAs mentioned in the previous section, a design kit will contain a boot file that helps thesystem load the design kit. The name of this file is recorded in the eesof_lib.cfg file sothere isn't a reserved name for the file that is searched. However, the name boot.ael istypically used in most ADS design kits today and the file resides in the de/ael subdirectoryof the design kit directory structure.

A boot file can be used to load the AEL item definitions for all components in a design kit,as well as to set up the palettes. The ADS Design Kit Tutorial gives an example of this use.Additionally, the boot file may be used to define some global variables or functions specificto the design kit. These are usually for advanced functionality and specific details are notincluded in this document.

The other method to load item definitions is through the file itemdef.ael, as explained inthe previous section on Adding Demand Loaded Components. The item definitions will besearched for in the file itemdef.ael in the cells of the components, only if these haven'tbeen found elsewhere in the design kit. These are not automatically loaded. They'reloadedonly when the system needs these item definitions (e.g. while placing a component inyour design).

You can also execute a particular code when your library is unloaded. To achieve this,create a function in your kit which contains the code that needs to be executed every timethe library is unloaded. Open the Library Configuration Editor for your kit and in thesecond tab , assign the function's name to the field unboot function and click OK. Nowevery time this kit is unloaded, the assigned function will be executed.

The about.txt FileA file named about.txt should be supplied and stored in the doc directory of the design kitstructure. This is required for version tracking and will assist Agilent Technologiescustomer support. The file will contain information such as the design kit version and datecreated. Process and component information can be included, as well as sourceinformation if the models were translated from another library. Revision history, support


51

contact information or any other details can be listed if desired.

A template for this file is shown in the table below. A future version of the design kitsoftware may have a menu pick to give the user easy access to this information.

Design Kit about.txt Template

Name:

Version:

Date:

Description:

Revision

For more information on design kit versions, refer to Assigning a Version .

The Example WorkspaceThe quickest way to help your customers start using your design kit is to provide a sampledesign that they can work from. This is a simple way for them to see that a design kit isinstalled properly and verify that they can run a simulation. It is also a way for you toshow some special features of the design kit.

To add the example workspace to the design kit, first create and save a small test circuit,including a process or include component if required. Then simulate the circuit and savethe data display. More test circuits can also be saved if desired. When all test designshave been saved, archive the workspace using the File > Archive Workspace menu pickin the ADS Main window. Copy the archived workspace to the examples directory in thedesign kit file structure. The tutorial steps in ADS Design Kit Tutorial can also be referredto for help in building an example workspace and storing it with the sample design kit.


52

Design Kit Development for LayoutThe purpose of this section is to show how to add layout artwork to a design kit. Theinformation provided in this section assumes that the component for which artwork isbeing added to has already been defined in the design kit for use with schematic andsimulation.

Demonstration Design Kit (SampleKit)A SampleKit is shipped with Advanced Design System. The SampleKit is provided toillustrate various aspects of creating a design kit with artwork. It can be used for buildingschematics and layouts that simulate. It does not represent any specific IC design processand cannot be used to create actual ICs. This design kit is located at:

$HPEESOF_DIR/examples/DesignKit/SampleKit

This design kit can be added for use just like other ADS design kits using the Add Librarydefinition File option in the ADS Main window menu DesignKits > Manage Libraries.

General Process for Adding Artwork to a Design Kit

Preparation

Ensure that you have a working design kit that can be used to create schematics and1.perform simulations.Develop a list of all components that will have artwork associated with them. Also,2.list each component parameter that will affect the shape of the artwork.Have a list of the layers, purposes and LayerIDs that you will use. This information is3.specific to a particular design process.Create an illustration of the artwork for each component that is roughly to scale using4.the default values of component parameters affecting the shape. Label the location ofthe pins. Ensure that you know what layerID each shape will be on.

Adding the Artwork to the Design Kit

Create an ADS workspace to do your work in.1.Add your design kit by selecting the for_editing_pdk.defs file in your kit, because you2.need write permissions for this kit. Ensure that you can place each component on aschematic.Set up the process information for the design kit library. Use the default file names3.for the preferences (layout.prf). The substrate information is optional. Save theprocess information to the proper location in your PDK's libraries. For moreinformation, refer to Specifying Technology File Information.For each component (see Adding Layout Artwork for details):4.

Choose either fixed artwork, manually written AEL macro, or AEL macro createdby the Graphical Cell Compiler. If you have one or more parameters that affectthe layout, you cannot use fixed artwork.Create the fixed artwork (see Creating Fixed Artwork) or AEL macro (seeCreating the Parameterized AEL Macro Artwork Manually ) and link it to thecorresponding cell in the design kit library. Restart Advanced Design Systemafter these edits.Test the component you created (see Testing the Artwork).


53

The following sections of this section provide the details related to the various parts ofadding artwork to a design kit.

Specifying Technology File InformationIt is important to set up information that is specific to your design kit before attempting tocreate artwork for the design kit. In Advanced Design System, this is separated into threemain areas:

Layer Definitions - Layer definitions enable you to specify artwork layers, includingtheir number, color, pattern, and their ability to connect to other layers.Layout Preferences - Layout preferences enable you to specify the units of distancemeasurements and other information.Substrate Information - Substrate information is optional. This information is used tospecify the electrical properties associated with the artwork layers that you havedefined. The Momentum electro-magnetic simulator uses substrate information forcases where arbitrary shaped components need to be simulated. This is differentinformation than the substrate components used in schematics when varioustransmission line components such as microstrip are simulated.Material Definitions - Material definitions are optional. These are used to specifyvarious electrical and magnetic properties of Conductors, Dielectrics andSemiconductors. The Surface Roughness Models are also defined here.Layer Mapping - This is used to specify the name of the Layer, Purpose, GDSLayer,and GDSPurpose. This is optional and required only if you need to export or importGDSII files of designs, which use your PDK's technology.

NoteUse only the default file names for the preferences (layout.prf) and layermap file (LayerMap.map)

Technology Setup

Every Library has its own technology. This technology could be natively created for thatlibrary, or the library could also refer to the technology of another library.

To set the technology of your Design Kit, in the main ADS window, go to Options >Technology > Technology Setup. In the dropdown, select your kit's technology library.Select the Referenced Libraries tab and click the Show Advanced Options button ifvisible. Show Advanced Options button is visible for single time only, once you click itwill not be shown again until you reopen the "Set Technology" dialog box.

Now select the first radio button, which mentions that the library has technology -

For adding ADS in-built schematic layers to your design kit, click Add ReferencedLibrary and select ads_schematic_layers.For adding ADS in-built layout layers to your design kit, click Add ReferencedLibrary and select ads_standard_layers


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NoteNote that the Technology Setup shown in the snapshot doesn't have the ads_standard_layers for layout.This is because the SampleKit's technology has it's own layout layers.To add custom schematic and layoutLayers, see Layer Definitions.

The most important information to define sets the units and the smallest layout x, ycoordinate (database unit) that can be used.An example of what you might see is Layout Units equal to mm and Resolution equal to.001. This means that the smallest x, y coordinate that can be specified is 0.001 mm. Thisnumber should be carefully chosen because it determines the smallest and largest size oflayout shapes. Length measurements in the layout database can span a dynamic range ofabout 100,000,000 (1e8).

In the example above the largest dimension of your layout could be about .1 meter (.001mm * 1e8 = 1e5 mm). The resolution also has to be small enough to ensure that thelayout can be properly represented. This is especially true if you expect to use curvedgeometry such as arcs in your layout. Each point along the arc will be specified by thisdatabase unit.

NoteOnce the units and resolution have been specified and layout artwork using these has been created, it isnot recommended to change the units or resolution.

For setting the Layout Unit, go to the Layout Units tab, check the Enable Units boxand select your desired layout unit.For setting the Resolution, go to the Layout Units tab, check the EnableResolution box and enter your desired Resolution.


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Click OK. You may receive a message about changing the library's units, databaseresolution and technology type. Click Yes. You have now set your design kit technology touse the ADS schematic and layout layers.

Layer Definitions

This section briefly discusses layer definitions. For more information, refer to DefiningLayers.

Every design has an associated layer file. When you create a design, the programautomatically looks for the layer information in the library where the design is created.Note that the library could have its own technology, or it could also reference thetechnology from another library.

To start editing the layer definitions, open a layout window and then choose Options >Technology > Layer Definitions. The Layer Definitions dialog box appears. Choose yourkit's technology library from the drop-down.


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You can add and remove Layers, Purposes and Layer Display Properties from this dialogbox. The Purpose you would generally want to use is drawing.You can remove any layers that you do not want except the default layer. The defaultlayer has a special purpose in ADS. If artwork is viewed and there are shapes on a layerthat do not exist in the layer definitions, they will be displayed with the definitions of thedefault layer.

The Color, Trans, Pattern, Shape Display, and Line Style control how the shapes on eachlayer will look. While all layers may be important to the process of fabrication of yourartwork, some layers are less important for the designer to see. The layers whereconnections will be made are usually the most important for the designer to see. You canset the Shape Display to Outline to cause shapes to display without filled centers. Thismight be used for your less important layers. The more important layers could use ShapeDisplay of Filled or Both. When using Filled or Both, you may want to change the Pattern.By using a pattern rather than a solid color on a layer it enables you to partly see throughthe layer and see other layers below it.

For information on adding custom fill patterns, refer to Adding Custom Fill Patterns to aDesign Kit.

Layer Binding

Layer Binding enables you to control which layers will make a connection to other layerswhen pins and shapes overlap. Layer Binding is found under the Layers tab of the LayerDefinitions dialog box. For ADS versions before 2004A, only pins could makeconnections. Starting with ADS 2004A, shapes (polygons, circles, paths, and rectangles)can also make connections between components. Also, components can have area andedge pins in addition to their point pins. Because of this, it is important to have your layerbinding specified correctly.

In a design process, interconnects are made on metal layers or by holes in a via layer. Torepresent this in ADS, the Layer Binding should have values on metal or via layers and


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other layers should have empty Layer Bindings.

The layer binding field is a list of words separated by spaces. The words typically are layernames, but this is not required. When pins or shapes overlap but are on two differentlayers, they will connect if a word in the layer binding list of the first layer matches thesame word in the layer binding list for the second layer.

Examples

Layer Name Layer Binding List

Metal1 Metal1

Metal2 Metal2

Since neither layer has the same word in their layer binding list, they will not connect toeach other.


Metal1 Metal1

Metal2 Metal1

Since both layers have the same word (Metal1) in their layer binding list, overlapping pinsand shapes on these layers will connect to each other.


Metal1 Metal1 Metal3

Metal2 Metal2

Metal3 Metal3 Metal1

The pins and shapes on layers Metal1 and Metal3 will connect, but those on the Metal2layer will not connect.


Metal1 Metal1

Via1 Via1 Metal1 Metal2

Metal2 Metal2

Via2 Via2 Metal2 Metal3

Metal3 Metal3

This is a typical way to setup metal and via layers. Pins and shapes will connect fromMetal1 to Metal2 if they overlay shapes on the Via1 layer. The same situation occurs forpins and shapes on Metal2 and Metal3 layers.


Metal1 conductors

Metal2 conductors

Metal3 conductors

The three layers have a common word, conductors, in their list and each will connect tothe others. Using "conductors" this way enables you to refer to a group of layers that willall connect to each other.

Layout Preferences

This section will briefly discuss the most important layout preferences that relate to aspecific design process. There are numerous other layout preferences that can bespecified. For more information, refer to Preferences for Layout.

To create a layout.prf file, add your kit to a workspace by selecting thefor_editing_pdk.defs file. It is assumed that you have already created proper technologyfor the design kit, as described in Technology Setup. Create a layout cell in the kit's


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library, and go to * Options > Preferences*. The Preferences for Layout dialog boxappears. Make the required changes and use the Save a copy button, to save the filewith the name layout.prf in the main library of the design kit. Repeat the same steps forcreating and saving the schematic.prf file.

In the dialog box, there are certain preferences with a *** mark. These are library-specific preferences, for which the values in your library (design kit) will take precedence.For the others, the values will be taken from the global workspace preferences.

Grid/Snap Preferences

An x, y snap grid is available on your layout drawing area. If Snap and Grid Snap areenabled, you will not be able to use your cursor to select an x, y point that is not on thisgrid. There are exceptions to this if other snap modes such as pin or vertex snap are used.

To set the grid/snap preferences in your layout, select the Grid/Snap tab in thePreferences for Layout dialog box.

The Snap Grid Distance defines the points on your snap grid. With the units exampleabove, a Snap Grid Distance of 0.25 means that every 0.25 µm a point could be selectedby the cursor. There is a relationship between the Resolution and the Snap Grid Distance.Even though both can contain decimal fractions, the Snap Grid Distance should be amultiple of the Resolution. A Resolution of 0.1 would not work well with a Snap GridDistance of 0.25.

The Snap Grid Per Minor Display Grid and Minor Grid Per Major Display Grid determinehow much of the grid is visible. A small (minor) grid point is displayed at multiples of theSnap Grid Distance as determined by the integer multiplier Snap Grid Per Minor DisplayGrid. A major (larger) grid point is displayed at multiples of the minor display grid asdetermined by the integer multiplier Minor Grid Per Major Display Grid.

Example

Layout Unit: mmSnap Grid Distance: .25Snap Grid Per Minor Display Grid: 4Minor Grid Per Major Display Grid: 10Resolution: .01

X, Y points as small as .25 mm can be selected. A visible grid with small points at 1 mmand large points at 10 mm will be displayed. The Snap Grid Distance should be a integermultiple of the Resolution.

The values of this snap grid can be changed later without it affecting artwork that hasalready been drawn.

Pin and Ground Symbol Size

The size of the pin and ground symbol should be changed so that they are a reasonablesize compared to other components in your design kit. The size refers to the height andwidth of the ground symbol and is expressed in layout units (i.e. 5 means 5 µm or 5 mil,etc.).

To set the size of the pin and ground symbol size in your layout, select the Placement tabin the Preferences for Layout dialog box.


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Component Text Size and Layers

The component name and its instance name are displayed on each component added toyour layout. The size of the component text needs to be adjusted so that they arereadable, but not large enough to overlap onto other components in the layout. The textsize refers to the height of the letters in layout units. It can be set to any value includingfractional values (i. e. 0.5, 2.5, etc.). It applies only to newly placed components. If youhave a layout with components already placed on it, this will not change the componenttext size on these. Use the Edit > Properties menu to change existing component textsize.

To set the component text size and layers in your layout, select the Component Text tabin the Preferences for Layout dialog box.

Set the Size to the height of the desired text size.

Note the Apply To Layer section. This section contains the names of the layers where thecomponent name and instance name will be drawn.

You will need to define at least one layer in your layer definitions that is not one of thelayers you will use to process your artwork. It will only be used for documenting thecomponent and instance names.

Once you have defined the Layers for your process you should return to this dialog boxand choose the layers that your Component Name and Instance Name will be drawn on.

Substrate Information

The Momentum simulator or the Advanced Model Composer can be used to simulatepassive structures and to create new components. These capabilities might be used by thedesign kit developer or by the end user of the design kit. In order to use this capability,additional information about the process must be specified. For information on how tocreate a substrate definition for your process, refer to Substrates in Momentum .

Substrate information is not required for a design kit; however, if you want to addsubstrate information to your design kit, the substrate files must be placed in thetechnology library of the design kit. These files have an extension of .subst. To create anew substrate file, in the main ADS window, right click on the library for which you wantto create the new substrate, (it ia assumed that you have already added your kit to theworkspace in editable mode by selecting for_editing_pdk.defs) and select New Substrate.


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When design files are created in any library of your workspace, by choosing the EM >Simulation Setup tab in the layout window, you can choose which substrate file to usefor designs in that library.

Via Configuration

If you want to put via configuration files into the design kit they must be placed in the de> defaults folder of the design kit. You can put multiple via configuration files in thisdirectory. They can have any name that ends with ".via". It is a good practice to put thedesign kit name as a prefix for this file name.

The via configuration files are created in layout using the Options > Via Configurationmenu. When you use the layout Insert > Trace menu, you will be able to choose a specificvia configuration file.

Adding Layout ArtworkMany of the topics covered in this section refer to information provided in other ADSdocumentation. Schematic Capture and Layout is very useful as a reference, especiallyArtwork.

Using Pins in Artwork

Angle

The angle of a pin is important for the correct operation of Design Synchronization. Itdetermines the direction that another component will be drawn relative to the pin. Thefollowing chart shows the angle to specify for the pin so that the next component will flowaway from the current component in the correct direction. For more information about pinangle, refer to Generating a Layout.


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For consistency with ADS components, two pin components generally have pin 1 on theleft-hand side and pin 2 on the right. In this case, pin 1 would have an angle of 180degrees so that the next component will be drawn to the left of pin 1. Pin 2 would have anangle of 0 degrees as shown in Two Pin Component in ADS.

Two Pin Component in ADS

Artwork Origin

The origin (x=0, y=0) of your artwork determines the part of the component that is at thelocation of the cursor when you are inserting a component based on this artwork. For bestusability, one of the component pins should be at the origin. Frequently this is pin 1 of thecomponent; however, it could be another pin.

Pin Layer and Layer Binding

Pins of a component are placed on a layer. A pin represents a connection point to anartwork shape. The layer the pin is on should be the same layer as the artwork shape. Formore information, refer to Layer Binding.

Edge and Area Ports

When a Pin is placed into a layout and this layout is placed as an instance into anotherlayout, you see a corresponding pin at a single x,y point. You can also place edge andarea ports into a layout and these will become edge and area pins when the layout isplaced as an instance into another layout. Edge and Area Ports must always be associatedwith a single Pin. The Pin defines where automatic connections will be made when usingdesign synchronization.

An edge port is created by placing a polyline or arc into your layout and then designatingthat this shape is associated with a specific Pin. An area port is created by placing apolygon, circle, rectangle, or path into your layout and then designating that this shape isassociated with a specific Pin. You may have multiple edge and area ports associated withone Pin and they may be on multiple layers. See below for specific details of creating edgeand area ports for fixed artwork, AEL macros, and with the Graphical Cell Compiler.


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For more information on edge and area ports, refer to Edge and Area Ports.

Creating Fixed Artwork

The term Fixed Artwork means that the shapes in the artwork do not change. Anyparameters on the component will not cause a change in the shapes. If you needparameters to change the shapes you will need to use a parameterized AEL macro forcreating your artwork.

Creating Your Own Layout

To create fixed artwork:

Add your kit in editable mode to the workspace, by choosing the1.for_editing_pdk.defs_ of the kit.Create a layout view of the component for which you wish to add the fixed artwork.2.You can do this by right-clicking on the component name in the Library View in theADS Main window, and selecting New Layout.Plan to draw the shapes of your component so that the origin will be at a logical3.location (see Artwork Origin).Select the correct layer for each shape. Draw the shape.4.Select the correct layer for each port. Using the Insert Pin button on the toolbar,5.add a pin at the correct location and angle for each pin that will be in the finalcomponent. Ensure the Pin num is correct for the pin number of the final component.You may also want to edit the Pin Name to be more descriptive such as Plus or Minus.

In the layout cell, go to File > Design parameters, and select the View-Specific6.Configuration tab. In the Type dropdown, choose Referenced/Fixed , and give the<LibraryName>:<CellName> in the Name field. Note that LibraryName is the nameof your PDK's library, and ComponentName is the name of your component. Save thelayout cell.


63

You can now use this component in your designs by placing it from the Library View7.in the ADS Main window (or Palette or Library Browser, if you have added thiscomponent to them).

Notice that the component now has point pins. Also, it can only be selected as awhole.

Using Edge Ports

Ensure that you have already placed the Pin that the edge port will be associated1.with.Add a polyline or arc where the edge port will be located. This will typically be along2.the edge of some other polygon, rectangle, circle or path.Choose the Edit > Edge/Area Pin menu item. Select the polyline or arc and the pin3.number it will be associated with. Click OK.


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For more information on edge ports, refer to Edge and Area Ports.

Using Area Ports

Ensure that you have already placed the Pin that the area port will be associated1.with.Add a polygon, rectangle, circle, or path where the area port will be located. If your2.artwork already has a polygon, rectangle, circle, or path where you want the areaport, you do not need to add another.Choose the Edit > Edge/Area Pin menu item. Select the polygon, rectangle, circle3.or path and the pin number it will be associated with. Click OK.


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This fixed artwork has a edge port associated with Pin number 1 and an area portassociated with Pin number 2.

This is an instance of the fixed artwork that has been placed into a second layout.

For more information on area ports, refer to Edge and Area Ports

Creating Fixed Artwork from GDS-II Files

To create fixed artwork from a GDS-II file:

Open the workspace where you have your kit added in an editable mode. Open a1.layout cell.GDS-II transfers shapes based on the GDS Layer Number and GDS DataType. These2.may be the same as your current Layer Number and Layer Purpose (as defined in thetechnology of the design kit) or they may be different. If they're different you maycreate a map to resolve these differences.Choose the File > Import menu to open the Import dialog box. Under File Type,3.


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select GDSII Stream Format and click the Browse button to select a GDS-II file.Click on More Options, and in the dialog box that opens up, choose the kind ofmapping you need, from the dropdown available. For more details on these optionsfor Layer Mapping, see Import GDSII More Options . Click OK to perform the GDS-IIfile import.Your GDS-II file may have contained one or many layout designs. For each design4.that you will use as fixed artwork in your design kit:

You will need to add pins to the design. Select the correct layer for each pin.Using the Pin button on the toolbar, add a pin at the correct location and anglefor each pin that will be in the final component. Ensure the Pin num is correct forthe pin number of the final component. You can also edit the Instance Name tobe more descriptive such as Plus or Minus.Choose File > Save As to save a copy of the design as the layout view of yourcomponent, in your PDK's main library.

You can test how this component would look by opening another layout window and5.placing this component from the Library View in the ADS Main window.Notice the component location relative to the cursor while you are inserting it.

Creating the Parameterized AEL Macro Artwork Manually

Creating the AEL Macro Function Files

The following section makes frequent references to various AEL functions. The details foreach of these functions can be found in AEL. Refer to the SampleKit to see examples ofAEL macros. The AEL macros are located at:$HPEESOF_DIR/examples/DesignKit/SampleKit/circuit/artwork

Simulator and User Units

When you look at the length parameters of a component on either the schematic orlayout, you will see them expressed in fundamental units of meters or feet such as 100µm or 100e-6. This is referred to as simulator units.Your layout preferences have a layout length unit specification such a µm (micrometers)that is used during the creation of artwork. If you draw a line 100 units long with a layoutlength unit of µm, the 100 represents 100 micrometers. This is referred to as user units.Some AEL functions use simulator units while others use user units. AEL functionsbeginning with de_draw use simulator units while functions beginning with de_add,db_add or de_define use user units. Length parameters that are passed into your AELmacro are always in simulator units. You can get the conversion factor from simulatorunits to layout user units by using the db_factor() function.

Example

decl conversionf;

conversionf = db_factor(); /* returns 1e6 if layout units are um *

Layer Definitions in the Macro

The layers and purposes used in an artwork macro need to be consistent with thosedefined in the technology of the library. When writing the artwork macro, , AEL variablesshould be declared for the layerIDs that will be used and then refer to these each time theLayerID needs to be used. This makes the file easier to understand and easier to change ifthe layer definition changes. Any libraries can define the same names as long as they do


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not refer to each other's technology. Two libraries could use the same names, if thenames are defined in one of the libraries or a 3rd library and the other library refers to thetechnology of the library defining the names.

LayerIDs are combinations of Layers and Purposes. For more information on LayerIDs, seeLayer Identifier.

Example

/* LayerID Definitions */

decl def=db_layerid(0,-1);

decl mesa=db_layerid(1,-1);

decl nicr=db_layerid(2,-1);

decl M0=db_layerid(4,-1);

decl Via_Nit2=db_layerid(5,-1);


decl nicr_DRC=db_layerid(2,1);

decl mesa_DRC=db_layerid(1,1);

defun sample_fet1(model,nf,gw,_M)

{

decl designContext= de_get_current_design_context();

db_add_rectangle(designContext,Via_Nit1,0,0,2,2);

See also:

$HPEESOF_DIR/examples/DesignKit/SampleKit/circuit/artwork

Simple Artwork Macro Function

/* Layer Definitions */



defun sample_res1(Type,R,w,l,Rsh)

{

de_set_global_db_factor()


w=w*1e6;

l=l*1e6;

decl ox=0;

decl oy=0;

/*set origin*/

de_set_origin(ox,oy);

/* Create the artwork shape */

db_add_rectangle(designContext,Via_Nit1,ox+1,oy-2-w/2,ox+6,oy+w/2+2);

/* Create pin 1 with pin angle of 180 */

db_create_pin(designContext, ox, oy, 180, M0, 1, NULL);

/* Create pin 2 with pin angle of 0 */

db_create_pin(designContext, ox+12+l, oy, 0, M0, 2, NULL);

}

This AEL macro begins with the variables that define the layerIDs. On the line defining thefunction, notice that the parameter list contains parameters that are not necessarily usedfor the artwork. This parameter list must correspond to the parameter list in yourcreate_item component definition. The names do not have to be the same, but the samenumber of parameters and same parameter positions are necessary.

The de_set_global_db_factor() function should be near the beginning of each macro youwrite. It ensures that the various shapes drawn by the de_draw_xxx functions are drawnin the right size by enforcing consistence between the simulator and layout units.

It is no longer mandatory to set the layer using a separate function. The new functionsintroduced from ADS2011, like db_add_rectangle(), take the LayerID as an argument aswell.

Creating Shapes

There are 2 ways in which you could create shapes -1. (Recommended) Use the functions that take the LayerIDs and Contexts as an


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argument. This is efficient as the Layer and Purpose doesn't need to be set separately.If you are using user units, the following ael functions can be used to create shapes:

db_add_arc1db_add_arc2db_add_arc3db_add_arc4db_add_circdb_add_path with db_set_path_corner, db_set_path_width and db_set_miter_cutoffdb_add_rectangledb_add_textdb_add_polygon with db_add_arc, db_add_point and db_enddb_add_polyline with db_add_arc, db_add_point and db_end

2. Use functions for which you will have to set the Layers and Purposes separately. TheLayerID can be set using the function db_set_entry_layerid. If you still use the functionde_set_layer, the Purpose defaults to Drawing.

If you are using user units, the following ael functions are used to create shapes:

de_add_arc1de_add_arc2de_add_arc3de_add_arc4de_add_circde_add_path with de_set_path_corner, de_set_path_width and de_set_miter_cutoffde_add_rectde_add_textde_add_polygon with de_add_arc, de_add_point and de_endde_add_polyline with de_add_arc, de_add_point and de_end

If you are using simulator units, the following ael functions are used to create shapes:

de_draw_arc1de_draw_arc2de_draw_arc3de_draw_arc4de_draw_circde_draw_rectde_draw_textde_add_polygon with de_draw_arc, de_draw_point and de_endde_add_polyline with de_draw_arc, de_draw_point and de_end

Refer to AEL for the details of each function.

Creating Pins

Pins can be created using the following AEL functions:

db_create_pin (recommended)de_draw_port (using simulator units)de_define_port (using user units)db_define_edge_area_port

Refer to AEL for the details of each function.

Adding Your AEL Artwork to the Design Kit

You may place all of your AEL artwork macro functions into one file or put them into


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multiple files.

Copy the AEL macro files into the <design_kit>/circuit/artwork directory. The files1.may be *.ael, *.atf, or both.AEL lines must be added to the <design_kit>/de/ael/boot.ael file so the artwork2.macro files will be loaded. The following example does not specify the .ael or .atfsuffix on the filename. ADS will try to load the .atf file if it is there. If no .atf file isthere, ADS will try to load the .ael file.

/*Example boot.ael File*/

/* Set a variable to store the top directory of design kit */

decl SAMPLEKIT_PATH = designKitRecord[1];

/* Set a variable to store the path to the artwork.ael file*/

load(strcat(SAMPLEKIT_PATH, "/circuit/artwork/sample_fet"));

See also $HPEESOF_DIR/examples/DesignKit/SampleKit/de/ael/boot.ael file

Add your PDK in editable mode to your workspace (by choosing the1.for_editing_pdk.defs).Create a layout view (typically named layout) of your component's cell. Open it, go to2.File > Design parameters, and select the View-Specific Configuration tab. In the Typedropdown, choose AEL Macro , and enter the name of the artwork macro in the Namefield. Save the layout cell.

NoteIn ADS2011.10, an itemdef.ael file may get saved in the component's cell, if the information in the thirdtab of the Design Parameters dialog box is changed. This will be fixed in future releases. The itemdef.aelfile should ideally get created/edited only when information in the other two tabs is modified. The itemdefinition from this file anyways is only be used if not loaded elsewhere in the kit. If not required, this filecan be deleted.

After adding artwork to one or more components proceed to Testing the Artwork.


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Troubleshooting Execution Errors in AEL Macros

If your artwork does not look like you planned or if you receive an error message duringthe insertion of an AEL macro, you may need to see the values of various AEL variables tounderstand why. Writing the information to a log file enables you to view the values ofthese variables.

Writing to a Log File

The information described below will enable you to see what parts of a function areexecuting and to print out variables.The first three lines should go near the beginning of the AEL macro function that needs tobe checked. Each time the component is inserted or edited, the AEL macro function will becalled. These lines will open and append BEGIN to a file called macro.log in your currentworkspace.

decl fid;

fid = fopen("macro.log","A");

fputs(fid,"\n\nBegin\n"); fflush(fid);

The next line is an example of a line that can be placed anywhere in the function. The lineshould be customized by replacing rotation with the variable that you want to view. Put asmany of these lines as necessary in your function.

fprintf(fid,"rotation =%s\n",identify_value(rotation));

fflush(fid);

Put the following two lines at the end of your function or just ahead of any returnstatement. They write END in the file and close it.

fputs(fid,"End\n"); fflush(fid);

fclose(fid);

Reloading an AEL Macro File without Restarting ADS

If you edit your artwork file and wish to reload it and test it without restarting ADS:

Choose Tools > Command Line in the ADS Main window. The Command Line dialog1.box appears.In the Command >> field, enter the command:2.load("sample_fet.ael");

Click Apply. This will reload the .ael file if it is in your current workspace. You can3.also add a path to the file and load it from anywhere.

In general, when you restart your workspace, previously loaded ael files (from includedlibraries also) get loaded again.

Creating AEL Artwork with the Graphical Cell Compiler

The information in this section provides a summary of steps needed to create an AELmacro using the Graphical Cell Compiler. An emphasis is placed on the steps required tointegrate a GCC AEL macro into a design kit. If you are not familiar with the Graphical CellCompiler, see Getting Started with the Graphical Cell Compiler.


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Creating the GCC Based AEL Macro

Add your PDK to a workspace(in editable mode by choosing for_editing_pdk.defs)1.and open a new layout view, in a library which uses the PDK's technology.Create the initial drawing for the component. GCC operates on existing shapes by2.stretching, rotating, moving, deleting, etc. You must choose the initial shapes wisely.Here are some suggestions for doing this.

If you are making a component that will be built by a lot of copying androtating, such as a spiral inductor, you should pay close attention to First SpiralExample.For each parameter that will affect the layout you need to choose the parametervalue. Many components have a minimum for these parameters. One goodchoice for these parameters is the minimum. By using the minimum, you canensure that the component shapes are consistent when the parameters are setto the minimum values. A second choice would be to draw the shapes using thedefault values for parameters.Some components have part of their structure repeated several times based ona parameter value such as the number of gate fingers of a FET. On thesecomponents, draw only one copy of the shapes that will be repeated. The GCCrepeat control will create the others. You might have shapes that will optionallyappear if the repeat parameter is more than one. An example is a gateinterconnect that is used only if multiple gate fingers are drawn. Draw theseshapes as they would appear for a repeat of two. The GCC controls can deletethese for the case of a repeat of one. For repeats greater than two, the stretchcontrol can enlarge them or the repeat control can create extra copies of them.The origin for the drawing does not have to be at the final location. It is fairlyeasy to use the GCC move control to change the origin.

Ensure that you add pins on the drawing where pins are needed. Place them on the3.same layer as the shape for which they represent a connection.(Optional) Define edge and area ports. This is done as described under the Creating4.Fixed Artwork.Add the layout parameters to the design by choosing the File > Design Parameters5.menu to open the Design Parameters dialog box. Select the Parameters tab. Entereach parameter that will affect the layout. You do not need to add other parametershere. Make sure the default value is correctly entered and has the correct units orvalue (i.e. 20 µm or 20e-6, not just 20).Save your layout using the File > Save menu.6.Start adding GCC controls one at a time and test them.7.

Add a construction line and a control as described in Graphical Cell Compiler.Compile the GCC macro using the Tools > Macro > Compile menu.For the Model Name you can use the same name as will be used for thecomponent in the design kit.In the Library View in the ADS Main Window, select this component and placethe component in the second layout window.Test the GCC control by changing the parameter value that would affect thiscontrol.Go back and add the next control.

After adding all controls and testing the component you can copy the AEL macro into8.the design kit. It is located in the layout view of your cell with the name artwork.ael.Copy the AEL macro file into the _<design kit>_/circuit/artwork directory.The parameter list in your AEL macro only contains parameters that affect the layout.9.The AEL macro file must be edited to ensure all parameters that are defined in yourcomponent definition are in the AEL macro parameter list. The component definitionis located in one of the files in the <design kit>/circuit/ael directory. It is thecreate_item() function for the component you are working on.Open your AEL macro in the design kit. Search for pam_ <model name>. You shouldfind a AEL function definition and it will probably be the last function defined at theend of the file.Exampledefun pam_SampleKit_fet(N, Width)


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Add any parameter names that are not already there. Change the order of theparameters in the GCC AEL macro to match the order listed in the create_itemcomponent definition.After:defun pam_SampleKit_fet(model, Width, N)

Now follow the steps mentioned in Adding Your AEL Artwork to the Design Kit, to addthis GCC based AEL Macro to your design Kit.

FET Example Implemented using GCC

This example uses the Graphical Cell Compiler (GCC). The FET in FET Example usingGraphical Cell Compiler has two layout parameters, Width (Gate Width) and N (Number ofGates). The number of gates can have values of 2, 4, 6, or 8. The minimum gate width is20 µm.

The left component in FET Example using Graphical Cell Compiler is drawn with N = 2 andWidth = 20 µm. The left pin is the gate connection. The right pin is the drain connection.The top and bottom pins are source connections. The origin for the component will be thegate pin. There is an air bridge over the gates and air bridge metal that connects thelower source and upper source.

FET Example using Graphical Cell Compiler

The middle component in FET Example using Graphical Cell Compiler is drawn with N = 4and Width = 20 µm. The original 2 gates are 6 µm lower and a second pair of gates havebeen replicated 12 µm above the original 2 gates. Notice the left and right shapes grow toconnect the 4 gates and 2 sources. The air bridge metal grows to cover all source metal.

The right component in FET Example using Graphical Cell Compiler is drawn with N = 6and Width = 30 µm. The gates are now 30 µm wide, but notice that the air bridge overthe gates is centered but does not grow in width.

GCC Steps for FET example

Graphical Cell Compiler includes detailed information about the usage of GCC controls. Atutorial example is also provided. You should be familiar with this information beforeproceeding into the following example.A workspace showing the completed GCC design is located at:


73

$HPEESOF_DIR/examples/DesignKit/GCC_FET_wrkInitial Drawing shows the initial drawing of the component. It is drawn with N = 2 andWidth = 20 µm. The origin is located at the gate pin.

Initial Drawing

Step 1

This stretch control stretches and moves selected shapes that are on the right of the1.vertical construction line. The expression for Length of this control is "Width - 20e-6".The "-20e-6" is here because the initial drawing has a gate width of 20 µm. If Width= 30, the amount of stretch needed is only 10 µm.Control: Stretch

Direction: Right

Length: Width-20e-6


74

Step 2

This stretch control moves the air bridge structures to the right 1/2 the distance of1.the change in gate width.Control: Stretch

Direction: Right

Length: (Width-20e-6)/2.0

Step 3

This stretch control moves most of the component to the right. This allows the left1.shape (at the gate pin) to increase in size as N (Number of gate fingers) changes.


75

The stretching of the left shape takes place in Step 7 & 8. Notice that for N = 2 thiscontrol does nothing.Control: Stretch

Direction: Right

Length: ((N/2)-1)*(12e-6)

Step 4

NoteAll shapes except the left shape are selected. Selection is shown by complementing the border of theselected shape. When two shapes have edges that are at the same location, then two complements aredone which returns the selection color to the original color. Because of this, overlapping shapes mayappear to not be selected.

This stretch control moves the gate structure down for N = 4, 6, or 8. For N = 21.nothing happens.Control: Stretch

Direction: Below

Length: ((N/2)-1)*(12e-6)


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Step 5

NoteSome shapes immediately to the left of the gates are selected even though they do not appear to be.

This repeat control copies the gate structure upward for N = 4, 6, or 8. For N = 21.nothing happens.Control: Repeat

Direction: Perpendicular

Number: N/2

Distance: 24e-6


77

Step 6

NoteSome shapes immediately to the left of the gates are selected even though they do not appear to be.

This stretch control operates on the shapes that are stretched when N = 4, 6, or 8.1.The stretch works in both directions.Control: Stretch

Direction: Both

Length: ((N/2)-1)*(12e-6)*2


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Step 7

This stretch control moves a single vertex of the left shape at a 45-degree angle. This1.step and step 8 enlarges the shape related to the gate connection.Control: Stretch

Direction: Above-Right

Length: ((N/2)-1)*(12e-6)*sqrt(2)

Step 8

NoteThe other shapes have already been moved to allow room for this stretch. This was step 3.

This stretch control moves a single vertex of the left shape at a 45-degree angle. This1.step and step 7 enlarges the shape related to the gate connection.Control: Stretch

Direction: Below-Right

Length: ((N/2)-1)*(12e-6)*sqrt(2)


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Step 9

Step 9, 10, and 11 are similar to step 3, 7, and 8. This step moves the drain1.connection to the right.Control: Stretch

Direction: Right

Length: ((N/2)-1)*(12e-6)

Step 10

This stretch control moves a single vertex of the right shape at a 45-degree angle.1.This step and step 11 enlarges the shape related to the drain connection.


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Control: Stretch

Direction: Above-Left

Length: ((N/2)-1)*(12e-6)*sqrt(2)

Step 11

This stretch control moves a single vertex of the right shape at a 45-degree angle.1.This step and step 10 enlarges the shape related to the drain connection.Control: Stretch

Direction: Below-Left

Length: ((N/2)-1)*(12e-6)*sqrt(2)

Testing the Artwork


81

This section applies to fixed artwork and AEL macros created manually or by the GraphicalCell Compiler unless otherwise specified.

Interactive Testing

Start ADS

If you see an error while starting ADS, you either have a syntax error in an AEL file or amissing file that you are trying to load. The error message should provide enoughinformation to find the problem.

Probable files:

<design_kit_name>/circuit/ael/<component definition file>.ael

<design_kit_name>_/de/ael/boot.ael

<design_kit_name>_/de/ael/palette.ael

<design_kit_name>_/circuit/artwork/<AEL macro file>.ael

Insertion Test

Open a layout window in a workspace that contains the design kit.1.Select the palette for your design kit.2.If your component does not show up in the palette it may not have been specified inthe palette group for the layout windows in the<design_kit_name>/de/ael/palette.ael file.Select a component from the palette and insert it onto the layout window.3.If you get a message indicating that the component definition could not be located,there is probably a syntax error in the AEL function that specifies the create_itemfunction for the component.If a rectangular box with an X through it appears, your AEL macro did not get loaded.Check your <design_kit_name>/de/ael/boot.ael file.You might get an error in your <design_kit_name>/circuit/artwork/ <AEL macrofile>.ael. The error message should give the name of the AEL macro file, the linenumber of the error, and a reason for the error (i.e. divide by zero, etc.).

Viewing Detailed Instance Information

After inserting the component, select the component and choose Tools > Identify. Thiswill display the Identify dialog box with detailed instance information about thecomponent. Notice which mask layers are used by the component. Then check the angleand layer for each pin. Are they consistent with what you expected?

Measuring Distances

You can use the Insert > Measure menu to check the size of various shapes in yourcomponent.

Visibility of Layers

If your component has shapes on multiple layers, it may be useful to view only one or two


82

layers at a time. The Options > Layers Preferences menu displays the LayerPreferences dialog box that enables you to turn off or on the visibility of any layer orlayers.

Testing Parameters (AEL Macros Only)

Select the component and double click on it to change parameter values that affect theshapes. Do all parts of the component change as expected? You may need to change layervisibility and use the Insert > Measure menu to verify this.

Testing with Design Synchronization

Create a new schematic window and place a component to be tested in it.

Connect an MLIN component to each pin of the component. Edit the length and widthparameters of the MLIN components so that they are similar in size to the size of thelayout for your test component. You might want to make the width of each MLINcomponent different.

Use the Options > Preferences menu and the Pin/Tee tab to set the Pin Numbersvisibility on for the schematic view as shown in Schematic View.

Schematic View

Use the Layout > Generate/Update Layout menu. After the dialog box is opened,select one of the components to be the starting point for a generated layout and then clickOK in the dialog box. You should see a layout window with components in it.In the layout window use the Options > Preferences menu and the Pin/Tee tab to setthe Pin Numbers visibility on for the layout view. It should look similar to Layout Window.


83

Layout Window

For each component pin, compare the MLIN on the schematic to the MLIN in the layout. Iseach MLIN in the layout connected to the correct location on the component? Does theMLIN have the correct angle relative to your component? This should verify the pinnumbers and angles for the layout of your component are correct.

Adding DRC RulesCustom rules can be written for the ADS Design Rule Checker (DRC) and put into a designkit. The details of writing the rules are included in ADS Desktop Design Rule Checker. Thissection discusses the detail of integrating the rules into a design kit. A sample of DRCrules are provided in the directory:

$HPEESOF_DIR>/examples/DesignKit/SampleKit/drc/rules

The 'rules' Directory

DRC rules can be placed in any directory and be used; however, a specific directory isdefined for ADS DRC rules in a design kit. This directory is called:

<design_kit_name>/drc/rules

The rules Files

The DRC rules are written in AEL files(.ael). As you compile your rules files, a compiledAEL(.atf) version of these files is automatically created. Both the AEL and ATF files mustbe placed into the <design_kit_name>/drc/rules directory. You can name them anythingthat you want and have any number of different AEL/ATF sets of files.


84

The 'setrule' Registry File

A special AEL file called setrule.ael should also be placed in the <design_kit_name>/drc/rules_ directory. The format for this file is included in ADS Desktop Design RuleChecker. It enables the designer to choose which DRC rules file to use by selecting a oneline description of the rules instead of just browsing to the correct rules file when usingthe ADS Design Rule Checker. Both the setrule.ael and setrule.atf files should be placedinto the _<design_kit_name>/drc/rules_ directory.

NoteTo see how Layers and Purposes can be used in ADS2011 to enhance DRC, unzap and open the exampleworkspace ($HPEESOF_DIR>/examples/DesignKit/SampleKit/examples\SampleKit_Demo_wrk) and runthe Resistor Width Rules on the design SampleKit_DRC_Demo

Configuring Design Kit Components for use with ADSNetlist ExporterThe ADS Netlist Exporter tool can generate a netlist of an ADS schematic. The netlist canthen be used by third party Layout versus Schematic (LVS) tools to compare the ADSschematic to the extracted components from an ADS or third party layout editing tool. Totake advantage of this capability for designs built using a design kit, all appropriate designkit components in a design kit need to be configured, as described in Netlist ExporterSetup.

The ADS Netlist Exporter tool is already configured to look in the directory<design_kit_name>/netlist_exp for all files related to netlist export for each design kitthat has been added in the workspace.Configuration for the netlist exporter requires that one component definition be created foreach device in the design kit. The component definition files should be placed into thedirectory <design_kit_name>/netlist_exp/components/<tool>. Each LVS tool requires itsown individual component definition.

In addition to the component definitions, you may also place custom AEL code for aspecific tool into the file:

<design_kit_name>/netlist_exp/ael/<tool>/cnexNetlistFunctions.ael

This file will be loaded each time a netlist file is generated through the netlist exporter fora specific tool.

Files can also be set up to be automatically included by placing them into the directory<design_kit_name>/netlist_exp/include/<tool>. If you have subcircuit definitions thatmust be included for a specific tool (e.g. a subcircuit definition for a box component inDracula), those definitions should be placed into a file in the include directory.

It is also possible, but not recommended, to place tool configuration files into the directory<design_kit_name>/netlist_exp/config. If it is expected that certain global settings willneed to be changed for a particular tool, the tool configuration file can be copied into thedesign kit directory so that the new global settings will be used.


85

Additional Parts for ADS Design KitsThis section describes the ADS design kits additional parts that may be added to a designkit. The basic parts are described in Basic Parts of an ADS Design Kit. Using the additionalparts in a design kit provides extra functionality to a kit.

This section is further divided into two sections. The topics in the first section are coveredsufficiently that you should be able to implement the functionality in your design kit. Thetopics in the second section include a description of capabilities that the system has tooffer, but it is beyond the scope of this document to cover the capabilities in depth.Contact Agilent EEsof-EDA Solution Services organization for assistance in implementingthese features in your design kit.

Adding Simulation Data to a Design KitIn Basic Parts of an ADS Design Kit, you learned about supplying simulation data in theform of an included netlist file which contained model and parameter information. This isthe default format for an RFIC design kit. Design kits usese various Other methods ofsupplying simulation data which serve different technologies. These methods aredescribed in the following section.

S-Parameter and MDIF Data

ADS schematics includes components such as SnP, S2P, MDIF, and DataAccessComponent. These components point to external data files. The file browser on these componentsuses the DATA_FILES configuration variable in de_sim.cfg to find all data files in thatpath.

NoteIf you use the browser to locate the files, be sure to manually strip off the full path to the selected file.You do not want your customers to receive files with a hard-coded path to files on the machine where thedesign kit was developed.

During simulation, the simulator uses the USER/_SIM/_FILE/_PATH variable to find thedata files. USER/_SIM/_FILE/_PATH includes a reference to DESIGN_KIT_SIM_FILE_PATH.When a design kit is loaded, the circuit/data subdirectory under the design kit directory isautomatically added to the DESIGN_KIT_SIM_FILE_PATH path variable in hpeesofsim.cfg. Make sure the data file names are unique so that the simulator finds only one file withthe given name. It is recommended to prefix the filename with the name of the companyand/or process.

User Compiled Models

User-compiled models are distributed as dynamically linked libraries (.dll files on PC) orshared libraries (.sl or .so files on UNIX/SUN platforms). This is especially important fordesign kit developers and users because it enables the design kit user to access custommodels from multiple design kits simultaneously. To create a user-compiled model for adesign kit, use the schematic menu pick Tools > User-Compiled Model and theassociated User-Defined Models. Be sure to make your component name specific to yourdesign kit so it remains unique when used with other design kits.

When the model has been compiled into a dynamically linked library (with file extension.dll, .sl, or .so), copy it and the associated index file, deviceidx.db, from the currentworkspace to the bin/$SIMARCH$COMPILE_VER subdirectory of your design kit. Todetermine the proper subdirectory of bin, run the program hpeesofarch, which resides in


86

$HPEESOF_DIR/bin. Some examples of the subdirectories on the different platforms aresun64_sparc_SS12, linux_x86_GCC442, linux_x86_64_GCC442, win32_VS2008 or

win32_64_VS2008.

NoteIf a user-compiled model is generated using ADS in 64-bit mode, place the file in the appropriateplatform's _64 subdirectory. If it is not placed in the appropriate _64 subdirectory, then the user-compiledmodel will not work in 32-bit mode. Suffixes _SS12, GCC442 and VS2008 are defined according to thecompilers name and versions.

If you add more files to the directory, you must regenerate the index file by runninghpeesofsim -X in that directory. Also, if a design kit supports multiple platforms, such assun64 and linux_x86, the shared libraries and index file should be placed in bothsubdirectories of the bin directory. The files may be the exact same binary files if youhave tested them on both platforms and determined that the code is compatible.

User-compiled models do not require a license for the end user of the design kit, but theappropriate shared library/DLL environment variables must be set. For more informationon setting the shared library/DLL environment variables, refer to RefNets.

When a user enables a design kit with a dynamically linked user-compiled model, theproper design kit directory is added to the path variable EESOF_MODEL_PATH, which isread by the simulator from the simulator configuration file hpeesofsim.cfg to locaterequired custom models.

To complete your design kit, copy the workspace to each supported platform, regeneratethe dynamic library, and copy the files to the design kit.

Verilog-A Models

If there are any Verilog-A files that are needed in the design kit, place the files in theveriloga folder in the main design kit directory.

Parameter CallbacksA parameter callback is an AEL function that is executed automatically when a componentparameter is modified in the schematic editor. The function is provided by the design kitdeveloper but must contain the specified arguments and must return the exact value typethat is documented. The purpose of parameter callbacks is to provide a means ofcontrolling the value of component parameters that depend on the values of otherparameters of the same component. It is expected that you have at least a minimalunderstanding of programming terms to comprehend this section.

Adding a Callback to a Parameter Definition

Parameter callback functions are associated with individual parameters of a component bymeans of information in the call to create_parm() for the specific component's parameter.This is done by the addition of a optional callback list.

For example, a create_parm() call without a parameter callback function might read as:

create_parm("X", // parameter

"Unknown value", // label

PARM_REAL | PARM_STATISTICAL | PARM_OPTIMIZABLE, // attribute

"StdFormSet", // formset


prm("StdForm", "10.0") // default value

),

Examples of the create_parm() call without a parameter callback function are also given in


87

ADS Design Kit Tutorial.

The same parameter information with an associated parameter callback function mightread:

create_parm("X", // parameter

"Unknown value", // label




prm("StdForm", "10.0"), // default value

list( // callback list

dm_create_cb( // define callback function

PARM_MODIFIED_CB, // callback type

"cb_funct_name", // callback function name

"", // clientData

TRUE // callback enable

)

)

),

Parameter callback function information is incorporated into the call to create_parm() as alist() of calls to the function named dm_create_cb(). In the example here, there is onlyone such call to dm_create_cb(), but there could be multiple calls as separate entries ofthe list. This way, a parameter could be associated with a number of independent callbackfunctions.

The function dm_create_cb() takes four (4) arguments:

For parameter callback functions, the first argument must be PARM_MODIFIED_CB.This is the callback type.The second argument − a quoted string − is the name of the AEL function to beinvoked when the associated parameter is modified in the schematic editor.The third argument − called clientData − is passed to the callback function. Anexample of a use of this argument is included in Writing the Parameter CallbackFunction. This argument can be an empty string as shown above if there is no extrainformation to be passed to the callback function. The parameter data is passedautomatically.The fourth argument - TRUE or FALSE - is used to enable or disable the callbackfunction association.

For more information, see dm_create_cb(). The examples on the following pages will alsohelp you understand parameter callbacks.

Writing the Parameter Callback Function

The section above described how to add a parameter callback when creating a parameter.Now the actual callback function needs to be written. This is the AEL code that isautomatically executed when the component parameter is modified in the schematiceditor.

The function declaration has a predefined set of three arguments, cbP, clientData andcallData. The callData is used to access all parameters on the component so you can usethe values of one or more independent parameters to calculate the value of a dependentparameter. clientData is a string that was set when the callback was added to theparameter. The clientData string gives you the flexibility to define callback functions in acouple different ways.

The first method used to define callback functions is to have a separate function for eachparameter on a component. In this case, you might not need to set clientData at all. Whenit is being executed, the AEL function will always know which parameter was beingmodified when the callback was triggered.

The second method for defining callback functions is to have only one function for each


88

component. The advantage is that it combines all the code related to the component inone location. It also allows reuse of code, which makes it easier to maintain the code,since changing it in one place changes it for all cases. To use this method, you will need tosupply an identifier so the function knows which parameter is being modified. Thisidentifier is the string passed in as clientData.

The basic structure of a parameter callback function is shown below, with examples ofboth of these methods on the following pages.

defun cb_funct_name(cbP, clientData, callData)

{

decl dependentParmData = NULL;

//

// additional declarations

//

// and

//

// callback function code

//

return dependentParmData;

}

This structure should be used as a template, substituting an appropriate name forcb_funct_name and replacing the section marked as comments with parameterdeclarations and AEL code. Note that it is important to maintain the illustrated declaration,initialization, and return of the variable dependentParmData. Examples on the followingpages will clarify this.

NoteIt is OK to change the argument names or dependentParmData variable name, as long as it is doneconsistently throughout the function.

The arguments of the function are:

cbP - This is a pointer to the function itself. There will not be any reason to use thisargument.clientData - This can be any information in string format. It is set when the callbackis declared in the dm_create_cb() function.callData - This is the parameter information for the component being edited.Examples of how to access and modify the parameter values are given in thefollowing pages.

It is not necessary to understand the structure of this information, since access functionsare provided to extract information about specific parameters.

Callback Example - One Function per Parameter

As an example of a callback that is filled out and functional, consider a component(perhaps a subcircuit model) that has three parameters A, B, and C. Further, assume thatthe following relationships are to be established among these three parameters:

When the value of either parameter A or B is modified, the value associated withparameter C is to be adjusted so that it is equal to the sum of A and B;When the value of parameter C is modified, the values associated with parameters Aand B are to be adjusted so that they are each equal to C/2.

One way of programming these relationships is shown in the following AEL code. First is acode fragment shows part of the item definition AEL for the parameters of the component:

create_parm("A", // parameter

"A parameter value", // label






89




"a_modified_cb", // callback function name

"", // clientData


)

)

),

create_parm("B", // parameter

"B parameter value", // label








"b_modified_cb", // callback function name

"", // clientData


)

)

),

create_parm("C", // parameter

"C parameter value", // label








"c_modified_cb", // callback function name

"", // clientData


)

)

),

Next, suitable callback functions are:

defun a_modified_cb(cbP, clientData, callData)

{


decl a_mks = pcb_get_mks(callData, "A");

decl b_mks = pcb_get_mks(callData, "B");

dependentParmData = pcb_set_mks(dependentParmData, "C", a_mks + b_mks);


}

defun b_modified_cb(cbP, clientData, callData)

{




dependentParmData = pcb_set_mks(dependentParmData, "C", a_mks + b_mks);


}

defun c_modified_cb(cbP, clientData, callData)

{


decl c_mks = pcb_get_mks(callData, "C");

dependentParmData = pcb_set_mks(dependentParmData, "A", c_mks/2.0);

dependentParmData = pcb_set_mks(dependentParmData, "B", c_mks/2.0);


}

The three functions above are very similar. The third one, c_modified_cb(), will be used toprovide a line by line description of the details of code which retrieves and sets parametervalues. It is expected that the reader already understands basic programming concepts.

line 1: decl dependentParmData = NULL;dependentParmData is a variable that will be used to collect the new parameter values. Itmust be set to NULL to start with so no garbage gets attached to the component.

line 2: decl c_mks = pcb_get_mks(callData, "C");As described in the previous section, callData contains the starting values of all theparameters on the component. pcb_get_mks() is used to get the numerical value of anyparameter on the component. In this case, it is the value of C, which the user just set inthe schematic, which is being retrieved. It was the modification of this value in theschematic that caused this code to be executed, or triggered the callback.


90

The syntax for this function is:mksValue = pcb_get_mks(callData, paramName);

Where:

callData is the third argument of the callback function, if the callback is of typePARM_MODIFIED_CB.paramName is the name of the parameter to get the value from. This must be aquoted string.mksValue is the requested value, returned in MKS (unscaled) units.

line 4: dependentParmData = pcb_set_mks(dependentParmData, "A", c_mks/2.0);Note that dependentParmData is both passed into this function and returned from it. Itneeds to be reset because it is accumulating the values for the dependent parameters. Aand B are dependent on the value of C in this example.

The syntax for this function is:paramData = pcb_set_mks(paramData, paramName, value)

Where:

paramData is a structure containing parameter data. It is NULL the first time itis called. In addition to this variable being a parameter to this function, thevalue returned by this function must also be assigned to it.paramName is the name of the parameter to set the value of. This must be aquoted string.value is the new value in MKS (unscaled) units.

line 5: return dependentParmData;A callback of type PARM_MODIFIED_CB, which these are, must return the collectedparameter information, which is stored in dependentParmData.

The function pair pcb_get_mks() and pcb_set_mks() is aware of scale factors that havebeen associated with a parameter's value. That is, if a resistance is specified asR=1kOhm, then pcb_get_mks() returns a value of 1000.

Similarly, a value of 2000 supplied as the third argument of pcb_set_mks() for the sameparameter results in R=2kOhm.

Not all parameter values are numerical. In addition to pcb_get_mks() and pcb_set_mks(),there are two more function pairs that are used to retrieve and store values of componentparameters. The functions named pcb_get_form_value() and pcb_set_form_value() areused (respectively) to get and set values associated with constant formsets. For moreinformation, refer to Forms and Formsets.

Similarly, string data can be retrieved and set using pcb_get_string() andpcb_set_string(). Arguments of these four functions exactly parallel those forpcb_get_mks() and pcb_set_mks() except that no scaling rules are applied. For moreinformation on these functions, refer to Utility Functions for AEL.

Callback Example - One Function per Component

Another way to program the above example makes use of the clientData field as a switchto select different logic within a single function. First, the item definition AEL code isrevised as:

create_parm("A", // parameter

"A parameter value", // label









91

"abc_modified_cb", // callback function name

"", // clientData


)

)

),

create_parm("B", // parameter

"B parameter value", // label









"", // clientData


)

)

),

create_parm("C", // parameter

"C parameter value", // label









"", // clientData


)

)

),

Next, the logic of the above three callback functions is combined into a single function.The value of the clientData is compared (strcmp) to A, B and C and the logic for A and Bcan be combined. This means if the value of either A or B is modified, the dependentparameter C is recalculated, but the code only needs to be provided once in the callback,as opposed to the previous example where it was provided separately for each parameter.

defun abc_modified_cb(cbP, clientData, callData)

{


if((strcmp(clientData, "A") == 0) ||(strcmp(clientData, "B") == 0))

{



dependentParmData = pcb_set_mks(dependentParmData,"C", a_mks + b_mks);

}

else if(strcmp(clientData, "C") == 0)

{

decl c2_mks = pcb_get_mks(callData, "C")/2.0;

dependentParmData = pcb_set_mks(dependentParmData, "A", c2_mks);

dependentParmData = pcb_set_mks(dependentParmData, "B", c2_mks);

}

else

fputs(stderr, "Illegal clientData value);


}

Using Parameterized Components in Optimization

If any (or all) of the parameters of a component have associated modified parametercallback functions in the design environment AND these parameters are to be optimized,then the same relationships between the parameters must be included in the model code.That is, the design environment does not automatically enforce these relationships in thesimulation environment during optimization (The relationships will, however be enforced inthe display of components in a design when optimization variables are updated.) It maybe desirable to restrict the optimizability of some parameters.

Developing and Testing Modified Parameter Callback Functions


92

As instructed in the tutorial, parameter callbacks should be included in the AEL file thatholds the item definition for the associated element. In the tutorial, this file was calledsample_fet.ael. For more information, refer to Modifying the Item Definition File.

Also, note that if the modified parameter callback function is being added to the AEL for auser-compiled model, this (AEL) file is subject to being overwritten by the designenvironment if any modifications are made therein. Keep a backup copy to put thecallback information back in place as needed. You may need to reload the element AEL byentering load("..."); at the design environment command line (in the ADS Main windowunder Tools > Command Line).

Limitations of Parameter Callbacks

Reference to data access components is not supported for elements that haveparameters with modified parameter callback functions. A message is written tostderr if such a reference (PARM=file{...}) is made.The modified parameter callback functions may be confused about unit scale factorswhen the right hand side of a parameter assignment involves an expression.Modified parameter callback functions do not modify dependent parameter valuesthat are either variables or expressions.The AllParams parameter (that is used on model data items) is ignored.There is currently no support for tuning, sweeping, optimization, back annotation,device operating point, etc.Parameter callbacks cannot use variable, they must be constants.

Netlist CallbacksA parameter callback, described in the previous section, is a piece of AEL code that isexecuted when a parameter is modified on the schematic. A netlist callback is similar, butthe AEL code for a netlist callback is executed when a schematic is netlisted for simulation.A netlist callback is defined for a component on the create_item() statement. Mostcomponents will not require a netlist callback. They can use the predefined netlisting rulesfor a general component or a component with a model, as explained in Item Definition. Ina design kit, a netlist callback is typically used for the process include component, asdefined in Netlist Include or Process Component.

A netlist callback is defined by the function dm_create_cb(). This function was definedabove in Adding a Callback to a Parameter Definition. The only difference is that instead ofPARM_MODIFIED_CB, the callback type for a netlist callback is ITEM_NETLIST_CB.

An example of a netlist callback is included in the Adding a Netlist Include Component. Itis hard-coded to output the #include statement with the proper filename as determinedfrom the design kit variables. The #include statement is described in The #include Pre-processor Command. It can also output the #define statement used to enable a specificcorner case, also described in The #ifdef and #define Pre-processor Commands. Theexample from the tutorial is included here with more explanation.

create_item("SAMPLE_NETLIST_INCLUDE",

...

list(

dm_create_cb(

ITEM_NETLIST_CB, //callback type

"SAMPLEKIT_process_netlist_cb", // callback function name

"", // clientData


)

)

);

A part of the create_item() statement is shown above. Note that most of the arguments


93

were omitted for this example. The callback information is a list, inserted before the list ofcomponent parameters. There are no parameters on this component. The list contains oneor more calls to dm_create_cb(). The arguments to dm_create_cb() are:

The first argument is the callback type. It must be ITEM_NETLIST_CB for a netlistcallback.The second argument is the function name. This is the AEL code that will be executedduring netlisting when this component is encountered in the schematic.The third argument is called client data. This is a string that may contain anyinformation that you would like to use in the code. For this example, no client data ispassed.The fourth argument is set to TRUE or FALSE and is used to enable or disable thecallback.

Part of the actual callback code is shown below.

defun SAMPLEKIT_process_netlist_cb (cbP, clientData, callData)

{

decl net="";

decl modelFileList;


modelFileList = get_dir_files(SAMPLEKIT_CIRCUIT_MODELS_DIR, "net");


{


SAMPLEKIT_PATH, car(modelFileList)));


}

return(net);

}

The arguments on the function are different than the arguments to dm_create_cb() whenthe callback was created. The callbacks on a callback of type ITEM_NETLIST_CB willalways be the following:

cbP - a pointer to the function, not needed for this example.clientData - a string defined in dm_create_cb() and passed in for reference. Also notneeded for this example. The parameter callback example in Callback Example - OneFunction per Component provides an example of how to use a clientData string.callData - also not needed for this example. Again, the parameter callback examplesearlier in this section make use of these parameters.

For this example, the global path variable SAMPLEKIT_CIRCUIT_MODELS_DIR, which wasset in boot.ael, is used to build the path to the model files. Then it is formatted into astring starting with the #include pre-processor statement. Finally the value net isreturned to the calling function. This is the string that is output to the netlist. A morecomplex example of a netlist callback, which includes the use of forms and formsets, isshown in Example Process Component with Forms and Formsets.

Creating Design Kit DocumentationAll design documentation should be saved in the /doc subdirectory of the design kitdirectory. The documentation that you are recommended to provide in The about.txt Fileand Providing Basic Documentation is a very basic summary of the design kit which isintended to be presented in a standard design kit.

More comprehensive documentation, such as detailed component information, can also beprovided in the form of HTML files. This documentation can be added into the ADSdocumentation set by the initial design kit developer or the end user of the design kit.There are two tools available in Advanced Design System which can help you create yourdocumentation.

The ADS Electronic Notebook can help you generate your html documentation.


94

The DesignGuide Developer Studio can help you generate the help server index filerequired to access the html documentation.

Adding Help for Components

If you have a design kit and you want to include comprehensive documentation for yourcomponents, a new subdirectory with your HTML documentation should be added into thedesign kit doc directory. Within the doc directory, you will also need to create a helpserver index file called, hs <bookName> _index. This file contains a component help topicstring for each entry that points to a specific documentation file.

To start building your component help documentation:

Create a new subdirectory for your component documentation under your design kit1.doc directory. For example:cd $HOME/SampleKit/doc

mkdir component_doc

Create the HTML documentation for your component and save your files in the new2.directory. For example, if you have a component called sample_res, save yourdocumentation file as:$HOME/SampleKit/doc/component_doc/sample_res.html

Create a help server index file and save your file under your design kit doc directory.3.For steps on creating the help server index file, refer to Creating a Help Server IndexFile. The help server index file might be saved as something like:$HOME/SampleKit/doc/hsSampleKit_index

Launch ADS, enable your design kit, and test your component help.4.Place an instance of your component on a schematic or layout.Double-click the component to launch the ADS Edit Component dialog box.Click the Help button in the Edit Component dialog box. Your documentationshould now be displayed in your browser window.

Finally, it is possible to add tag names in your HTML files in order to jump to specifictopics within your documentation. Because this makes the process somewhat morecomplex and more difficult to troubleshoot, it is not recommended.

Adding Help for Custom Design Kit Menus

One form of documentation that you may want to add to your design kit is help that canbe accessed from a custom design kit menu. For more information on custom menus,refer to Adding Custom Menus to ADS.

To start building your custom help documentation:

Create a new subdirectory for your documentation under your design kit doc1.directory. For example:

cd $HOME/SampleKit/doc

mkdir menu_doc

NoteThe SampleKit in ADS has the help files for menus present in the doc directory itself.

Create the HTML documentation for your design kit and save your files in the new2.directory. For example, if you have created menu_doc, save your documentation fileinside menu_doc directory only.


95

NoteImages in a form such as a .gif file which are used in the html page should be saved in the samedirectory.

Create a help server index file and save your file under your design kit doc directory.3.For steps on creating the help server index file, refer to Creating a Help Server IndexFile. The help server index file might be saved as something like:

$HOME/SampleKit/doc/hsSampleKitMenu_index

NoteYou can have multiple help server index files in your design kit doc directory. Each indexfile must be in the form hs_<bookName>_index and have a unique _<bookName>.

Add a call in the menu callback AEL function of your help menu to call the appropriate4.help page. For example:de_invoke_help("SampleKitMenu", "Schematic");

For more information, see de_invoke_help().Launch ADS, enable your design kit, and test your custom help. Select your custom5.help menu item. Your documentation should now be displayed in your browserwindow.

Creating a Help Server Index File

The help server index file is used to map the help calls to the appropriate documentationfiles. The help server index filename must be in the form:hs <bookName> _index

where <bookName> is a unique name created for your design kit documentation. Forexample, your help server index file might be saved as something like hsSampleKit_index.

The help server index file can be created as a simple text file using any text editor. Whenconstructing your index file, you can add comments to the file by including a '#' characterat the beginning of each line of commented text (see Example below).

You can think of the help server index file as having two columns of information for eachrow or entry:

The first column on the left-hand side is the help topic string (<topicString>)followed by a single space, a " ! " delimiter, and another single space.The second column on the right-hand side defines the relative path from the helpserver index file to the html file to open for that particular topic string(<bookName>/<topicString>.html !). This column is also followed by a single spaceand a " ! " delimiter.

So a single entry in the help server index file would look something like this:<topicString> ! <bookName>/<topicString>.html !

Notice in the example below that the name of the component for component help isactually the topic string.

Example

# Name: SampleKit

# Version: 1.0

sample_res ! component_doc/sample_res.html !

SAMPLE_NETLIST_INCLUDE ! component_doc/SAMPLE_NETLIST_INCLUDE.html !

sample_fet ! component_doc/sample_fet.html !

Alternatively, you can create your help server index file using the DesignGuide DeveloperStudio in ADS. To access this tool:

Choose DesignGuide > DesignGuide Developer Studio > Start DesignGuide1.


96

Studio. The DesignGuide Developer Studio dialog box appears.Choose Tools > System Help Editor. The System Help Editor dialog box appears.2.

Use the System Help Editor to create your hs<bookName>index file. For moreinformation, refer to _"Using the System Help Editor" in the "DesignGuide DeveloperStudio" documentation.

Detecting the Help Server Index Files

After adding your html files and your help server index file(s) to your design kit docdirectory, you will need to restart ADS to test your documentation. The design kitinfrastructure code automatically detects any help server index file(s) in any added designkit doc directories. The software then defines two variables based on the content of the hs<bookName> _index file(s).

DESIGN_KIT_DOC_PATH - This variable identifies the path to the design kit's docdirectory. For example:DESIGN_KIT_DOC_PATH = <path to design kit>/SampleKit/doc;

DESIGN_KIT_BOOKNAMES - This variable identifies the name of the book(s) foundwithin the doc directory. For example:DESIGN_KIT_BOOKNAMES = SampleKit;

These two variables are then combined and added to the file$HOME/hpeesof/config/hpeesofhelp.cfgThe DESIGN_KIT_DOC_PATH and DESIGN_KIT_BOOKNAMES variables are used bythe two other variables in the ADS installation's$HPEESOF_DIR/config/hpeesofhelp.cfg file, LOCAL_DOC_PATH andLOCAL_BOOK_NAMES. These two variables are set in the hpeesofhelp.cfg file atinstallation as follows:LOCAL_DOC_PATH = {%DESIGN_KIT_DOC_PATH}LOCAL_BOOK_NAMES = {%DESIGN_KIT_BOOKNAMES}

Layers and Preferences FilesThe de/defaults directory of an ADS installation includes default preference (*.prf) files forthe schematic and layout windows. These files have names such as schematic.prf,layout.prf . Additional preferences files are included for different schematic units, such asmm, mil and µm. The configuration variable in de.cfg which is used by ADS to determinewhere the preferences files should be read from is:

PREFERENCES_DIR - When a new workspace is created in ADS, the default layersand preferences files are copied from this location, unless specified otherwise. Theuser also has the option to use his kit's preferences for some values that are markedwith a * in the Options > Preferences dialog box. The other preferences, if notfound in the kit, are taken from the workspace defaults.

Design kits may provide layers and preferences files so that their components look thesame as when they were created. These files should have the default names of tech.db,display.tech, library.tech, layout.prf and schematic.prf and be placed in your design kit<design_kit_tech_lib_name> directory (<design_kit_lib_name> directory for the .prffiles). Your design kit documentation should describe what settings from these files areimportant so that the end user can make a decision on how to use them during the designprocess.

After adding a design kit with technology files, the end user can select a specific design kitto be used as the source for the library's design technology files when creating a newlibrary, as each library in a workspace can have a unique technology. The end user canalso use the Options > Technology menu to update the technology source files in theworkspace and set the default technology source for any new libraries in the workspace.


97

Adding Custom Fill Patterns to a Design KitTo supply custom fill patterns with a design kit, follow the steps below.

Make a directory in the design kit called de/fill_patterns. Save all custom fill patterns1.in this directory. For an example of the syntax of a fill pattern file, refer to thesupplied files in $HPEESOF_DIR/de/fill_patterns. Fill patterns are specified in Xbitmap format.Make a directory in the design kit called config and save a file called hpeefill.cfg. The2.path to each fill pattern should start with a variable reference to the design kit path,such as {%SampleKit_PATH}/de/fill_patterns/chain01.pattern : 3 35 60. Refer to FillPattern Configuration, hpeefill.cfg.Add 2 lines to de/ael/boot.ael in the design kit:3.setenv("SampleKit_PATH", SampleKit_PATH, "hpeesof",

ASTR_ENV_SAVE_HOME,TRUE);

setenv("HPEESOF_FILL", "{%SampleKit_PATH}/config/hpeefill.cfg", "hpeesof",

ASTR_ENV_SAVE_HOME,TRUE);

SampleKit_PATH should have been set already by a call such as this:decl SampleKit_PATH = expandenv(designKitRecord[1]);

Restart ADS and then the proper fill patterns will be loaded.4.

When you add the design kit, it will define SampleKit_PATH and HPEESOF_FILL inhpeesof.cfg in $HOME/hpeesof/config. When you open a workspace, the system will re-read hpeesof.cfg, but unfortunately it will not re-read hpeefill.cfg or the fill patterns itreferences. You must start ADS with those variables set for it to have those fill patternsloaded when you open the workspace. There are other parts of a design kit that do not getinitialized properly until ADS is restarted so some users do this automatically the first timeanyway.

The risk with this approach is that if somebody has already defined HPEESOF_FILL inhpeesof.cfg in their workspace directory, that value will take precedence. This might alsobe the case if they set it in a startup directory, sometimes used on unix. To see if thesystem has recognized the new value, you can enter the following command using Tools> Command Line in the main ADS window:de_info(identify_value(getenv("HPEESOF_FILL", "hpeesof")));

Or, use Tools > Configuration Explorer in the main window. We are using thisapproach with many other configuration variables to add functionality from a design kitinto ADS and it is working very well so far.

Other limitations to be aware of:

The system only recognizes one fill pattern file at a time and a design file or layers1.file has no connection to the file by name, only by positional index number. Anhpeesof.cfg file could be set up in a workspace directory to allow differentworkspaces to use different fill pattern files, but ADS must be restarted for the fillpattern index file and the associated fill pattern files to be read.

Advanced TopicsThe topics in the remainder of this section are included to give you a preview of more ofthe capabilities that Advanced Design System has to offer. It is beyond the scope of thisdocument to cover them in depth at this time. In some cases, references are given toother ADS documentation which will give you more information on the topics. You can alsocontact Agilent EEsof-EDA's Solution Services organization for assistance in implementingthese features in your design kit.


98

Expressions

A design kit can include expressions for data processing before simulation or aftersimulation. In ADS, a VAR component can be placed in schematic and expressions can beattached to it which will be evaluated before simulation. A MeasEqn component can beplaced in an ADS schematic and expressions attached to it will operate on data generatedduring simulation. This type of expression can also be entered directly onto a data display.

Add your AEL expression functions to a file named dk_defined_fun.ael in your design kit'sexpressions/ael directory. When a user loads the design kit, the design kit'sexpressions/ael/dk_defined_fun.ael file will be automatically tied into the appropriateplaces in the schematic or data display windows.

Templates

ADS supports two types of templates - simulation templates and data display templates. Asimulation template can facilitate setting up common simulations and a data displaytemplate can contain a standard set of plots that can be used in different workspaces.A design kit can include templates for simulation or for data display. Both tools in ADShave a menu pick Save As Template (data display) or Save Design As Template(schematic) . Save a template that is designed specifically for use with your design kit andstore it in the circuit/templates directory.

When a user loads the design kit, the appropriate path variable will be extended to includethe design kit template directory and the templates will be available to users of yourdesign kit. The Path to Templates in the design kit is defined by the variablesTEMPLATES_DIRECTORY and DDS_TEMPLATE_DIRECTORY in the eesof_lib.cfg file.

The default value of TEMPLATES_DIRECTORY is the circuit>templates>library in thedesign kit, so before you save any templates, you must create a new library(using File >New > Library), named library in circuit>templates folder and then save your designtemplates in that library.However the data display templates can be saved in the circuit > Templates folder itself.

This path variable is DESIGN_KIT_TEMPLATE_BROWSER_PATH and it is referenced byHP_TEMPLATE_BROWSER_PATH in hpeesofbrowser.cfg. For more information ontemplates, refer to Using a Template in Your Display.

Adding Custom AEL

There are times when a design kit developer may choose to include additional functionalityin a design kit in the form of custom AEL code. The best way to load a custom AEL file isto have it loaded from the boot.ael file when a design kit is loaded. Other methods whichmight involve modifying configuration variables are not recommended. Your design kitshould be easily distributable, so all files should reside in the design kit directory structureand no manual steps should be required of the end user.

Custom AEL files can be stored in the de/ael directory or the utilities directory. Thelocation should be known by the boot.ael file so it can load the files with the full path.

To protect your AEL code, you can ship your design kit with the .atf files only. The .atf filesare compiled versions of the AEL code. This will prevent users from modifying the codeand the behavior of your kit. It should not be relied on as a form of security.

Adding Custom Menus to ADS


99

Adding custom design kit menus to Advanced Design System can be done automaticallyby using two design kit infrastructure functions dk_register_menu_name() anddk_register_menu_function(). These two functions enable you to register your menus withthe design kit infrastructure code. Once your menu items are registered in a design kit,the software will add your design kit menus to ADS when the design kit is added andremove them when the design kit is removed.

dk_register_menu_function() accepts the name of an ael menu function that is created bythe design kit developer. This ael menu function is called whenever an ADS Main,Schematic or Layout window is ready to have menus added to it.Example call:// Name of AEL menu creation function provided by the design kit

dk_register_menu_function ( "SAMPLEKIT_add_custom_menus" );

dk_register_menu_name() accepts a window type (i.e. MAIN_WINDOW,SCHEMATIC_WINDOW, or LAYOUT_WINDOW) and menu name, or list of menu names, asparameters. This identifies which menus to remove when a design kit is disabled.

Example calls:

// Takes a list of menu names for that window type

dk_register_menu_name ( MAIN_WINDOW, list("SampleKit", "About SampleKit"));


dk_register_menu_name ( SCHEMATIC_WINDOW, list("SampleKit", "About SampleKit Schematic"));

// Takes one menu name for that window type

dk_register_menu_name ( LAYOUT_WINDOW, "SampleKit");

// Takes one menu name for that window type

dk_register_menu_name ( LAYOUT_WINDOW, "About SampleKit Layout");

The following method is recommended for enabling a design kit to automatically addcustom menus to ADS.

Create the file de/ael/ menu.ael. This AEL file will include all of your menu1.information. The Example menu.ael: defines a menu function that will handle thecreation of the menus and that will call the dk_register_menu_function() anddk_register_menu_name() functions to enable the design kit infrastructure toautomatically load and unload the design kit menus when it is added and removed.Modify the file de/ael/ boot.ael to load the menu.ael file (see Example boot.ael:).2.

Example menu.ael:

// Example Menu callback function taken from SampleKit

// --------------------------------------------------------

// CREATE MENU FUNCTION TO HANDLE MENU CREATION BASED ON

// WINDOW TYPE

// --------------------------------------------------------

// Callback function for SampleKit menu

defun SampleKit_sch_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Schematic");

}


defun SampleKit_lay_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Layout");

}


defun SampleKit_main_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Main");

}

defun SAMPLEKIT_add_custom_menus(winType)

{

if (winType == MAIN_WINDOW)

{

decl mainMenuH, mainMenuPickH;

// If main menu doesn't already exist, create it.

if (!(mainMenuH = api_find_menu(NULL, "SampleKit")))

{

mainMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Main Menu"

,API_MA_TEAROFF


100

,NULL

);

if (mainMenuH) api_add_menu(NULL, mainMenuH);

}

// If main menu, nested menu doesn't exist, create it.

if (!(mainMenuPickH = api_find_menu(mainMenuH, "About SampleKit")))

{

mainMenuPickH = api_create_menu("About SampleKit"

,"About SampleKit"

,"SampleKit_main_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (mainMenuPickH) api_add_menu(mainMenuH, mainMenuPickH);

}

// Display main menu

api_menu_manage(mainMenuH, TRUE);

api_menu_manage(mainMenuPickH, TRUE);

}

else if (winType == SCHEMATIC_WINDOW)

{

decl schematicMenuH, schematicMenuPickH;

// If schematic menu doesn't already exist, create it.

if (!(schematicMenuH = api_find_menu(NULL, "SampleKit")))

{

schematicMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Schematic Menu"

,API_MA_TEAROFF

,NULL

);

if (schematicMenuH) api_add_menu(NULL, schematicMenuH);

}

// If schematic menu, nested menu doesn't exist, create it.

if (!(schematicMenuPickH = api_find_menu(schematicMenuH, "About SampleKit Schematic")))

{

schematicMenuPickH = api_create_menu("About SampleKit Schematic"

,"About SampleKit Schematic"

,"SampleKit_sch_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (schematicMenuPickH) api_add_menu(schematicMenuH, schematicMenuPickH);

}

// Display schematic menu

api_menu_manage(schematicMenuH, TRUE);

api_menu_manage(schematicMenuPickH, TRUE);

}

else if (winType == LAYOUT_WINDOW)

{

decl layoutMenuH, layoutMenuPickH;

// If Layout menu doesn't already exist, create it.

if (!(layoutMenuH = api_find_menu(NULL, "SampleKit")))

{

layoutMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Layout Menu"

,API_MA_TEAROFF

,NULL

);

if (layoutMenuH) api_add_menu(NULL, layoutMenuH);

}

// If Layout menu, nested menu doesn't exist, create it.

if (!(layoutMenuPickH = api_find_menu(layoutMenuH, "About SampleKit Layout")))

{

layoutMenuPickH = api_create_menu("About SampleKit Layout"

,"About SampleKit Layout"

,"SampleKit_lay_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (layoutMenuPickH) api_add_menu(layoutMenuH, layoutMenuPickH);

}

// Display Layout menu

api_menu_manage(layoutMenuH, TRUE);

api_menu_manage(layoutMenuPickH, TRUE);

}

}

// Name of AEL menu creation function provided by the design kit

dk_register_menu_function("SAMPLEKIT_add_custom_menus");


dk_register_menu_name(MAIN_WINDOW, list("SampleKit"

,"About SampleKit"

));

dk_register_menu_name(SCHEMATIC_WINDOW, list("SampleKit"


));

dk_register_menu_name(LAYOUT_WINDOW, list("SampleKit"


));


101

Example boot.ael:

/*----------------------------------------------------------------------------+/

FILE : boot.ael

This file controls the loading of the design kit.

The value of variable designKitrecord is picked up from the eesof_lib.cfg

/+----------------------------------------------------------------------------*/

// Read values from eesof_lib.cfg file.

decl SAMPLEKIT_NAME = designKitRecord[0];


decl SAMPLEKIT_BOOT = designKitRecord[2];

decl SAMPLEKIT_VER = designKitRecord[3];

// These path names may be used later to load other files.

decl SAMPLEKIT_CIRCUIT_AEL_DIR = strcat(SAMPLEKIT_PATH, "circuit/ael/");

decl SAMPLEKIT_CIRCUIT_BITMAP_DIR = strcat(SAMPLEKIT_PATH,

"circuit/bitmaps/");

decl SAMPLEKIT_CIRCUIT_ARTWORK_DIR = strcat(SAMPLEKIT_PATH, "circuit/artwork/");

decl SAMPLEKIT_DE_AEL_DIR = strcat(SAMPLEKIT_PATH, "de/ael/");

decl SAMPLEKIT_DRC_RULES_DIR = strcat(SAMPLEKIT_PATH, "drc/rules/");

decl SAMPLEKIT_CIRCUIT_MODELS_DIR = strcat(SAMPLEKIT_PATH, "circuit/models/");

fprintf(stderr, "Loading %s design kit\n", SAMPLEKIT_NAME);

/*--- AEL files to be loaded at boot time ----------------------------------*/

load(strcat(SAMPLEKIT_PATH, "/de/ael/palette"));

load(strcat(SAMPLEKIT_PATH, "/circuit/ael/sample_res"));

load(strcat(SAMPLEKIT_PATH, "/circuit/ael/sample_fet"));

load(strcat(SAMPLEKIT_PATH, "/circuit/ael/SAMPLE_NETLIST_INCLUDE"));

load(strcat(SAMPLEKIT_PATH, "/circuit/artwork/sample_res_art"));

load(strcat(SAMPLEKIT_PATH, "/circuit/artwork/sample_fet_art"));

load(strcat(SAMPLEKIT_DE_AEL_DIR, "menu"));

//See boot.ael of SampleKit for the complete code.

NoteThe USER_MENU_FUNCTION_LIST function is not available in ADS 2011 and later. You need to use thecommands described above for adding menus to design kits.

The RF IP Encoder and Design Kits

Adding an encoded library to your design kit enables you to share a design while providingsome level of protection for your intellectual property. The RF IP Encoder enables you toautomatically generate a file structure that is supported by the design kit infrastructure.This file structure can contain an encoded library with multiple parts.When you select one of the design kit encoding formats in the RF IP Encoder userinterface, a directory structure similar to the one shown in Encoded Library DirectoryStructure is automatically generated. You can use this information to help you merge therequired sections for your encoded library into an existing design kit. It is recommendedthat you have some knowledge of encoding designs using the RF IP Encoder and arefamiliar with the design kit file structure.

Merging an Encoded Library into a Design Kit

If you want to include an encoded component, model, or library in an existing design kit:

Encode your intellectual property. While using the RF IP Encoder to encode your1.component, model or library:

Note the name that you define in the Library Name field of the Create EncodedLibrary dialog box. Also note the path that you define in the Destination Pathfield. This information will be used later in this process.Select the Design Kit with no .zip file option provided in the Create EncodedLibrary dialog box.For detailed information on using the RF IP Encoder or the encoding process,refer to the RF IP Encoder documentation.

You should now have an encoded library directory structure similar to the one shown2.in Encoded Library Directory Structure. This structure is created under the directorythat you defined in the Destination Path field of the RF IP Encoder's Create EncodedLibrary dialog box.


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Encoded Library Directory Structure

Directories Subdirectories Files Description

circuit/ ael/ <libraryname>_encode_item.ael

create_item() definition

<libraryname>_encode_def.ael

Palette definition

bitmaps/pc* <prefix>_<item>.bmp Component bitmap

bitmaps/unix* <prefix>_<item>.bmp Component bitmap

config/ ADSlibconfig #uselib lookup table

data/ *.ds unencodedsimulation/measurements

*.s2p unencoded Touchstone S-parameter files

*.cti unencoded CITIFILE files

models/ *.library encoded library part

records/ <prefix>_<lib>.ctl control file

<prefix>_<lib>.rec record file

symbols*/ SYM_<prefix>_<item>.dsn Not required in ADS2011

<design_kit_lib>/ <cell_name>/symbol/ master.tag, symbol.oa ADS internal files. Not to beedited by user.

tech.db Technology database file. Not tobe edited by user.

.oalib ADS internal files. Not to beedited by user.

eesof_lib.cfg Contains environment variables

<design_kit_lib_tech>/ tech.db Technology database file

.oalib ADS internal files. Not to beedited by user.

de/ ael/ boot.ael loads circuit/ael files

design_kit*/ ads.lib Not required in ADS2011

doc/ about.txt contains revision data enteredfrom the RF IP Encoder userinterface.

* Note that these directories are no longer required in ADS2011. All the bitmaps candirectly be copied into bitmaps directory, separate pc and unix directories are no longerrequired.

Using your encoded library and the information provided in Encoded Library DirectoryStructure:

Copy any *.ael files into your <design_kit_name>/circuit/ael directory. These files1.contain the item definitions and de_define_palette_group() calls for each component.For more information, refer to Item Definition.Copy any circuit bitmap files into the appropriate <design_kit_name>/circuit/bitmaps2.directory if you want your components to be available from the component palette.Ensure that the variable name used to get the bitmap path in the<prefix>_<def>.ael file is the same as you were using in your design kit. For moreinformation, refer to the section on Bitmaps.If you do not already have an existing ADSlibconfig file in your design kit, copy the3.ADSlibconfig file from your encoded directory structure into your design kit's<design_kit_name>/circuit/config/ directory. If you already have an existingADSlibconfig file in your design kit, open your <design_kit_name>/circuit/config/ADSlibconfig file in a text editor and append the information providedin your encoded libraries circuit/config/ADSlibconfig file. Save the new<design_kit_name>/circuit/config/ADSlibconfig file.Copy any data files such as *.ds, *.s2p, and *.cti files into your <design_kit_name>4./circuit/data directory if you want to provide optional ways to define your simulationdata. For more information, refer to Adding Simulation Data to a Design Kit.


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Copy your encoded library file (<encoded_lib>.library) into <design_kit_name>5./circuit/models/ <encoded_lib>.library, where <encoded_lib> is the name that youdefined in the Library Name field of the Create Encoded Library dialog box of the RFIP Encoder user interface.Copy any control and record files (*.ctl and *.rec) into your <design_kit_name>6./circuit/records directory if you want your design kit components to be available fromthe library browser. For more information, refer to Library Browser.Create symbol view for each encoded design into your <design_kit_name>7./<design_kit_lib> directory. The name of the cell for a component needs to be sameas that mentioned in the item definition in the <prefix>_<item>.ael file.Alternatively, you could change the name in the item definition to match the name ofthe cell that you are creating for this component.Open your <design_kit_name> /de/ael/boot.ael file in a text editor and append the8.load statements provided at the bottom of the boot.ael file of your encoded library.These commands are used to load the circuit/ael files. You will also need to copy thefollowing path variable just before the appended load statements and assign it toyour design kit path variable.decl <encoded lib path> PATH = _<design kit> _PATH;Where:

<encoded lib path>_PATH is the path variable used in your load statementsand <design_kit>_PATH is the path variable used in your boot.ael file.

For more information on the boot.ael file, refer to Creating the boot.ael File.

NoteYou may also need to redefine your palette group ael files in order to display your encodedcomponents in the design kit palette.

Open your <design_kit_name>/doc/about.txt file in a text editor and append any9.documentation and revision information supplied with your encoded library. For moreinformation, refer to The about.txt File.After copying all of the files to the appropriate location, it is recommended that you10.restart Advanced Design System to ensure that all of the new files are recognized.

Including an Encoded Netlist Fragment in a Design Kit

The information in this section assumes that you are using the NetlistInclude componentto reference models that are needed for simulation.

The RF IP Encoder enables you to encode your netlist model fragment, and with a minormodification to the netlist file, reference the encoded netlist.

Example

For this example, it is assumed that your circuit uses a NetlistInclude component thatreferences a netlist fragment called fet1.net. Using the RF IP Encoder:

Encode fet1.net with a library name of NETLIB. For this example, select the Design1.Kit with no .zip file option provided in the Create Encoded Library dialog box of the RFIP Encoder.The output of the RF IP Encoder will contain the encoded netlist fragment in a filecalled NETLIB.library. This file is located in the NETLIB/circuit/models/ directory asdescribed in Encoded Library Directory Structure.Move the file NETLIB.library into your <design_kit_name> /circuit/models/ directory.2.Using a text editor:3.

Append the information provided in your NETLIB/circuit/config/ADSlibconfig fileto your <design_kit_name> /circuit/config/ADSlibconfig file and save yourchanges.


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Edit the file <design_kit_name>/circuit/models/fet1.net and replace all of itscontents with the following line:#uselib "NETLIB", "fet1"

Save the file with your changes.4.

You should now be able to simulate your design just as before; however, instead ofreferencing the ASCII netlist, the simulator will use the newly created encoded library.


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Completing the Design KitThis section describes the process of finalizing an ADS Design Kit. Verification is anessential step in design kit creation if model files were translated from another simulatorformat. There is a standard method for packaging and distributing design kits that shouldbe adhered to, and understanding the requirements of design kit support is alsoimportant. This section is mostly aimed at design kits that are being developed fordistribution outside of the organization where they were developed.

Verifying a Design KitIf a design kit contains translated models, verification of those models is an essential partof ADS design kit development and potentially the most time consuming part of creating adesign kit. This is because there can be significant differences between how simulatorswork, due to the use of different equations or unique extensions to a base technology. Anengineer working on verification must understand the details of the model very well, andmust take the time to understand how to correct for simulation differences.

Assigning a VersionEach release of a design kit must have a version assigned to it for the design kit to qualifyas following the standard. The version can be any string of your choice, but it must beregistered in the template eesof_lib.cfg file. For more information on the eesof_lib.cfg file,refer to Configuration Variables.

This version must be changed any time even one file in a design kit is changed, and thewhole design kit should be repackaged and shipped as a single unit, to maintain theintegrity of the complete set of files. This is very important for tracking down customerproblems. If a customer has a problem with a design in ADS, the Agilent EEsof-EDACustomer Support department cannot investigate the issue without installing the exactversion of the design kit that the customer has installed.

It is highly recommended that a revision control software package is used to store thedesign kit files during development and after release. This type of software tags eachindividual file with a version. The complete set of files can then be tagged at a releasewith a tag that is related to the version of the design kit seen by users.

Packaging for DistributionTo distribute your design kit, create a zip or 7z archive from the files. Zip and 7z areshipped as a standard part of ADS. The files are in the $HPEESOF_DIR/bin directory,including documentation in the zip.doc file for the zip format. If your design kit ispackaged in anything other than a .zip or _.7z_file, you must include installationinstructions with the design kit and be prepared to support your customers if they haveinstallation problems.

The design kit standard does not extend into the distribution method. It is up to eachcompany to decide the best method for distributing its design kits. The typical method forfoundry design kit distribution is from the foundry web page.

Once you have created and tested your design kit, there are a couple more steps you cantake prior to zipping up the contents of the design kit.

Remove all .ael files. If there is a .atf file for every .ael file, you can remove the .ael1.


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files. This will prevent users from modifying your code and changing the behavior ofyour design kit. It also hides the code you have built into your callbacks. Oneexception to this is the palette.ael file. Some users prefer to control the ordering oftheir palettes themselves. Since there is no user interface to control the paletteconfiguration, setting the palette location in the palette.ael file is the only way to dothis. There is no harm in shipping the palette.ael file.Remove the for_editing_pdk.defs file from the PDK. This file is used for adding the2.PDK in an editable mode to a workspace in ADS. Without this file, for adding a PDK toa workspace, the user will choose the lib.defs file, and thus won't be able to makemodifications to your design kit in ADS.Remove the circuit/ael directory. Only do this if you are using demand-loaded3.components and have all the item definitions in the form of itemdef.ael files.Make sure that none of the files in your design kit are read-only. All files must have4.full write permission or the unzip procedure may fail. To set the write permission onall files:On unix, from the directory at the top of the design kit, enter the command: chmod -R 777 *

On PC, open the Windows Explorer file browser and click the right mouse button oneach directory and filename. Select Properties and ensure the Read-only attribute isunchecked.Zip the design kit, including the top level directory. Make sure before you start the5.zip that you are pointing to the top level directory of the design kit, the one whichbears the name of the design kit. If you are performing this process from thecommand line in a DOS or unix shell, cd to the directory above the design kit. Tocreate the .zip file SampleKit.zip, enter the following command in a DOS shell or unixwindow:zip -r SampleKit SampleKit

To test the result, copy the .zip file to a different directory and unzip it. The unzipped6.image should contain only one directory at the top level. All subdirectories will be onelevel below that (see Design Kit Directories). To test the kit as your customers willuse it, refer to the Using ADS Design Kits documentation.

Note that the first three steps are highly recommended, so that the end-customer doesn'tinadvertently make modifications to the design kit.

Design Kit Directories

Supporting a Design KitThe creator and supplier of a design kit is responsible for informing the users of the kithow to get help with the kit, including installation, component and model or data fileproblems. Copy of Using ADS Design Kits can be used as a starting point for design kitusers. Agilent Technologies customer support can help with general setup issues orsimulation issues, but if the problem is specific to the design kit, the support personnelwill need access to the design kit.

Your company is expected to have a dedicated resource for this purpose. This person will


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handle the support calls first. If the problem is determined to be with the ADSenvironment or simulator, then the call and the design kit can be forwarded to the AgilentEEsof EDA customer support department. The customer should not contact AgilentTechnologies directly, since they will not have permission to share the design kit with theAgilent EEsof EDA customer support department. Additionally, if your customer worksdirectly with Agilent Technologies and it is discovered that the problem is in the design kit,then you may not get the feedback that you need to make the corrections to the kit.


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ADS Design Kit TutorialThis section provides step-by-step instructions for creating the basic parts of a sampledesign kit consisting of several typical foundry kit components:

Device with model reference and macro-based artworkInclude component

Even though these components may not be typical for all design kits, the steps areapplicable to a design kit in any technology.

To complete this tutorial, it is assumed that you have a basic working knowledge ofAdvanced Design System, including the location of the ADS installation directory for yourcomputer or site. This tutorial will refer to your ADS installation directory, which is definedas $HPEESOF_DIR. For example, on a PC, an ADS 2011 installation is typically installed inC:/Agilent/ADS2011. If you cannot find the installation directory on your computer or thesite-wide installation on a networked system, contact your system administrator or CADmanager. For simplicity, the tutorial steps will assume a typical PC installation.

NoteThe directory delimiter slash is shown as a forward slash "/". This should be used in most cases in adesign kit, especially in AEL files, where the backslash character "\" is interpreted as a string formattingcharacter. For example, "\n" is interpreted as a new line character. The AEL system() function is one ofthe rare cases where the back slash character may be required, and each backslash must be preceded byan extra backslash to tell the system to interpret it literally. The list of known characters that cause thisproblem are:\n=new line\r=return\f=form feed\b=back space\t=tab

Tutorial OverviewThe list below shows the basic steps that will be performed in this tutorial and includes ashort description of each section so you can quickly get a sense of what is required tobuild a simple design kit.

NoteThe completed sample design kit (SampleKit) is available with the ADS design kit software atHPEESOF_DIR/examples/DesignKit/SampleKit . For more information, refer to ADS Design Kit Tutorial.

Building the Basic Design Kit Parts describes setting up the various folders needed inyour basic design kit.Creating the lib.defs and for_editing_pdk.defs files describes how to create the librarydefinition files which mark the first step of design kit creation.Creating technology and preference files describes how to setup the technology andpreferences of your design kit.Creating eesof_lib.cfg file discusses how to create the eesof_lib.cfg file which is theconfiguration file of the design kit.Creating and Placing Models describes how to create models for your design Kit.Creating Component Symbol View explains how to create a symbol view for eachcomponent in your design kit.Viewing Debug Output describes how to view the debug output while on PC andLINUX.Creating the boot.ael describes how to create boot file (boot.ael) to load the designkit.Creating a Component Palette and Bitmaps describes how to create bitmaps (*.bmp)for your design kit components. The AEL file (palette.ael), which loads the bitmapsonto a palette and makes the palette available in an ADS schematic window, is alsodescribed in this section.


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Creating Component Definitions discusses how to build a component definition AELfile (sample_fet.ael) which defines how the component is netlisted along with otherproperties.Creating Artwork Macro discusses how to build a component artwork AEL file(sample_fet_art.ael) which creates the component artwork/layout.Linking Artwork Macro to the component explains how to create a layout view foreach component in your design kit.Providing Basic Documentation gives an example for creating a simple text file(about.txt) used to document the design kit.Making Components Accessible simply describes the two methods available forsetting up easy access to your design kit components.Testing Your Component lists a few steps you can use to verify that your componentsare working properly.Adding a Netlist Include Component describes how to create a netlist includecomponent which can be used to include model files (*.net) in your netlist.Creating the Netlist Include Definition discusses how to build a component definitionAEL file (SAMPLE_NETLIST_INCLUDE.ael) which defines how the component isnetlisted along with other properties.Creating Templates discusses how to create a template which can be used directly inany given circuit depending on our requirement.Creating an Example Design Using your Design Kit shows an example schematic thatuses the design kit created in the tutorial.Adding Components to the Component Library Dialog describes the method formaking your design kit components visible in the Component Library dialog.Adding Demand Loaded Components describes how to create the item definition file(*itemdef.ael) used for dynamically loading design kit components.Using a Subcircuit Model provides an outline of how to include a subcircuit model inyour design kit using the information learned in the tutorial.Creating Component and Menu Documentation discusses how to create thedocumentation for the menu and the components present in your design kit.Adding DRC discusses how to add basic Design Rule Check(DRC) to your sampledesign kit.Accessing the Supplied Sample Kit gives information about how to access theSampleKit which has been supplied along with ADS.

Building the Basic Design Kit PartsThe first step in creating a design kit is to create the directory in which to store the basicdesign kit parts after they have been built. This will be the directory that you willeventually archive and distribute as the design kit. Create that directory now. You cancreate this directory anywhere but to simplify the tutorial, it is assumed that it will becreated in the home directory ($HOME). Name this directory <KitName>_.

Create the following subdirectories in your Kit.

circuit/aelcircuit/artworkcircuit/modelscircuit/bitmaps/circuit/records*circuit/templates*de/aelSampleKitSampleKit_techdocdrc/rulesexamples


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NoteDirectories noted with an asterisk are optional directories that are used in this tutorial.

Creating the lib.defs and for_editing_pdk.defs files

The next step is to create library definition files, which will be referred to when this kit isadded to a workspace. The lib.defs file assigns a read only mode to these librarieswhereas the for_editing_pdk.defs assigns a shared mode to these libraries. One can usethe for_editing_pdk.defs file if you requires to edit the libraries of the design kit.

To create the SampleKit/lib.defs file that will be used in this tutorial:

Open a text editor.1.Enter the following line, exactly as it is written here, in a text file.2.

# Library Defs for SampleKit

DEFINE SampleKit_tech ./SampleKit_tech

ASSIGN SampleKit_tech libMode readOnly

DEFINE SampleKit ./SampleKit

ASSIGN SampleKit libMode readOnly

Save the file as:3.

$HOME/SampleKit/lib.defs

Note that lines beginning with a # are ignored by ADS. # is used to add comments to the.defs files.

To create the SampleKit/for_editing_pdk.defs file that will be used in this tutorial:


# Library Defs for editing the SampleKit

# Remove this from the design kit before distributing to customers.

DEFINE SampleKit ./SampleKit

ASSIGN SampleKit libMode shared

DEFINE SampleKit_tech ./SampleKit_tech

ASSIGN SampleKit_tech libMode shared

Save the file as:3.

$HOME/SampleKit/for_editing_pdk.defs

Note that this assumes that you have created the SampleKit/SampleKit subdirectoriesunder your $HOME directory as described in Building the Basic Design Kit Parts.

Creating technology and preferences

These files are used to define the technology and preferences for the design kit beingcreated.

Creating Technology

For creating technology of the design kit create a new workspace, say,1.SampleKit_wrk and add your kit in editable mode while following the steps in theworkspace wizard. For now you may choose any of the technology settings for yourdefault library that is created while creating a new workspace.From ADS Main window, go to the Options->Technology->Technology Setup...,2.choose your library SampleKit_tech from the drop-down and set the technologyparameters as described in the section Specifying Technology File Information.Ideally in the Referenced Libraries tab of this window, you should add


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ads_schematic_layers (for schematic layers) and ads_standard_layers (for layoutlayers if your kit is schematic-only) by using the Has Technology option on the left.You could of course add your own layers in addition to these. Click on Show OtherTechnology Tabs if you see only two tabs in this dialog box.

Technology SetUp- Reference Libraries tab

Technology SetUp- Layout Units tabNext, choose the library SampleKit from the drop-down, and using the Has3.Technology option on the left, add the library SampleKit_tech. Now you havesuccessfully set your PDK's technology.


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Layer Mapping

Layer Mapping is used to map the name of the Layer, Purpose to the GDSLayer, andGDSPurpose respectively. This is required if you need to export or import GDSII files ,which use your PDK's technology.For creating/editing the layermap.map file for your PDK, follow the below mentionedsteps:

Create a layout cell and go to File->Export.. and a Export dialog box would open up.1.

In the Export dialog box click on More options tab which would open a More Options2.dialog box.In the More Options dialog box switch to Layer tab.3.From the dropdown chose the Load custom layer map file option as shown in the4.figure below.


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Now you can add/delete layer details using the Add row and delete row buttons.5.After making desired changes chose the Save layer map file option and save the file6.in the location SampleKit\SampleKit_tech with the name LayerMap.map.

Now when you want to use this file during GDS export.import, simply select Use layermap file from library: SampleKit_tech

Material Definitions

Material definitions are used to specify various electrical and magnetic properties ofConductors, Dielectrics and Semiconductors.The Surface Roughness Models are alsodefined here.This step is optional and is required only if you would like to provide theelectrical and magnetic properties of your layers.


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For setting the material definitions in your design kit(it is presumed that you have addedthe kit in editable mode), go to Options->Technology->Material Definitions in your ADSmain window, which opens a Material Definitons dialog box. In this dialog box, from thedropdown, choose the SampleKit_tech library for editing. Now you can manually edit theMaterial definitions in this box.

After making the changes, press Apply and then press OK.After performing above stepsthe changes would be saved in the material definitions file, materials.matdb.

Substrate Definition

Substrate information is used to specify the electrical properties associated with theartwork layers that you have defined.The Momentum electro-magnetic simulator usessubstrate information for cases where arbitrary shaped components need to be simulated.This is different information than the substrate components used in schematics whenvarious transmission line components such as microstrip are simulated. Substrateinformation is optional and is required only if you want to specify the electrical propertiesassociated with the artwork layers.For setting the Substrate definitions of your kit follow the below mentioned steps:

In the ADS main window, go to the Library view.1.Now right click on the Sample_Tech library and chose the New substrate option which2.would result in the New Substrate dialog box as shown below.


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Name the substrate as sample and chose appropriate template and click OK.3.A new sample substrate dialog window opens up as shown below.4.

Now create your desired substrate in the sample substrate window and save it.5.For details regarding creating substrate please refer to the link Substrate Editor .

Creating Preference files

Create a layout in the library SampleKit, and go to * Options > Preferences*. ThePreferences for Layout dialog box appears. Now you can set the desired preferences asdescribed in Layout Preferences . After setting the preferences use the button save a copyto save the file as layout.prf in $HOME/SampleKit/SampleKit location.


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Repeat similar steps for creating the schematic preference file and save it as schematic.prfat the same location where the layout.prf file has been saved.

Ensure that the names of these files you save in the design kit are layout.prf andschematic.prf.

After you have successfully set and saved the preferences in your design kit, you maydelete this layout and schematic.

Creating eesof_lib.cfg file

The next part of your design kit to be created is the eesof_lib.cfg file which is the


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configuration file of the design kit. For creating the eesof_lib.cfg file follow the belowmentioned steps:

Open SampleKit_wrk workspace(with SampleKit in editable mode) which was created1.previously.In the Library View, right click on the design kit's main library (SampleKit in our2.case) and choose Configure Library... option.A Library Configuration Editor dialog box opens up.3.Fill the appropriate fields in various tabs of the Library Configuration Editor. For4.details about filling the Library Configuration Editor box refer the link ConfigurationVariables.

Simulation Tab Setup


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Custom AEL tab Setup

Templates tab Setup


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Verification tab Setup

Technology tab Setup


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Library Browser tab Setup

Documentation tab Setup


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Design Kit tab SetupAfter updating the desired values in the Library Configuration Editor apply the5.changes and press OK to exit the editor.The updates made in the eesof_lib.cfg wouldonly get reflected in the Kit only the next time when the Library is opened.

After the above mentioned steps ensure that a eesof_lib.cfg file has been created in theSampleKit/SampleKit folder. Note that the eesof_lib.cfg is not supposed to be editedmanually. All changes must be made using the Library Configuration Editor.

Creating and Placing Models

The model file are used to include the simulation data in the design kit.

For creating model files for the component of the design kit, follow the following steps:


define model11(d g s1 s2)

parameters gw=100 um nf=4

R:R1 s1 _net1 R= .01

R:R2 s2 _net1 R= .01

"TOM3M_L":TOM3 d g _net1 W=gw Ng=nf

model TOM3M_L TOM3 NFET=1 PFET=0 Tnom=25 Ugw=1 um Ngf=1 Vto=-1.18482 V Alpha=5.68

Beta=0.0003541 Lambda=-0.02564 Gamma=0.036718 Q=1.25 K=0.682 Vst=0.01811457 Mst=0.23

Ilk=4.18e-007 mA Plk=2.6 V Kgamma=0.013926 Taugd=1000 nsec Qgql=0.2e-15 Qgqh=1.2e-16

Qgi0=7.05e-7 Qgag=1.31025 Qgad=1.13 Qggb=6.7 Qgcl=5.2e-17 Qgsh=8.1e-16 pF Qgdh=5.7e-16 pF

Qgg0=8.6e-17 Capmod=2 Cds=0.0002391 pF Tau=0.0011 nsec Rd=0 Ohm Rdtc=0 Rg=1.0 Ohm

Rgmet=0.1 Rs=0 Ohm Rstc=0 Is=1.0e-11 mA Eta=1.3 Alphatce=0 Gammatc=0 Msttc=0 Vsttc=0

Vtotc=0 Betatce=0 Xti=2 Eg=0.8 Imax=1.43 Fnc=0 R=0.01 P=0.7 C=0.001 Kf=3.9e-12 Af=1 Ffe=1

end model11

Save the file as:3.

$HOME/SampleKit/circuit/models/fet1.net

If you wish to add more than one component in your design kit then you may add more


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model files.

Creating Component Symbol View

The next part of your design kit to be created is a schematic symbol view for each of yourcomponents. The tutorial will guide you through one method of symbol view creation,copying an existing symbol. Basic Parts of an ADS Design Kit describes two other methodsin Schematic Symbol.

To copy an existing symbol:

Open SampleKit_wrk workspace which was created previously.1.Create a cell in kit's main library, SampleKit, with the name of your component (you2.will need to use this same name in the first argument of create_item of yourcomponent in further steps). The name in our case will be sample_fetCreate a symbol view for this component named symbol.3.A symbol view opens up and the Symbol Generator dialog box appears.4.In the Symbol Generator dialog box, select the Copy/Modify tab.5.Set the Symbol Category to Devices-Linear.6.Click the FET symbol so the ads_rflib:FET appears in the Symbol Name field, then7.click OK.Once you have copied the built-in symbol, you can edit the symbol if desired.8.However it will not be modified for this example.Choose File > Save and save the view.9.

You should now have a symbol view for use in your design kit. The symbol view is locatedin the directory $HOME/SampleKit/SampleKit/sample_fet/symbol.

Viewing Debug Output

On unix, debug output is visible in the window from which ADS was invoked. On PC, editthe shortcut property Target and add -d daemon.log to the end of the command line inthe Target field.Example: C:\agilent\ADS2011_10\bin\ads.exe -d daemon.logThis will enable you to view output to stderr in a log window. Look for text in red. All othertext is a communication log. The information is also saved to a file called daemon.log inthe ADS startup directory.

Another option for displaying debug information is using the de_info() function to outputmessages to an info dialog that will pop up from ADS.

Instead of

fputs(stderr, "comment");

you can use

de_info(identify_value("comment"));

You can even define a utility function such as:

defun debug_print(msg)

{

de_info(identify_value(msg));

}


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To use this function, simply call:

debug_print("msg");

Creating the boot.ael File

An ael file called boot.ael must be provided so that ADS knows how to load the design kit.From the boot.ael file, you can load other AEL files, such as those that will load the itemdefinition and palettes as described in later sections.

To create the de/ael/boot.ael file:

Open a text editor.1.Copy the text below into a new file.2.

The Boot File (boot.ael)

/*----------------------------------------------------------------------------+/

FILE : boot.ael

This file controls the loading of the design kit.

The value of variable designKitrecord is picked up from the eesof_lib.cfg

/+----------------------------------------------------------------------------*/

// Read values from eesof_lib.cfg file.

decl SAMPLEKIT_NAME = designKitRecord[0];


decl SAMPLEKIT_BOOT = designKitRecord[2];

decl SAMPLEKIT_VER = designKitRecord[3];

// These path names may be used later to load other files.

decl SAMPLEKIT_CIRCUIT_AEL_DIR = strcat(SAMPLEKIT_PATH, "circuit/ael/");

decl SAMPLEKIT_CIRCUIT_BITMAP_DIR = strcat(SAMPLEKIT_PATH,

"circuit/bitmaps/");

decl SAMPLEKIT_CIRCUIT_ARTWORK_DIR = strcat(SAMPLEKIT_PATH, "circuit/artwork/");

decl SAMPLEKIT_DE_AEL_DIR = strcat(SAMPLEKIT_PATH, "de/ael/");

decl SAMPLEKIT_DRC_RULES_DIR = strcat(SAMPLEKIT_PATH, "drc/rules/");

decl SAMPLEKIT_CIRCUIT_MODELS_DIR = strcat(SAMPLEKIT_PATH, "circuit/models/");

fprintf(stderr, "Loading %s design kit\n", SAMPLEKIT_NAME);

Save the file as $HOME/SampleKit/de/ael/boot.ael3.

The Boot File (boot.ael) shows the contents of your new boot.ael file. This code will beadded to later in this tutorial. By accessing certain global variables, you can get the valuesfrom the eesof_lib.cfg file, as described in Creating the eesof_lib.cfg File. These values arestored in a list called designKitRecord.

Debug tips are included directly in the boot.ael code for your convenience. Remember toremove all debug print statements before you ship your design kit.

NoteVariables such as those in The Boot File (boot.ael) called SAMPLEKIT_PATH, etc., are global variables. Thescope of an AEL variable is not restricted to the file in which it is defined. In other words, this variablemust be unique in the library to avoid being overwritten by another declaration of the same variable.Therefore, in the future when you build design kits, make sure that each AEL variable name is unique inthe library. One way to do this is to include the name and version of the design kit in the variable name.

Creating a Component Palette and Bitmaps

Defining a component palette consists of two steps:

Creating bitmap files for each component.Writing an AEL function to connect the bitmap to the component and load thedefinition into the system.


124

Basic Parts of an ADS Design Kit , discusses the details of bitmap creation for design kits.A tool offered within ADS is the DesignGuide Developer Studio.

The Developer Studio can be installed from your ADS installation CD, if it is not alreadyinstalled, and it does not require a license to run. A design guide is different than a designkit, but the bitmap tool can be used for both. For more information on the differencesbetween DesignGuides and design kits, refer to Design Kits versus Libraries. This tool ismentioned here because it provides a bitmap editor which is specially designed to createbitmaps for use in ADS. The Save As menu facilitate saving the bitmaps in both pc andunix formats. Sample bitmaps for all ADS components are available with the tool to copyas starting material. For an explanation of how to use the various features of the tool,refer to Bitmap Editor.

For a design kit with a large number of components, more than one palette group may bedefined. For the sample kit in this tutorial, all components will go into one palette.

To create your UNIX and PC compatible bitmap:

From the ADS Main window, choose DesignGuide > DesignGuide Developer1.Studio > Start DesignGuide Studio.From the Developer Studio dialog, choose Tools > Bitmap Editor. The Bitmap2.Editor dialog box appears.From the Bitmap Editor, choose File > Open. The Open Bitmap dialog box appears.3.Sample bitmaps are provided in:4.$HPEESOF_DIR/designguides/projects/dgstudio/ui/bitmaps/adsbmpsOpen the bitmap for FET.BMP and edit the bitmap as needed to customize it for yourdesign kit (see The sample_fet.bmp File in the Bitmap Editor).

The sample_fet.bmp File in the Bitmap Editor

After editing your bitmap file, save the bitmap in the appropriate design kit directory.5.Remember that the directory where the bitmap should be stored is:

SampleKit\circuit\bitmapsName the FET bitmap sample_fet.bmpThe final step in making the palette available is to create an AEL file calledpalette.ael, which makes a library palette using the functionde_define_library_palette.*

NoteThe function de_define_library_palette used in the palette.ael file defines a separate palettefor Schmatic and the Layout windows. For more information about the palette function, referto Component Palette.

To create the de/ael/palette.ael file:Open a text editor.6.Copy the code below into a file.7.


125

set_design_type(analogRFnet);

de_define_library_palette("SampleKit",SCHEMATIC_WINDOW, "analogRF_net", "SampleKit",

"SampleKit", 0

,list(

"SampleKit"

,"sample_fet"

,""

,"Low Noise FET"

,strcat(SAMPLEKIT_CIRCUIT_BITMAP_DIR, "sample_fet")

)

);

de_define_library_palette("SampleKit",LAYOUT_WINDOW, "analogRF_net", "SampleKit",

"SampleKit", 0

,list(

"SampleKit"

,"sample_fet"

,""

,"Low Noise FET"


)

);

NoteDo not include the file extension (.bmp) on the bitmap name in de_define_library_palette. This willcause the function to fail on some unix systems.

Save the file as $HOME/SampleKit/de/ael/palette.ael8.In order for ADS to read the new palette.ael file, the boot file must be modified to9.load the palette.ael file. Add the following line to SampleKit/de/ael/boot.ael now:load(strcat(SAMPLEKIT_PATH, "/de/ael/palette"));

NoteThe load() function does not need the .ael extension on the filename it is loading. If the filepalette.atf is found with a newer time stamp than palette.ael, the palette.ael file will not berecompiled. If palette.ael is newer, it will be recompiled into a new palette.atf and then loaded.

For more information about the palette function, refer to Component Palette.

Creating Component Definitions

A component definition is added to the design environment by a create_item() commandprovided in an AEL file.

Basic Parts of an ADS Design Kit also includes more information about the create_item()function. For this tutorial, the most you need to understand is how to define a list ofparameters, how the component is netlisted and how are callbacks called. These are allparts of the item definition.

The create_item() functions for your sample components should be defined as follows in afile called sample_fet.ael.

For a small design kit, all the item definitions could be combined into one file. But therecommended method is to create a separate file for each item. This is especiallyrecommended if there are parameter callbacks associated with each component.

To create a component definition for your FET component:

Open a text editor.1.Copy the coded text as per given below into a new file.The coded text shown below2.consists of several sections

HeaderDeclaring RangeList for the parametersDeclaring default values for the parametersCreating formsets for "nf" and "model" parameterDefining parameter callback functionCreating Item Definition


126

NoteOnly the text given in the boxes below has to be copied to form the sample_fet file.The headingsprovided in between for explanation are only for the purpose of elaborating each section of file. Thesample_fet.ael provided below includes more information than is required. This is provided to teachyou about the specific role which each command/function performs.

The Item Definition File (sample_fet.ael)

Header

/*----------------------------------------------------------------------------+/

FILE : sample_fet.ael





item definition

/+----------------------------------------------------------------------------*/

Declaring RangeList for the parameters

decl sample_fet1_ranges = list(50e-6,200e-6,1,100);

Declaring default values for the parameters


decl sample_fet1_nf_default=4;

decl sample_fet1_gw_default=100e-6;

decl sample_fet1__M_default=1;

Creating formsets for "nf" and "model" parameter

create_constant_form("sample_fet1_nf2", "2", 0, "2", "2");

create_constant_form("sample_fet1_nf4", "4", 0, "4", "4");

create_form_set("sample_formset_fet1_nf",

"sample_fet1_nf2",

"sample_fet1_nf4"

);

create_constant_form("model11","model11",0,"model11","model11");

create_form_set("sample_formset_fet1_model",

"model11"

);

Defining parameter callback function

defun sample_fet1_parm_modified_cb

(

cbP, // callback function pointer

parmName, // clientData

itemInfoP // itemInfo pointer

)

{

decl parmList = NULL;

decl nf;

decl rangeList;

decl checkVal;

/*--- calculate dependent parameter values -----------------------------------*/

nf = pcb_get_form_value(itemInfoP, "nf");

rangeList = sample_fet1_ranges;

decl gw = pcb_get_mks(itemInfoP, "gw");

decl _M = pcb_get_mks(itemInfoP, "_M");

if (listlen(rangeList)==4)

{

if (parmName == "gw")

{

decl var_present = pcb_get_parm_type(itemInfoP, "gw");

if (var_present != NULL)

{

decl gw = pcb_get_mks(itemInfoP, "gw");

checkVal=SampleKit_v1_parm_checkRange("gw", gw, nth(0, rangeList), nth(1, rangeList),

"um");

if(checkVal != gw && var_present=="NUMBER")

{

gw=checkVal;


127

parmList = pcb_set_mks(parmList, "gw", gw);

}

else if(checkVal != gw)

{

gw=checkVal;


}

else

{

gw =SampleKit_v1_parm_checkStep("gw",gw,1e-6,"um");

if(var_present=="NUMBER")


}

}

}

else if (parmName == "_M")

{

decl var_present = pcb_get_parm_type(itemInfoP, "_M");


{

decl _M = pcb_get_mks(itemInfoP, "_M");

checkVal=SampleKit_v1_parm_checkRange("_M", _M, nth(2, rangeList), nth(3, rangeList),

"");

if(checkVal != _M && var_present=="NUMBER")

{

_M=checkVal;

parmList = pcb_set_mks(parmList, "_M", _M);

}

else if(checkVal != _M)

{

_M=checkVal;


}

else

{

_M =SampleKit_v1_parm_checkStep("_M",_M,1,"");

if(var_present=="NUMBER")


}

}

}

}

return(parmList);

}

Creating Item Definition

create_item("sample_fet", // name

"FET", // description label

"M", // prefix

0, // attributes

NULL, // priority

NULL, // iconName


NULL, // dialogData

CmpModelNetlistFmt, // netlist format string






ITEM_PRIMITIVE_EX, // extra attributes

create_parm("model",

"model name",

0,

"sample_formset_fet1_model",

UNITLESS_UNIT,

prm("model11")

),

create_parm( "nf", // name

"Number of Fingers = 2 and 4", // label

PARM_INT, // attrib

"sample_formset_fet1_nf", // formSet


prm("sample_fet1_nf4"), // default value

list(dm_create_cb(PARM_MODIFIED_CB, // callback

"sample_fet1_parm_modified_cb",

"nf",

TRUE)

)

),

create_parm( "gw", // name

"Gate Width-->(50 um to 200 um in step of 1 um)", // label

PARM_OPTIMIZABLE|PARM_STATISTICAL, // attrib

"StdFileFormSet", // formSet

LENGTH_UNIT, // unit code

prm("StdForm", "100 um"), // default value




128

"gw",

TRUE)

)

),

create_parm( "_M", // name

"Number of Devices in Parallel", // label




prm("StdForm", "1"), // default value



"_M",

TRUE)

)

)

);

In order for ADS to read the new sample_fet.ael file just created, the boot file must1.be modified to load the sample_fet.ael file. Add the following lines(if not alreadypresent) to the end of the SampleKit/de/ael/boot.ael and save the boot.ael file.

load(strcat(SAMPLEKIT_PATH, "/circuit/ael/sample_fet"));

NoteWhen writing AEL code, you must be very careful that each quote, semi-colon, parenthesis andbracket is exactly as shown. The AEL interpreter will fail if there are errors in the file, and it may nottell you where the errors are. If you get error messages when starting ADS compare your fileagainst the tutorial file shipped with the software.

Creating Artwork Macro

Creating Artwork macro has been discussed in detail in the section Creating theParameterized AEL Macro Artwork ManuallyFor the sake of example we will use the belowpresent code for making our Artwork Macro.For creating the Artwork macro, follow thebelow mentioned steps:

Open a text editor.1.Copy the coded text as per given below into a new file.2.

/* LayerID Definitions */

decl def=db_layerid(0,-1);

decl mesa=db_layerid(1,-1);






decl Via_Poly=db_layerid(7,-1);


decl Via_Pass=db_layerid(9,-1);

decl BVia=db_layerid(10,-1);

decl demo_dummy=db_layerid(11,-1);

decl Border=db_layerid(12,-1);

decl nicr_DRC=db_layerid(2,1);

decl mesa_DRC=db_layerid(1,1);

defun sample_fet1_art(model,nf,gw,_M)

{

//A DesignContext is an AEL object that holds information about a particular design being

edited


de_set_global_db_factor();

decl ox=0;

decl oy=0;

gw=gw*1e6;

decl n;

decl j;

decl k;

decl l,m,p,q,r,x,a,b,c,y,z;

decl i;

decl d=20; // width of M0 to M0 rectangle and the lenght will be gw-1 um

decl s=4.15;// gap b/w each multilayer rectangle i.e. from M0 to M0

decl g=20;

decl rep=d+g+2*s;

if(nf=="2" || nf==2)

{

db_add_rectangle(designContext,mesa,ox,oy,ox+gw,oy+2*d+2*s+g+1);


129

for(l=0;l<1;l++)

{

db_add_rectangle(designContext,M0,ox-0.43,oy+2.5+d,ox+gw,oy+d+2.65);

db_add_rectangle(designContext,M0,ox-0.43,oy+2.5+d+s+g,ox+gw,oy+d+s+g+2.65);

oy=oy+rep;

}

oy=0;

for(p=0;p<1;p++)

{

db_add_rectangle(designContext,M0,ox-3.01,oy+0.5+d+1.59,ox-0.43,oy+0.5+d+2.56);

//start of finger small rectangle (left)

db_add_rectangle(designContext,M0,ox-3.01,oy+0.5+d+s+g+1.59,ox-0.43,oy+0.5+d+s+g+2.56);

oy=oy+rep;

}

oy=0;

for(q=0;q<1;q++) //end of finger

small rectangle (right)

{

db_add_rectangle(designContext,M0,ox+gw,oy+2.5+d,ox+gw+1,oy+3+d);

db_add_rectangle(designContext,M0,ox+gw,oy+2.5+d+s+g,ox+gw+1,oy+d+s+g+3);

oy=oy+rep;

}

oy=0;

for(r=0;r<1;r++) //small triangle

on the right

{

for(x=0;x<=1;x++)

{

db_add_polygon(designContext);

db_add_point(designContext,ox+gw,oy+d+x*s+x*g+2.65);

db_add_point(designContext,ox+gw,oy+d+x*s+x*g+3);

db_add_point(designContext,ox+gw-0.5,oy+d+x*s+x*g+2.65);


db_end(designContext, M0);

}

oy=oy+rep;

}

oy=0;

db_add_rectangle(designContext,M0,ox+gw+2.5,oy+0.5+d+1.65,ox+gw+12.5,oy+0.5+d+s+g+2.5);

db_add_rectangle(designContext,Via_Nit2,ox+gw+3,oy+0.5+d+2.15,ox+gw+12,oy+0.5+d+s+g+2);


db_add_rectangle(designContext,Via_Poly,ox+gw+4,oy+0.5+d+3.15,ox+gw+11,oy+0.5+d+s+g+1);


for(k=0;k<1;k++) /*-------left side small trapezium----------*/

{

for(i=0;i<=1;i++)

{


db_add_point(designContext,ox-0.43,oy+0.5+d+i*s+i*g+1.59);

db_add_point(designContext,ox,oy+0.5+d+i*s+i*g+2);

db_add_point(designContext,ox,oy+0.5+d+i*s+i*g+2.15);



db_end(designContext,M0);

}

oy=oy+rep;

}

oy=0;

for(j=0;j<=1;j++) //rectangle of width 20(M0)

{

db_add_rectangle(designContext,M0,ox+0.5,oy+0.5,ox+gw-0.5,oy+d+0.5);

db_add_rectangle(designContext,Via_Nit2,ox+1,oy+1,ox+gw-1,oy+d);

db_add_rectangle(designContext,M1,ox+1.5,oy+1.5,ox+gw-1.5,oy+d-0.5);

db_add_rectangle(designContext,Via_Poly,ox+2,oy+2,ox+gw-2,oy+d-1);


oy=oy+rep;

}

oy=0;

for(m=0;m<1;m++) // rectangle of width g=5 um

{

db_add_rectangle(designContext,M0,ox+0.5,oy+0.5+d+s,ox+gw+6.5,oy+0.5+d+s+g);

db_add_rectangle(designContext,Via_Nit2,ox+1,oy+1+d+s,ox+gw+6,oy+d+s+g);

db_add_rectangle(designContext,M1,ox+1.5,oy+1.5+d+s,ox+gw+5.5,oy+d+s+g-0.5);

db_add_rectangle(designContext,Via_Poly,ox+2,oy+2+d+s,ox+gw+5,oy+d+s+g-1);


oy=oy+rep;

}

oy=0;

for(a=0;a<1;a++)

{

db_add_rectangle(designContext,M1,ox-6.81,oy+0.5+d-0.45,ox-2.01,oy+0.5+d+2*s+g+0.45);

db_add_rectangle(designContext,Via_Nit2,ox-6.31,oy+0.5+d+0.05,ox-2.51,oy+0.5+d+2*s+g-

0.05);

db_add_rectangle(designContext,M0,ox-5.81,oy+0.5+d+0.55,ox-3.01,oy+0.5+d+2*s+g-0.55);

oy=oy+rep;

}

oy=0;

db_create_pin(designContext, ox+gw/2, oy+2*d+2*s+g-1.5, 90, M2, 4, NULL);

decl dg_HandleS1=db_add_rectangle(designContext,M2,ox+2.5,oy+2.5+rep,ox+gw-2.5,oy+d-

1.5+rep);

db_define_edge_area_port(designContext,dg_HandleS1,4);


130

db_create_pin(designContext, ox+gw/2, oy+2.5, -90, M2, 3, NULL);

decl dg_HandleS2=db_add_rectangle(designContext,M2,ox+2.5,oy+2.5,ox+gw-2.5,oy+d-1.5);

db_define_edge_area_port(designContext,dg_HandleS2,3);

db_create_pin(designContext, ox+gw+10.5, oy+34.15, 0, M2, 1, NULL);

decl

dg_HandleD=db_add_rectangle(designContext,M2,ox+gw+4.5,oy+0.5+d+3.65,ox+gw+10.5,oy+0.5+d+

s+g+0.5);

db_define_edge_area_port(designContext,dg_HandleD,1);

db_create_pin(designContext, ox-6.81, oy+34.15, 180, M1, 2, NULL);

decl dg_HandleG=db_add_rectangle(designContext,M1,ox-6.81,oy+0.5+d-0.45,ox-

2.01,oy+0.5+d+2*s+g+0.45);

db_define_edge_area_port(designContext,dg_HandleG,2);

de_set_origin(ox-6.81,oy+34.15);

}

/*----------------------*************************************************************----

-------------------------*/

else if(nf=="4" || nf==4)

{

db_add_rectangle(designContext,mesa,ox,oy,ox+gw,oy+3*d+4*s+2*g+1);

for(l=0;l<=1;l++)

{

db_add_rectangle(designContext,M0,ox-0.43,oy+2.5+d,ox+gw,oy+d+2.65);

//finger width

db_add_rectangle(designContext,M0,ox-0.43,oy+2.5+d+s+g,ox+gw,oy+d+s+g+2.65);

oy=oy+rep;

}

oy=0;

for(p=0;p<=1;p++)

{

db_add_rectangle(designContext,M0,ox-3.01,oy+0.5+d+1.59,ox-0.43,oy+0.5+d+2.56);

//start of finger small rectangle

db_add_rectangle(designContext,M0,ox-3.01,oy+0.5+d+s+g+1.59,ox-0.43,oy+0.5+d+s+g+2.56);

oy=oy+rep;

}

oy=0;

for(q=0;q<=1;q++)

{

db_add_rectangle(designContext,M0,ox+gw,oy+2.5+d,ox+gw+1,oy+3+d);

db_add_rectangle(designContext,M0,ox+gw,oy+2.5+d+s+g,ox+gw+1,oy+d+s+g+3);

oy=oy+rep;

}

oy=0;

for(r=0;r<=1;r++)

{

for(x=0;x<=1;x++)

{



db_add_point(designContext,ox+gw,oy+d+x*s+x*g+3);

db_add_point(designContext,ox+gw-0.5,oy+d+x*s+x*g+2.65);



}

oy=oy+rep;

}

oy=0;

/*-----------------------------------Ports on M2-----------------------------------*/

db_create_pin(designContext, ox+gw/2, oy+3*d+4*s+2*g-1.5, 90, M2, 4, NULL);

oy=oy+2*rep;

decl dg_Handle=db_add_rectangle(designContext,M2,ox+2.5,oy+2.5,ox+gw-2.5,oy+d-1.5);

db_define_edge_area_port(designContext,dg_Handle,4);

oy=0;

db_create_pin(designContext, ox+gw/2, oy+2.5, -90, M2, 3, NULL);

decl dg_Handle1=db_add_rectangle(designContext,M2,ox+2.5,oy+2.5,ox+gw-2.5,oy+d-1.5);

db_define_edge_area_port(designContext,dg_Handle1,3);

db_create_pin(designContext, ox+gw+25.5, oy+0.5+1.5*d+2*s+g, 0, M2, 1, NULL);

decl

dg_Handle2=db_add_rectangle(designContext,M2,ox+gw+4.5,oy+2.5+d+s,ox+gw+25.5,oy+2*d+3*s+2

*g-1.5);


for(k=0;k<=1;k++)

{

for(i=0;i<=1;i++)

{



db_add_point(designContext,ox,oy+0.5+d+i*s+i*g+2);

db_add_point(designContext,ox,oy+0.5+d+i*s+i*g+2.15);




}

oy=oy+rep;

}

oy=0;

for(j=0;j<=2;j++)

{

db_add_rectangle(designContext,M0,ox+0.5,oy+0.5,ox+gw-0.5,oy+d+0.5);

db_add_rectangle(designContext,Via_Nit2,ox+1,oy+1,ox+gw-1,oy+d);


db_add_rectangle(designContext,Via_Poly,ox+2,oy+2,ox+gw-2,oy+d-1);


131


oy=oy+rep;

}

oy=0;

for(m=0;m<=1;m++)

{

db_add_rectangle(designContext,M0,ox+0.5,oy+0.5+d+s,ox+gw+6.5,oy+0.5+d+s+g);

db_add_rectangle(designContext,Via_Nit2,ox+1,oy+1+d+s,ox+gw+6,oy+d+s+g);


db_add_rectangle(designContext,Via_Poly,ox+2,oy+2+d+s,ox+gw+5,oy+d+s+g-1);


oy=oy+rep;

}

oy=0;

db_add_path(designContext);

db_set_path_corner(designContext,PREF_MITERED_PATH);

db_set_path_width(designContext,10);

db_set_miter_cutoff(designContext,50);

db_add_point(designContext,ox+2.5,oy+10.5);

db_add_point(designContext,ox-21.32,oy+10.5);

db_add_point(designContext,ox-21.32,oy+2.5*d+4*s+2*g+0.5);

db_add_point(designContext,ox+2.5,oy+2.5*d+4*s+2*g+0.5);


de_cancel_draw_command();

for(c=0;c<1;c++)

{

db_add_polyline(designContext);

db_add_point(designContext,ox-16.32,oy+1.5*d+2*s+g+0.5);





db_add_point(designContext,ox+2.5,oy+0.5+d+2*s+g+5);


db_add_point(designContext,ox-16.32,oy+0.5+d+2*s+g+15);

db_add_point(designContext,ox-16.32,oy+0.5+d+2*s+g+5);




oy=oy+rep;

}

oy=0;

for(a=0;a<=1;a++) //left side three layered rectangles.....

{

db_add_rectangle(designContext,M0,ox-5.81,oy+0.5+d+0.55,ox-3.01,oy+0.5+d+2*s+g-0.55);

db_add_rectangle(designContext,Via_Nit2,ox-6.31,oy+0.5+d+0.05,ox-2.51,oy+0.5+d+2*s+g-

0.05);

db_add_rectangle(designContext,M1,ox-6.81,oy+0.5+d-0.45,ox-2.01,oy+0.5+d+2*s+g+0.45);

oy=oy+rep;

}

oy=0;

for(b=0;b<1;b++) //rectangles connecting the above drawn rectangles

{

db_add_rectangle(designContext,M0,ox-5.81,oy+0.5+d+g+2*s-0.55,ox-

3.01,oy+0.5+2*d+2*s+g+0.55);

db_add_rectangle(designContext,Via_Nit2,ox-6.31,oy+0.5+d+g+2*s-0.05,ox-

2.51,oy+0.5+2*d+2*s+g+0.05);

db_add_rectangle(designContext,M1,ox-6.81,oy+0.5+d+g+2*s+0.45,ox-2.01,oy+0.5+2*d+2*s+g-

0.45);

oy=oy+rep;

}

oy=0;

for(y=0;y<1;y++)

{

db_add_rectangle(designContext,M0,ox+gw+2.5,oy+0.5+d+s,ox+gw+27.5,oy+0.5+2*d+3*s+2*g);

db_add_rectangle(designContext,Via_Nit2,ox+gw+3,oy+1+d+s,ox+gw+27,oy+2*d+3*s+2*g);

db_add_rectangle(designContext,M1,ox+gw+3.5,oy+1.5+d+s,ox+gw+26.5,oy+2*d+3*s+2*g-0.5);

db_add_rectangle(designContext,Via_Poly,ox+gw+4,oy+2+d+s,ox+gw+26,oy+2*d+3*s+2*g-1);

db_add_rectangle(designContext,M2,ox+gw+4.5,oy+2.5+d+s,ox+gw+25.5,oy+2*d+3*s+2*g-1.5);

oy=oy+rep;

}

oy=0;

for(z=0;z<1;z++)

{

db_add_rectangle(designContext,M1,ox-36.81,oy+0.5+d+g+s+1.59,ox-

6.81,oy+0.5+2*d+2*s+g+2.56);

oy=oy+rep;

}

oy=0;

db_create_pin(designContext, ox-36.81, oy+0.5+1.5*d+2*s+g, 180, M1, 2, NULL);

decl dg_Handle3=db_add_rectangle(designContext,M1,ox-36.81,oy+0.5+d+g+s+1.59,ox-

6.81,oy+0.5+2*d+2*s+g+2.56);


de_set_origin(ox-36.81,oy+0.5+1.5*d+2*s+g);

}

/*------------------------------------------

*********************************************************--------------------------------

--------------*/

}

Save the new file as $HOME/SampleKit/circuit/artwork/sample_fet_art.ael.3.


132

NoteFor more information about the commands used in the Artwork macro please refer to the link AEL.

NoteEnsure that the Artwork macro name used while making the layout view of the component is exactlythe same as the one used to make the artwork in the sample_fet_art.ael file, as explained in LinkingArtwork Macro to the component

Linking Artwork Macro to the component

The next part of your design kit to be created is a layout view for your component.

For creating a layout view:

Open SampleKit_wrk workspace which was created previously.1.Create a new layout view(named layout) of the sample_fet cell which was created2.while creating the symbol view.A layout view opens up, now go to file->Design Parameters and a dialog box opens3.up.

In the View-Specific Configuration tab and select the artwork type from the drop-4.down as AEL Macro and fill appropriate name in the Artwork name feild- we will choseit as "sample_fet1_art" for this example (this is the name of the artwork macro whichused to create layout for the sample_fet component in the previous step). Click OK.Choose File > Save and save the layout view.5.

After the last step above, in ADS2011.10, you may get an itemdef.ael file created in yourcell named sample_fet. This can safely be deleted.

You should now have a layout view for use in your design kit. The layout view can belocated in the directory $HOME/SampleKit/SampleKit/sample_fet/layout.


133

Providing Basic Documentation

Using a text editor, you will now create the about.txt file to document your new design kit.This file should include the information listed in the template in Design Kit about.txtTemplate . Note that the template is only a suggested format for the file. You may modifythe format of the file or include information not listed in the template.

To create the SampleKit/doc/about.txt file:

Open a text editor.1.Add the following information to a file:2.Name: SAMPLE_KIT

Version: 1.0

Date: <The current date>

Description: This design kit contains the sample components

Revision History: Rev. 1.0

Save the new file as $HOME/SampleKit/doc/about.txt3.

Making Components Accessible

There are three methods for accessing your design kit components:

A component palette on the schematic window-The component palette is on theleft border of the schematic window.

The Component Library dialog-The Component Library dialog can be opened bychoosing Insert > Component > Component Library. The default tool bars alsoincludes a Display Component Library List button to open the Component Library

dialog. .All the cells are listed in the Library dialog even if they are notmentioned in the control and records file, which being the case, the componentswould pick default values.Library control and records files are used to load the necessary information into theComponent Library dialog.


134

The Library View in the ADS Main window-This view by default shows all cells inyour libraries.You can expand the individual cells to view the schematic, layout andsymbol views of the cells.

While this tutorial will show you how to setup both the component palette and theComponent Library dialog, you may decide to only provide one or the other. For moreinformation on choosing one of the two, refer to Component Palette vs. ComponentLibrary dialog.

Testing Your Component

At this time, you can test that the palette is loaded correctly. The files shown in the tablebelow should now be saved in their respective directories under the design kit top leveldirectory.

Tutorial Directory and File Locations


135

Directory File(s)

$HOME/SampleKit lib.defs, for_editing_pdk.defs

de/ael boot.ael

de/ael palette.ael

SampleKit/sample_fet/symbol symbol.oa

circuit/ael sample_fet.ael

circuit/bitmaps/ sample_fet.bmp

circuit/ael sample_fet_art.ael

circuit/models fet1.net

doc about.txt

In addition to these, you will also have 2 libraries - SampleKit and SampleKit_techTo test your changes:

Restart ADS to load the design kit.1.Open new workspace in ADS loading the lib.defs file in the SampleKit made by you.2.From the schematic window, select the new palette called SampleKit from the3.Component Palette List.From the palette list on the left side panel of the schematic window, select the4.sample_fet component and drag it onto the schematic page.

Adding a Netlist Include Component

The tutorial sample design kit will get its model data from a netlist file with a model card.

For the ADS simulator to find an externally referenced file, a design kit must contain anetlist include component. A built-in component called NetlistInclude is provided on theData Items palette. On this component, you must browse to or manually enter the nameof the included file. The built-in NetlistInclude component is handy for testing whilebuilding a design kit, but customers who use a design kit should not have to know wherethe model files are stored or be bothered with manually entering the file name. Thetutorial will guide you through creating a custom include component where the file nameis defined automatically for the design kit user.

NoteIf you place the NetlistInclude component and double click to view its parameters, select the IncludeFilesparameter and notice the field on the right side of the dialog called Section. This is one implementation ofselecting a corner case as defined in a section of a model file. In your design kit, you will want to presentthe user with the list of available corner case labels, as opposed to making them fill in a blank. This isdone by the definition of forms and formsets, as described in Forms and Formsets. An example of acomponent using this capability is also include in Example Process Component with Forms and Formsets.

Creating a Netlist Include Component Symbol view

Create a netlist include component symbol view, using the same process as described inCreating Component Symbols.

Open SampleKit_wrk workspace which was created previously.1.Create a cell in kit's main library, SampleKit, with the name of your component (you2.will need to use this same name in the first argument of create_item of yourcomponent in further steps). The name here will be SAMPLE_NETLIST_INCLUDE.Create a symbol view for this component named symbol.3.A symbol view opens up and the Symbol Generator dialog box appears.4.In the Symbol Generator dialog box, select the Copy/Modify tab.5.Set the desired Symbol Category, for example:Data Items.6.Click the desired symbol, then click OK.7.Once you have copied the built-in symbol, you can edit it.8.It is beneficial for the words on the symbol to identify the design kit. Change the9.


136

words NETLIST INCLUDE to SAMPLEKIT TECH INCLUDE, as shown in SAMPLEKITTECH INCLUDE Component Symbol.

NoteInstead of copying the symbol, you can also create a new component symbol. For making thesymbol from scratch refer to Schematic Symbol.

SAMPLEKIT TECH INCLUDE Component Symbol

For more information on editing symbol text, refer to Editing Existing Text and TextAttributes.Choose File > Save and save the view.10.

You should now have a symbol for use in your design kit. The cell can be located in thedesign kit's main library$HOME/SampleKit/SampleKit/%S%A%M%P%L%E_%N%E%T%L%I%S%T_%I%N%C%L%U%D%E.

Creating the Netlist Include Component Bitmap

A bitmap must also be created for the new SAMPLE_NETLIST_INCLUDE component.

To create bitmaps for the include component, use the same general process as describedin Creating a Component Palette and Bitmaps:

Create a bitmap that looks like the one in The SAMPLE_NETLIST_INCLUDE.bmp1.Bitmap.

The SAMPLE_NETLIST_INCLUDE.bmp Bitmap

Save the bitmap to the $HOME/SampleKit/circuit/bitmaps/ directory. The bitmap files1.should be named SAMPLE_NETLIST_INCLUDE.bmp.Modify the palette file (de/ael/palette.ael) to add the below mentioned code to the2.de_define_library_palette function of the palette.ael file.

list(

"SampleKit"

,"SAMPLE_NETLIST_INCLUDE"


137

,""

,"Process Netlist Include"

,strcat(SAMPLEKIT_CIRCUIT_BITMAP_DIR, "SAMPLE_NETLIST_INCLUDE")

)

In a palette with a long list of components, make sure that a custom include or processcomponent is placed at the top of the palette. This is a visual reminder to users that thiscomponent must be present in a schematic in order to simulate a circuit that uses any ofthe other components on that palette. This bitmap is not required in the layout palette,since it is required only for simulation.

NoteFor more information about the palette function, refer to Component Palette.

Creating the Netlist Include Definition

Netlist Include or Process Component has been discussed in detail in the section NetlistInclude or Process Component.For our example we will use the below present code for making our Netlist includedefinition.For creating the Netlist include definition, follow the below mentioned steps:

Open a text editor.1.Copy the coded text as per given below into a new file.2.

defun SAMPLEKIT_process_netlist_cb

(

cbP,

cbData,

instH

)

{

decl net="";

decl modelFileList;

decl parmStr = NULL;


modelFileList = get_dir_files(SAMPLEKIT_CIRCUIT_MODELS_DIR, "net");


decl instIter = db_create_inst_iter(context);

decl compName = db_get_instance_component_name(instIter);

parmStr = dm_format_instance_data( instH, compName, analogRFnet,

"%b%r%8?%29?%:%30?%p\n%:%k%?[%1i]%;=%p\n%;%;%;%e%e" );

decl parmList = parse( parmStr, "\n", NULL, TRUE );

decl parm;


{


SAMPLEKIT_PATH, car(modelFileList)));


}

while ( is_list(parmList) && parmList ) {

parm = car( parmList );

net = strcat(net, "", parm, netlist_newline() );

parmList = cdr( parmList );

}

return(net);

}

/*--- item-definition --------------------------------------------------------*/

create_item("SAMPLE_NETLIST_INCLUDE", // name

"Process Netlist Include", // description label

"NetlistInclude", // prefix

ITEM_UNIQUE|ITEM_GLOBAL, // attributes

NULL, // priority

NULL, // iconName


NULL, // dialogData

ComponentNetlistFmt, // netlist format string







list(dm_create_cb(ITEM_NETLIST_CB, "SAMPLEKIT_process_netlist_cb", "", TRUE))

);

Save the new file as $HOME/SampleKit/circuit/ael/SAMPLE_NETLIST_INCLUDE.ael.3.


138

Using the Netlist Include as a Default Design

ADS2011 has a feature wherein components from particular designs can be netlisted intothe top design of any circuit simulation, that uses a component from the library. For ourSampleKit, since the NetlistInclude component doesn't have any editable parameters, theuser needs to place this component in every simulation. So to save time and effort, wehave added the SAMPLE_NETLIST_INCLUDE as a Default Design (see cellDefaultDesign_Netlist_Include)For adding this default design to your design kit follow the following steps:

Open SampleKit_wrk workspace which was created previously.1.Add a new cell named DefaultDesign_NetlistInclude and a schematic view for this cell2.in kit's main library SampleKit.A schematic view opens up. In the schematic view place the3.SAMPLE_NETLIST_INCLUDE component and save the design.In the ADS Main window, go to Options > Technology > Defaults Designs, select4.your library SampleKit from the dropdown.Click Add defaults Design and choose the design you just created above. Click OK.5.

You should now have a default schematic design in your design kit. The cell will be locatedin the design kit's main library$HOME/SampleKit/SampleKit/%Default%Design_%Netlist%Include.To verify that all the steps above have been performed correctly, create a new workspaceusing this design kit and try simulating your sample_fet component without placing thenetlist include component separately. The simulation should work, otherwise debug ifthere has been any error in performing the abovementioned steps.

Creating Templates

There two types of templates -

Simulation templates -A simulation template can facilitate setting up common1.simulations.Data display templates - A data display template can contain a standard set of plots2.that can be used in different workspaces.

To create a template first create a templates folder inside the SampleKit\circuit1.directory of design kit.Now in the workspace go to File > New > Library... optionafter which a New_Library_Wizard dialog box will open up.


139

In this library wizard click Next and then name and path of the library to be created2.as shown in the image below.

After performing the above mentioned steps click Next and chose the appropriate3.options and move through the wizard. After you have finished creating a librarynamed library in the SampleKit\circuit\templates folder, open a schematic cell in thatlibrary and make any design template.Save this cell, for example save it as template1 as is done in the SampleKit.4.


140

Note that the name of the library is fixed to be 'library' by the TEMPLATES_DIRECTORYvariable in the eesof_lib.cfg file.

To check whether the above steps have been performed correctly, check theSampleKit\circuit\templates\library folder of your kit, it should now contain a template1folder having the schematic view.

To access this template, create a new workspace including SampleKit, and create a newschematic in it. Now go to Insert->Templates... icon, and a new dialog box opens.Thesaved template for the design can be seen at the top of the dialog box.


141

For more details about Templates please refer to the Templates

Creating an Example Design Using your Design Kit

Now, your design kit is ready for use in designing a circuit.

To use your new design kit:

Restart ADS to make sure all the information is loaded.1.Create a new workspace and a schematic . Name the workspace fet_dc_wrk. Add the2.SampleKit to the workspace.Choose Insert > Template > ads_templates:FET_curve_tracer to place an3.instance of the FET_curve_tracer template on your schematic page.Using the FET and Include components from your design kit, complete the schematic4.as shown in Example Schematic.Note that the Include component is not explicitly required if you have already createdthe Default Design as described above.

Example Schematic

Simulate the circuit. Your plot should be similar to the plot shown in IDS.i vs. VDS5.Simulation Results.


142

IDS.i vs. VDS Simulation Results

Save the design and the data display. Call them fet_dc and fet_dc.dds respectively.6.Using the File > Archive Workspace... menu pick from the ADS Main window,7.archive the workspace. You can now save this workspace if needed.

The SampleKit includes a SampleKit_Demo_wrk, demo workspace in theSampleKit\examples directory.This workspace contains a schematic as well as a drc demodesign.

The schematic design consists of a simple S Parameter circuit for sample_rescomponent of the design kit. This circuit can be used for simulation purposes andshows the calculated Resistance for the resistor in the data display.The Sample_Res_Demo schematic cell is shown below:


143

The drc design consists of flattened layout of the two types of resistors: res1 andres2.This desing is used for DRC purpose. The explanation about this design iscontained in the design itself.The Sample_DRC_Demo schematic cell is shown below:

This completes the first part of the tutorial. You have now created a simple design kit. Youcould, at this point, refer to Packaging for Distribution to prepare your design kit fordistribution to an end user.

The last part of the tutorial will cover the following topics:


144

Adding Components to the Component Library Dialog

Adding Demand Loaded Components

Using a Subcircuit Model

Accessing the Supplied Sample Kit

Adding Components to the Component Library Dialog

This is an optional step. If you choose to access your components from the componentpalette only, you may skip this step. The many advantages of the Component Librarydialog, especially when using the control and records files, are outlined in ComponentPalette vs. Component Library Dialog. Information is also provided to help you decide ifyou should use the Component Library dialog in its simple form, complex form, or not atall.

Setting Up Control and Records Files

This method for defining libraries for the Component Library dialog consists of setting up acontrol file and a set of one or more records files. For more information on the details ofthe file formats, refer to Component Library Dialog.

To setup the control file, SampleKit/circuit/records/SampleKit_library.ctl:

Open a text editor and create the file shown below.1.


<LIBRARIES>

<LIBRARY>

<NAME>SampleKit</NAME>

<CATEGORY>DL</CATEGORY>

<SUBLIBRARY>

<NAME>SampleKit Components</NAME>

<RECORD_FILES>SampleKit_library_brows.rec</RECORD_FILES>

<PLACEMENT>BOTH</PLACEMENT>

</SUBLIBRARY>

</LIBRARY>

</LIBRARIES>

Save the new file as SampleKit_library.ctl in the $HOME/SampleKit/circuit/records2.directory.Continue to the next section to write the records file.3.

To create the records file, which is referred to in the control file shown above:

In a text editor, create the file1.SampleKit/circuit/records/SampleKit_library_brows.rec, as shown below.


<COMPONENTS>

<COMPONENT>

<NAME>SAMPLE_NETLIST_INCLUDE</NAME>

<DESCRIPTION>Process Netlist Include</DESCRIPTION>

<LIBRARY>SampleKit</LIBRARY>

<PLACEMENT>NOLAYOUT</PLACEMENT>

<VENDOR>Agilent Technologies</VENDOR>

<URL>http://www.agilent.com</URL>

</COMPONENT>

<COMPONENT>

<NAME>sample_fet</NAME>

<DESCRIPTION>Low Noise FET</DESCRIPTION>





</COMPONENT>


145

</COMPONENTS>

Save the new file as SampleKit_library_brows.rec, in the2.$HOME/SampleKit/circuit/records directory.After saving both the control and records files, restart ADS. The SampleKit_library.ctl3.and SampleKit_library_brows.rec files will be located if their location has beendefined in the Library Browser tab of the Library Configuration Editor as described inCreating eesof_lib.cfg file.Open a workspace and a schematic window.4.Access the Component Library dialog and verify that the library is now called5."SampleKit".

NoteThe format of the control and records files is very strict. Each space, bracket and slash is very important.If you do not see your library in the Component Library dialog, check your files very carefully against thefiles shown above. Correct any errors that you may find and restart ADS.

To make it easier to see your library, collapse all libraries from the toolbar by clicking theCollapse Libraries icon in the Component Library/Schematic dialog box.

NoteIf you created the Default Design as described in Using the Netlist Include as a Default Design above, youwill also see that in the library browser in the library SampleKit, since all cells in the library are displayedthere.

Adding Demand Loaded Components

This step is also optional.You can specify that components in your designkit be loaded only when they are selectedfor placement. This is called demand-loading.

As described in Demand Loaded Components, one more file can be added to the$HOME/SampleKit/SampleKit/sample_fet directory. This file is called an itemdef.ael andcontains the item definitions created in the sample_fet.ael file in the circuit/ael folder.

NoteWhen the item definition is modified from the Design Parameters dialog box, the itemdef.ael file getsoverwritten. No functions, comments, declarations, global variables, formatting, etc. are preserved. Also,the Design Parameter dialog box does not support editing of custom item definitions. So this demandloading technique should only be used for read-only libraries.

The advantages of using an item definition file are:

Dynamic loading of componentsFaster loading speedLower memory usageWhen the item definition file (itemdef.ael) is used, components are loaded into ahash table and then loaded into ADS only when needed. For a large kit, there is asubstantial loading time and memory usage savings.

For the next step in the tutorial,

Open a text editor and create a file in the $HOME/SampleKit/SampleKit/sample_fet1.directory called itemdef.ael. This file will be used to contain the item definition of thecomponent.Copy the content(variables, forms, formsets, callbacks, item definition) of the2.sample_fet.ael file in the ciruit/ael directory to the file itemdef.ael.The section on Demand Loaded Components describes how the create_item()function call must be the last function in the block of functions related to eachcomponent. The program hpedlibgen uses the end of this function as the key to startreading the next item.

To test the file, follow the steps below to remove the other methods of defining item


146

definitions that have been described so far in the tutorial.

Move the file circuit/ael/sample_fet.ael away to a safe place outside of the design kit1.directory.Edit the file de/ael/boot.ael and comment out the line to load sample_fet.ael as2.shown below.// load(strcat(SAMPLEKIT_PATH, "/circuit/ael/sample_fet"));

Note that comment characters in AEL are two forward slashes at the beginning of theline (//) or the traditional C programming slash and asterisk pair delimiting acomplete block of code (/* this text is commented out */).

Restart ADS to make sure the components are still available and can be placed from thepalette and from the Component Library dialog.

You will notice that the itemdef.atf gets created only when the component is placed on theschematic, and not when the library is loaded. This verifies demand-loading of thatcomponent.You may undo the changes done in this section, as demand-loading is generally requiredfor kits with a large number of components.

Using a Subcircuit Model

This section has been added as an assignment for the user. The subcircuit basedcomponent is not available in the SampleKit.The section on Adding a Model File explains how to set up a component that refers to amodel card in an included netlist file. It is also possible to use a subcircuit model in thesame manner if a simple model card is not sufficient to represent the model.

The files or code fragments listed here can be added to the design kit created in thetutorial as an example of a subcircuit model for the Resistor.

Add new files for the Resistor component, following the similar process as used for makingthe FET component:

circuit/ael/sample_res.ael - add the new item definition

circuit/bitmaps/sample_res.bmp - add new bitmaps

circuit/models/res1.net - add new model file

circuit/models/res2.net - add new model file

circuit/records/SampleKit_library_brows.rec file - add component sample_res in library browser

SampleKit/SampleKit - Create a symbol view named sample_res

de/ael/palette.ael - add component sample_res in palette

The new content for each file is listed below. Refer to the earlier sections in the tutorial fora reminder of the steps required to update the sample kit.

The steps below, provide a general outline of the process.

Add the new item definition to circuit/ael/sample_res.ael as shown in1.my_design_kit/circuit/ael/sample_res.ael.

/*----------------------------------------------------------------------------+/

FILE : sample_res.ael





item definition

/+----------------------------------------------------------------------------*/


decl sample_res_type_default = "sample_res_Mesa";

decl sample_res_R_default = 100;

decl sample_res_w_default = 20e-6;

decl sample_res_Rsh_default = 250;

decl sample_res_ranges = list("1",list( 25, 10000,5e-6,50e-6),


147

"2",list(5, 2000,5e-6,50e-6)) ;

/*--- forms and formsets -----------------------------------------------------*/

// Type

create_constant_form("sample_res_Mesa", "1", 0, "res1", "res1");

create_constant_form("sample_res_NiCr", "2", 0, "res2", "res2");

create_form_set("sample_formset_res_type",

"sample_res_Mesa",

"sample_res_NiCr");

/*--- netlist callback function ----------------------------------------------*/

defun sample_res_calc_l(type,R,w,Rsh)

{

if (type=="1")

{

Rsh=250;

}

else if (type=="2")

{

Rsh=50;

}

decl l=((R*w*1e6)/Rsh);

return(l);

}

defun sample_res_calc_R(type,w,l,Rsh)

{

if (type=="1")

{

Rsh=250;

}

else if (type=="2")

{

Rsh=50;

}

decl R=((l/w)*Rsh);

return(R);

}

defun sample_res_parm_defaultValue_cb

(

cbP,

parmName,

parmDefP

)

{

decl parmH = NULL;

if (parmName == "l")

{

decl formLabel;


decl formDefP = dm_find_library_form("SampleKit", sample_res_type_default);

formLabel = dm_form_get_label(formDefP);

decl l = sample_res_calc_l(

formLabel,sample_res_R_default,sample_res_w_default,sample_res_Rsh_default);

l = round(l*1.0e1)*1.0e-1;

parmH = prm("StdForm", sprintf("%g um", l));

l=l*1e-6;

}

/*--- return to calling function -------------------------------------------*/

return(parmH);

}

defun sample_res_parm_modified_cb

(

cbP, // callback function pointer

parmName, // clientData

itemInfoP // itemInfo pointer

)

{

decl parmList = NULL;

decl type;

decl rangeList;

decl checkVal;

decl Mess1="Calculated length is less than the minimum allowed.\nSetting length to

minimum and\nadjusting resistance.";

decl Mess2="Calculated length is greater than the maximum allowed.\nSetting length to

maximum and\nadjusting resistance.";

//--- calculate dependent parameter values ---------------------------------

type = pcb_get_form_value(itemInfoP, "Type");

rangeList = car(cdr(member(type, sample_res_ranges)));

decl w= pcb_get_mks(itemInfoP, "w");

decl l = pcb_get_mks(itemInfoP, "l");

decl Rsh = pcb_get_mks(itemInfoP, "Rsh");

decl R=pcb_get_mks(itemInfoP,"R");

if (listlen(rangeList)==4)

{

if (parmName == "R" || parmName == "Type")

{

decl var_present = pcb_get_parm_type(itemInfoP, "R");


{

decl R = pcb_get_mks(itemInfoP, "R");

checkVal=SampleKit_v1_parm_checkRange("Resistance", R, nth(0, rangeList),

nth(1, rangeList), "Ohm");

if(checkVal != R && var_present=="NUMBER")


148

{

R=checkVal;

parmList = pcb_set_mks(parmList, "R", R);

}

else if(checkVal != R)

{

R=checkVal;


}

else

{

decl l = sample_res_calc_l( type, R, w,Rsh);

l = round(l*1.0e1)*1.0e-1;

parmList = pcb_set_mks(parmList, "l", l);

l=l*1e-6;


if(l<4.9999e-6)

{

l=5e-6;

parmList = pcb_set_mks(parmList,"l",l);

de_info(Mess1);

decl R=sample_res_calc_R(type,w,l,Rsh);

R = round(R*1.0e2)*1.0e-2;


}

else if(l>200e-6)

{

l=200e-6;


de_info(Mess2);


R = round(R*1.0e2)*1.0e-2;


}

}

if (type=="1")

{

Rsh=250;

}

else if (type=="2")

{

Rsh=50;

}

parmList = pcb_set_mks(parmList, "Rsh", Rsh);

}

}

if (parmName=="w" || parmName == "Type")

{

decl var_present1 = pcb_get_parm_type(itemInfoP, "w");

if (var_present1 != NULL)

{

decl w=pcb_get_mks(itemInfoP, "w");

checkVal=SampleKit_v1_parm_checkRange("Width", w, nth(2,

rangeList), nth(3, rangeList), "um");

if(checkVal != w && var_present1=="NUMBER")

{

w=checkVal;

parmList = pcb_set_mks(parmList, "w", w);

}

else if(checkVal != w)

{

w=checkVal;


}

else

{

w =SampleKit_v1_parm_checkStep("w",w,0.1e-6,"um");


decl l = sample_res_calc_l( type, R, w,Rsh);

l = round(l*1.0e1)*1.0e-1;


l=l*1e-6;


if(l<4.9999e-6)

{

l=5e-6;


de_info(Mess1);


R = round(R*1.0e2)*1.0e-2;


}

else if(l>200e-6)

{

l=200e-6;


de_info(Mess2);


R = round(R*1.0e2)*1.0e-2;



149

}

}

if (type=="1")

{

Rsh=250;

}

else if (type=="2")

{

Rsh=50;

}

parmList = pcb_set_mks(parmList, "Rsh", Rsh);

}

}

}

return(parmList);

}

/*--- item definition --------------------------------------------------------*/

create_item("sample_res", // name

"Resistor", // description label

"R", // prefix

16, // attributes

NULL, // priority

NULL, // iconName


NULL, // dialogData

CmpModelNetlistFmt, // netlist format string







create_parm( "Type", // name

"1-->Mesa :2-->NiCr", // label

PARM_DISCRETE_VALUE, // attrib

"sample_formset_res_type", // formSet


prm("sample_res_Mesa"), // default value

list(dm_create_cb(PARM_MODIFIED_CB,

"sample_res_parm_modified_cb",

"Type",

TRUE)

)

),

create_parm( "R", // name

"res1--> 25 to 10000 Ohm : res2--> 5 to 2000 Ohm", // label

PARM_OPTIMIZABLE|PARM_STATISTICAL, //

attrib

"StdFileFormSet", //

formSet

RESISTANCE_UNIT, //

unit code

prm("StdForm", "100"), //

default value



"R",

TRUE)

)

),

create_parm( "w", // name

"Width: 5 um to 50 um", // label




prm("StdForm", "20 um"), // default value



"w",

TRUE)

)

),

create_parm( "l", // name

"Minimum Calculated lenght is 5um and Maximum is 200 um", // label

PARM_NOT_NETLISTED|PARM_NOT_EDITED, // attrib



prm("StdForm", "8 um"), // default

value

list(dm_create_cb(PARM_DEFAULT_VALUE_CB,

"sample_res_parm_defaultValue_cb",

"l",

TRUE)

)

),

create_parm( "Rsh", // name

"Sheet Resistance:(res1=250 Ohm/sq , res2=50 Ohm/sq) ",// label

PARM_NOT_EDITED|PARM_NO_DISPLAY, // attrib



prm("StdForm", "250"), // default value


150

)

);

Add the new bitmaps (see SampleKit/circuit/bitmaps/sample_res.bmp) to the2.directory.

SampleKit/circuit/bitmaps/sample_res.bmp

Add the new model to the model files circuit/models/res1.net and res2.net as shown3.below.For res1.net:

define res1 (_n22 _n33)

parameters R=100 w=10 um

R:R1 _n22 _n33 R=R Noise=yes

Rsh=250

l=(R*w)/Rsh

x=l*1e6

a1 = 0.0011748815

b1 = 0.00015274375

c1 = -2.0040801e-006

d1 = 1.3379705e-008

e1 = -2.8885036e-011

a2 = -0.0008425464

b2 = 0.0006177481

c2 = -1.0672771e-005

d2 = 5.9932898e-008

e2 = 1.779622e-010

C:C1 _n11 0 C=Cr1 pF


L:L1 _n11 _n22 L=Lr1 nH

L:L2 _n33 _n44 L=Lr1 nH

Cr1=(a1+b1*x+c1*x^2+d1*x^3+e1*x^4)

Lr1=(a2+b2*x+c2*x^2+d2*x^3+e2*x^4)

end res1

For res2.net:

define res2 (_n12 _n13)

parameters R=100 w=5 um

R:R1 _n12 _n13 R=R Noise=yes

Rsh=50

l=(R*w)/Rsh

x=l*1e6

a1 = 0.00083292396

b1 = -4.1306814e-006

c1 = 7.8650954e-007

d1 = -5.440526e-009

e1 = 1.2563758e-011

a2 = 0.0065446601

b2 = -0.00036561786

c2 = 3.0868581e-005

d2 = -6.7416894e-007

e2 = 4.7407417e-009



L:L1 _n11 _n12 L=Lr1 nH

L:L2 _n13 _n14 L=Lr1 nH

Cr1=(a1+b1*x+c1*x^2+d1*x^3+e1*x^4)

Lr1=(a2+b2*x+c2*x^2+d2*x^3+e2*x^4)

end res2

NoteIn the files above, res1.net and res2.net, the define keyword is used to define a subcircuit model.ADS does not support nested subcircuits, so another define cannot be included before the matchingend keyword. A design kit user can inadvertently cause this to happen. See Avoiding Illegal NestedSubcircuits for tips on how to prevent this from happening.

Add the new component to the records file circuit/records/mykit.rec as shown in4.SampleKit/circuit/records/SampleKit_library_brows.rec.

<COMPONENT>

<NAME>sample_res</NAME>

<DESCRIPTION>Resistor</DESCRIPTION>



151




</COMPONENT>

If you would also like to create a top level circuit, e.g. a single resistor which is theseries combination of res1 and res2 defined above, see steps 5-7 below. Otherwisejump to step 8.Open SampleKit_wrk workspace which was created previously.5.Add schematic view to the already existing symbol view of sample_res in the design6.kit's main library.Open the schematic view and make a subcircuit as shown in the figure below and7.save it. You may add parameters to the top-level component, but that is not neededfor this exercise

Add the new component to the de/ael/palette.ael file as shown below.8.

/*----------------------------------------------------------------------------+/

FILE : palette.ael

COMMENTS : creates component palette

/+----------------------------------------------------------------------------*/

set_design_type(analogRFnet);

de_define_library_palette("SampleKit",SCHEMATIC_WINDOW, "analogRF_net", "SampleKit",

"SampleKit", 0

,list(

"SampleKit"

,"SAMPLE_NETLIST_INCLUDE"

,""

,"Process Netlist Include"

,strcat(SAMPLEKIT_CIRCUIT_BITMAP_DIR, "SAMPLE_NETLIST_INCLUDE")

)

,list(

"SampleKit"

,"sample_res"

,""

,"Resistor"

,strcat(SAMPLEKIT_CIRCUIT_BITMAP_DIR, "sample_res")

)

,list(

"SampleKit"

,"sample_fet"

,""

,"Low Noise FET"


)

);

de_define_library_palette("SampleKit",LAYOUT_WINDOW, "analogRF_net", "SampleKit",

"SampleKit", 0

,list(

"SampleKit"

,"sample_res"

,""

,"Resistor"

,strcat(SAMPLEKIT_CIRCUIT_BITMAP_DIR, "sample_res")

)

,list(

"SampleKit"

,"sample_fet"

,""

,"Low Noise FET"


)

);


152

The new component would now be available as subcircuit based component.9.You can also add a layout for this component, if required. For adding the layout10.follow a similar process, as the one previously mentioned in the tutorial, for thesample_fet component.To check its functioning you can open a workspace and try pushing into the11.component or verifying the netlist. You can also use it in your simulation to verifythat it gives the correct resistance, i.e. sum of resistances of res1 and res2.

Avoiding Illegal Nested Subcircuits

ADS does not support nested subcircuits. Nested subcircuits will occur in a netlist when ahierarchical schematic has an include component that includes a file with a subcircuit usedin any level of hierarchy other than the top level.As part of the netlist callback you should include pre-processor commands that allow onlythe first include statement to be used by the simulator. This is important if the user addsmultiple instances of the include schematic in a design. If the model file is included morethan once a redefinition error will occur. Using pre-processor commands will avoid thisproblem by limiting the include to the first instance in the netlist.

Example netlist

#ifndef SAMPLE_NETLIST_INCLUDE|

#define SAMPLE_NETLIST_INCLUDE

#include "/fet1.net.net"

#endif

For more information on the pre-processor commands, refer to Model Files .

If more than you netlist include component is used in the design, there could be confusionas to which component is used. It is not straightforward to define which component will benetlisted first in a hierarchical design. Your design kit instructions should include a warningthat includes components only be placed once, at the top-most, analog schematic of thedesign hierarchy. To further prevent multiple components, use the ITEM_UNIQUE attributein the create_item() function call. This will prevent the user from placing more than onenetlist include component in a single schematic. In a hierarchical design it is not possibleto limit the number of netlist include components, since the schematic design files can beused in multiple designs.

NotePrevious versions of the Design Kit Development documentation recommended using theITEM_NOT_NETLISTED_IF_SUB attribute with netlist include components to avoid nested subcircuits. Thiscan create a issue if the top-level schematic is a digital schematic, since design kit components are notvalid on digital schematics. Agilent EEsof EDA recommends using the method described above for avoidingillegal nested subcircuits.

Creating Component and Menu Documentation

The specific documentation for components and menus is an optional part of the designkit. This documentation can be added if you would like to give the user a good know-howabout the details of the components and menus in the design kit.One can also refer to Creating Design Kit Documentation for detailed step-by-stepprocedure of creating the documentation.

To create component help -

Create a new subdirectory for your component documentation under your design kit1.doc directory. For example:cd $HOME/SampleKit/doc


153

mkdir component_docCreate the HTML documentation for your components and save your files in the new2.directory. For example, if you have a component called sample_res, save yourdocumentation file as:$HOME/SampleKit/doc/component_doc/sample_res.htmlYou can refer to the sample_res.html provided with the SampleKit for referring tocontent of this file.The next step in adding the Documentation is adding the help server index files:3.hsSampleKit_index. This file will link the component with its document page.For knowing how to create these files, please refer to Adding Help for Componentsand Adding Help for Custom Design Kit Menus .Copy the following text in the hsSampleKit_index.

# Name: SampleKit

# Version: 1.0

sample_res ! component_doc/sample_res.html !

SAMPLE_NETLIST_INCLUDE ! component_doc/SAMPLE_NETLIST_INCLUDE.html !

sample_fet ! component_doc/sample_fet.html !

To create menu help -

Create a new subdirectory for your menu documentation under your design kit doc1.directory. For example:Note that this step is optional, and in the SampleKit, these documents have beensaved directly in the doc directory.Create the HTML documentation for your menus and save your files in the new2.directory. For example, if you have a menu for schematic, save your documentationfile as:$HOME/SampleKit/doc/index_samplekit_sch.htmYou can modify the index_samplekit_sch.htm provided with the SampleKit.The next step in adding the Documentation is adding the help server index files:3.hsSampleKitMenu_index. This file will link the menu with its document page.For knowing how to create these files, please refer to Adding Help for Componentsand Adding Help for Custom Design Kit Menus .Copy the following text in the hsSampleKitMenu_index.4.

# ---------------------------------------------

# Index file for ADS Help Server

# ---------------------------------------------

Schematic ! index_samplekit_sch.htm !

Layout ! index_samplekit_lay.htm !

Main ! index_samplekit_main.htm !

Finally you would need to create a menu.ael file which would be used to define the5.way in which the Menu Help would work.Following is the text which you can use inthe menu.ael file:

// Filename: menu.ael

// --------------------------------------------------------

// CREATE MENU FUNCTION TO HANDLE MENU CREATION BASED ON

// WINDOW TYPE

// --------------------------------------------------------


defun SampleKit_sch_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Schematic");

}


defun SampleKit_lay_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Layout");

}


defun SampleKit_main_menu_cb(cbData, callData, winInstP)

{

de_invoke_help("SampleKitMenu","Main");

}

defun SAMPLEKIT_add_custom_menus(winType)

{

if (winType == MAIN_WINDOW)

{

decl mainMenuH, mainMenuPickH;

// If main menu doesn't already exist, create it.


154

if (!(mainMenuH = api_find_menu(NULL, "SampleKit")))

{

mainMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Main Menu"

,API_MA_TEAROFF

,NULL

);

if (mainMenuH) api_add_menu(NULL, mainMenuH);

}

// If main menu, nested menu doesn't exist, create it.

if (!(mainMenuPickH = api_find_menu(mainMenuH, "About SampleKit")))

{

mainMenuPickH = api_create_menu("About SampleKit"

,"About SampleKit"

,"SampleKit_main_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (mainMenuPickH) api_add_menu(mainMenuH, mainMenuPickH);

}

// Display main menu

api_menu_manage(mainMenuH, TRUE);

api_menu_manage(mainMenuPickH, TRUE);

}

else if (winType == SCHEMATIC_WINDOW)

{

decl schematicMenuH, schematicMenuPickH;

// If schematic menu doesn't already exist, create it.

if (!(schematicMenuH = api_find_menu(NULL, "SampleKit")))

{

schematicMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Schematic Menu"

,API_MA_TEAROFF

,NULL

);

if (schematicMenuH) api_add_menu(NULL, schematicMenuH);

}

// If schematic menu, nested menu doesn't exist, create it.

if (!(schematicMenuPickH = api_find_menu(schematicMenuH, "About SampleKit

Schematic")))

{

schematicMenuPickH = api_create_menu("About SampleKit Schematic"


,"SampleKit_sch_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (schematicMenuPickH) api_add_menu(schematicMenuH, schematicMenuPickH);

}

// Display schematic menu

api_menu_manage(schematicMenuH, TRUE);

api_menu_manage(schematicMenuPickH, TRUE);

}

else if (winType == LAYOUT_WINDOW)

{

decl layoutMenuH, layoutMenuPickH;

// If Layout menu doesn't already exist, create it.

if (!(layoutMenuH = api_find_menu(NULL, "SampleKit")))

{

layoutMenuH = api_create_menu_cascade("SampleKit"

,"Sample Kit Layout Menu"

,API_MA_TEAROFF

,NULL

);

if (layoutMenuH) api_add_menu(NULL, layoutMenuH);

}

// If Layout menu, nested menu doesn't exist, create it.

if (!(layoutMenuPickH = api_find_menu(layoutMenuH, "About SampleKit Layout")))

{

layoutMenuPickH = api_create_menu("About SampleKit Layout"


,"SampleKit_lay_menu_cb"

,SAMPLEKIT_NAME

,NULL

,NULL

);

if (layoutMenuPickH) api_add_menu(layoutMenuH, layoutMenuPickH);

}

// Display Layout menu

api_menu_manage(layoutMenuH, TRUE);

api_menu_manage(layoutMenuPickH, TRUE);

}

}

// Name of AEL menu creation function provided by the design kit

dk_register_menu_function("SAMPLEKIT_add_custom_menus");


dk_register_menu_name(MAIN_WINDOW, list("SampleKit"

,"About SampleKit"

));


155

dk_register_menu_name(SCHEMATIC_WINDOW, list("SampleKit"


));

dk_register_menu_name(LAYOUT_WINDOW, list("SampleKit"


));

Save menu.ael file in the $HOME/SampleKit/de/ael folder, and add the following line inthe boot.ael file:load(strcat(SAMPLEKIT_DE_AEL_DIR, "menu"));

Once the above mentioned steps are complete you can check the working of these helpfiles by following the below mentioned steps:

Place an instance of your component on a schematic or layout.1.Double-click the component to launch the ADS Edit Component dialog box.2.Click the Help button in the Edit Component dialog box. Your documentation should3.now be displayed in your browser window.Now use the SampleKit menu on the ADS Main, Schematic and Layout window, to4.check if the correct help is displayed.

Adding DRC

Adding DRC to the design kit is an optional feature.It is used to check design rules on thekit components.A DRC error is flagged if a particular component is not complying with theDRC rules.For creating DRC for the design kit follow the below mentioned steps:

Create a new text file in SampleKit\drc\rules directory and save it as setrule.ael after1.copying the following code into the file.

// Rule Registry File

dve_set_rule_list(list(

"SampleKit : Off-Grid Rules", "Offgrid_rule.ael",

"SampleKit : Resistor Width Rules", "Res_width_rule.ael"

));

This file provides the list of drc rule files to the Design Rule Check dialog box.2.In the SampleKit\drc\rules folder of your design kit open a new text file.3.Copy the following code into the file.4.

//Import Layers

decl mesa = dve_import_layer("mesa");

decl nicr = dve_import_layer("nicr");

decl Via_Nit1 = dve_import_layer("Via_Nit1");

decl M0 = dve_import_layer("M0");

decl Via0_1 = dve_import_layer("Via0_1");


decl Via1_2 = dve_import_layer("Via1_2");


decl Via_Pass = dve_import_layer("Via_Pass");

decl BVia = dve_import_layer("BVia");

decl demo_dummy = dve_import_layer("demo_dummy");

decl Border = dve_import_layer("Border");

// declare output error layer

decl lyr_DRC_error = dve_export_layer(36);

/****************** OFF-GRID RULES****************************/

// mesa Off-Grid

lyr_DRC_error += dve_drc (off_grid (mesa, 0.01),

"mesa Layer is off grid");

// nicr Off-Grid

lyr_DRC_error += dve_drc (off_grid (nicr, 0.01),

"nicr Layer is off grid");

// Via_Nit1 Off-Grid

lyr_DRC_error += dve_drc (off_grid (Via_Nit1, 0.01),

"Via_Nit1 Layer is off grid");

// M0 Off-Grid

lyr_DRC_error += dve_drc (off_grid (M0, 0.01),

"M0 Layer is off grid");

// Via0_1 Off-Grid

lyr_DRC_error += dve_drc (off_grid (Via0_1, 0.01),

"Via0_1 Layer is off grid");

// M1 Off-Grid


156



// Via1_2 Off-Grid

lyr_DRC_error += dve_drc (off_grid (Via1_2, 0.01),

"Via1_2 Layer is off grid");

//M2 Off-Grid



// Via_Pass Off-Grid

lyr_DRC_error += dve_drc (off_grid (Via_Pass, 0.01),

"Via_Pass Layer is off grid");

//BVia Off-Grid

lyr_DRC_error += dve_drc (off_grid (BVia, 0.01),

"BVia Layer is off grid");

// Border Off-Grid

lyr_DRC_error += dve_drc (off_grid (Border, 0.01),

"Border Layer is off grid");

Save this file as Offgrid_rule.ael in that location.This file would check the offgrid error5.present in the components of the design kit.

You can check the working of the DRC files by running them on the layout and checking ifthe errors are being caught on the designs that do not comply with these rules.For more information on how to run DRC, see DRC Quick Start.

NoteThe SampleKit also contains another DRC file, Res_width_rule.ael, which uses the Layers and PurposesPairs (LPPs) to distinguish between 2 different kind of resistors in the PDK.

Accessing the Supplied Sample KitA copy of the completed tutorial design kit is available with the ADS design kit software.This can be used to compare the files as you build them in the tutorial. However, since thetutorial builds the files slowly, it is recommended that you go through the process asdescribed in the tutorial.

The sample design kit is located in:

$HPEESOF_DIR/examples/DesignKit/SampleKit


157

Design Kit Development for RFICDynamic LinkThis section describes general information related to design kits created for use in theRFIC Dynamic Link Flow between Advanced Design System and Cadence DFII.

RFIC Dynamic LinkThe RFIC Dynamic Link is an EDA framework integration product based on Inter-ProcessCommunication (IPC), rather than data file translation, maximizing data integrity and easeof use. The Dynamic Link enables you to create a design in the Cadence EDA frameworkand then simulate your design in Advanced Design System. This provides you with thepowerful capabilities of both EDA design environments.

RFIC Dynamic Link provides fundamental information on the installation, usage andcustomization of your EDA environment. Ensure that the Dynamic Link is properlyconfigured before attempting to use the product.

Design Kits for RFIC Dynamic LinkADS foundry models have been developed to provide access to a specific process withinAdvanced Design System when using RFIC Dynamic Link. To give the simulator access tothese models, RFIC Dynamic Link recommends that you place a generic includecomponent called NetlistInclude. For more information on the NetlistInclude component,refer to Netlist Include or Process Component. On the include component, you must enterthe name and path of model files to be referenced, as well as specifying any corner caseidentifiers.

When developing a design kit for use in the RFIC Dynamic Link flow, it is recommendedthat you create a custom process component instead of requiring the end user toconfigure the NetlistInclude component. A custom component can contain the names ofthe model files so the end user does not need to know this information. It can also presentthe end user a simple list to select the appropriate corner case based on meaningfulcriteria. This process component, coupled with reusable models or data files, can then beused as the basis for a design kit for use in the ADS Front-End Design Flow.

For an example of this type of process component, refer to Example Process Componentwith Forms and Formsets.


158

Generic Add-on Toolbar KitCustom schematic and layout toolbars are important capabilities that make schematic andlayout editing commands work seamlessly with PDK elements. These toolbars provideeasy access to several important and powerful ADS capabilities to improve efficiency andproductivity.

Generic Add-on Toolbar kit includes the following:

Adding the Generic Add-On Toolbar to your WorkspaceRemoving the Generic Add-On Toolbar from your WorkspaceUsing the Generic Add-on Toolbar

Schematic ToolbarLayout Toolbar

Adding the Generic Add-On Toolbar to yourWorkspaceThis kit is present at $HPEESOF_DIR/examples/DesignKitTo add Generic Add-on toolbar to a workspace, follow the steps mentioned in Adding aPDK from a Workspace

NoteIf the user does not have write permission in the $HPEESOF_DIR then copy the Design kit,Generic_AddOn_Toolbar, from $HPEESOF_DIR/examples/DesignKit to a local directory having writepermission and then add it to your workspace.

Removing the Generic Add-On Toolbar from yourWorkspaceTo remove the Generic Add-on toolbar, follow the steps mentioned at Removing a PDKfrom a Workspace

Using the Generic Add-on Toolbar

Schematic Toolbar

Generic Add-on Toolbar

Schematic Cell having Generic Add-on Toolbar


159


160

Tool Action

About GENERIC Add-OnToolbar

Displays the splash dialog Eesof Generic Add-On Toolbar v2.0. Itdisplays the current version number of the toolbar and the date of release.Click Done after viewing the information.

Select All

Selects everything in the current design.

Deselect All

Deselects all the selected designs.

Deselect Area

Deselects the selected area.

Clear Highlighting

Clears highlighted objects.

Delete ALL SchematicContents

Deletes everything in the current design.

Restore View beforePan/Zoom

Restore the view before Pan/Zoom.

Reposition To Origin

Repositions to the origin.

Insert A Template Into AnExisting Design

Inserts a template into a design. For example, S_Params, S_Params_DC

Insert Quad dB/Smith ChartDisplay Template

Inserts a Display template

Insert template to measureFET Device Characterizationfor existing sub circuit

Performs common standards of measurement for an existing FET sub-circuit design.

Top-level Design Netlist

Creates a netlist file starting at the current design, moving through allreferenced designs

Stop Simulator And ReleaseLicense

Ends a simulation. Also releases the simulation license.

Check Representation

In the Schematic view, the Check Representation command providesaccess to information on any of the following characteristics of your design- Open Connections, Bus Connectivity, Nodal Mismatches, Port/PinMismatches, Parameter Value Mismatches, and Overlayed Components.

Toolbar Help

Provides help on the various functionalities in Toolbar.

Layout Toolbar

Open a new layout window from ADS main window.


161

Layout Toolbar

Tool Action

AboutGENERIC Add-On Toolbar

Displays the splash dialog Eesof Generic Add-On Toolbar v2.0. It displays the currentversion number of the toolbar and the date of release. Click Done after viewing theinformation.

Select All

Selects everything in the current design.

Deselect All

Deselects all the selected designs.

Deselect Area

Deselects the selected area.

ClearHighlighting

Clears highlighted objects.

Delete AllLayoutContents

Deletes everything in the current design.

Restore ViewbeforePan/Zoom

Restore the view before Pan/Zoom.

Select Layerfor NewShapes

Clicking on a shape changes the entry layer to the layer of the shape.

Show LayoutLayers byName

Layout Layers dialog opens displaying all the layers. Select any layer to view it; it makesonly the selected layer visible.


162

Reposition ToOrigin

Repositions to the origin.

Fast GridSpacingToolbox

Adjusts the Grid Snap Distance, Snap Grids per Minor Grids, Minor Grids per Major Grid. Italso lets you turn off or turn on minor and major grids.

Adjust theTransparencysetting

Layer Properties dialog opens on clicking this tool. Select the layer name from Layer Namedrop down list and select the transparency of the selected layer either by moving the slideron the transparency scale (0-100%) or enter the desired value in the edit box. Click Applyand then OK.

Check Design

It provides information about the characteristics of your design such as Open Connections,Nodal Mismatches, Wires in layout, Parameter Value Mismatches, OverlayedComponents, Shapes touch but belong to different nodes, Polygon overlapscomponent without overlapping a pin and Connection is not pin-to-pin. When youclick this tool, Check Design dialog opens and it displays all the warnings based on theOptions... selected. You can select/deselect the options and Refresh the list to view thelatest warnings.


163

You can select any warning from the list to view its details by clicking Details...You can save these warnings as a text file by clicking Save As....You can print these warnings by clicking Print.

Show NodalInterconnect

Highlights all objects at the current level that are connected to the same logical node.

Show PhysicalInterconnect

Highlights all objects that are physically connected, throughout the hierarchy.

Open 3DViewer

Define the substrate stack before opening the 3D viewer. After defining the substrate stack,click this tool. Generating 3D Model dialog opens displaying the progress bar.

Agilent 3D Preview window opens displaying the 3D preview.

Open Selectedin 3D Viewer

Opens 3D viewer for selected items in a design after reading the correct substrate stack.

Invoke DRC

Opens Design Rule Check dialog that lets you run rules by selecting Rule location, Rule file, and Check Area.


164

You can also Create Width/Spacing Rule. Enter Job Name and click Run. DRC Messagewindow opens displaying the status.

View DRCResults

Open the DRC results viewer.

Create Reticle

Creates reticle using step and repeat copies of a single layout design.

Toolbar Help

Provides help on the various functionalities in Toolbar.

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