design criteria for ultra wideband distributed amplifiers...distributed filters tr #0103-01 usc...

TECHNICAL REPORT #0103-01

Design Criteria for Ultra Wideband Distributed Amplifiers

John Choma Professor & Chair (USC)

Department of Electrical Engineering University of Southern California University Park: Mail Code: 0271

Los Angeles, California 90089-0271 213–740–4692 [USC Office] 213–740–7581 [USC Fax]

[email protected]

ABSTRACT: This report presents the analysis of lumped, lossless networks configured to emu-late ideal transmission line characteristics over broad frequency passbands. The filter sections are configured to allow for the realization of distributed amplifiers capable of processing signal frequencies extending through tens of gigahertz. The principle advantage of the distributed approach to broadband amplifier de-sign is that it allows for the incorporation of amplifier cell cascades, which are required for high gain, without incurring the significant bandwidth degradation that arises from the increased input and output port capacitance indigenous to cascade configurations. As a result, impressive amplifier gain-bandwidth prod-ucts are achievable, at least in principle, with monolithic device technologies that do not necessarily offer impressively high unity gain frequencies. A design strategy for the foundational filter realization is developed, and HSPICE simula-tions that confirm the propriety of the adopted design methodology are provided.

February 2004

Distributed Filters TR #0103-01 USC Viterbi School of Engineering

February 2004 2 Choma

I. INTRODUCTION

Deep submicron complementary metal-oxide-semiconductor (CMOS), heterostructure sili-con-germanium (SiGe) bipolar, and other state of the art monolithic device technologies boast unity gain frequencies in the high tens -to- low hundreds of gigahertz. Despite these device re-sources and the continuing maturation of large scale integrated processing and layout technolo-gies, the realization of conventional lumped analog cells featuring reasonably constant gains over bandwidths as large as several gigahertz remains a daunting challenge. This design challenge derives from circuit signal flow paths whose transmission properties are compromised by energy storage elements implicit to the utilized active devices, the circuit architecture, and the circuit layout. Although the literature is rife with circuit compensation measures that promote broad-band network responses[1]-[2], often at the expense of increased noise and power consumption, ac-tive networks featuring gain-bandwidth products exceeding one-fifth -to- one-third of the unity gain frequency for their utilized active elements remain rare. It is both curious and depressing that this ratio of achievable circuit -to- device gain-bandwidth product has not changed substan-tially for silicon-based device technologies over the past three decades.

At least three engineering circumstances compel an investigation of new design methodol-ogies that can mitigate the foregoing gain-bandwidth product anemia in silicon-based, and par-ticularly, monolithic CMOS networks. The most obvious of these circumstances is the perpetually increasing bandwidth requirements imposed by modern wireless and wired data processing, information transmission, and other types of communication systems. For example, the Federal Communications Commission (FCC) recently adopted service rules for the commer-cial use of spectra in the 71-76 GHz, 81-86 GHz, and 92-95 GHz bands[3]. These spectra comple-ment passbands already allocated for industrial, scientific, medical, satellite, mobile radio, and other applications at frequencies ranging from 30 -to- 76 GHz. It is to be noted that even if tuned amplifiers boasting quality factors as high as ten are exploited in these extremely high frequency systems, the recently allocated spectra imply information bandwidths ranging from a low of 3.0 GHz -to- a high of 9.5 GHz. Second, the electronics hardware implicit to these communication systems is seldom exclusively analog or digital in nature. Instead, this hardware is often a mixed signal architecture. Since the digital component of mixed signal architectures destined for al-most all commercial and many military applications is invariably realized in CMOS technology, a CMOS realization of requisite analog subcircuits is expedient from electrical interface and processing perspectives. Third, and despite the omnipresent energy storage parasitics that plague both active and passive devices realized in silicon-based technologies, the amenability of silicon to system-on-chip implementations is an indisputable attribute.

Traditional circuit compensation strategies aimed toward bandwidth enhancement natural-ly focus on mitigating the negative impact of energy storage parasitics that are pervasive of sili-con devices and associated circuit interconnects. Since these broadbanding schemes are unavoidably imperfect in that they themselves forge unwanted poles and zeros, it is only natural to explore new design techniques that productively exploit said parasitics. A clue as to the gen-eral complexion of any new design methods that might be advanced is offered by classic trans-mission line theory[4]. In particular, a uniformly distributed RLC transmission line that is terminated at its output port in the characteristic impedance of the line presents a driving point input impedance that is identical to the terminating characteristic impedance. This is to say that a distributed line whose output port is match terminated effectively behaves as an ideal, zero im-pedance interconnect between the input and output (I/O) ports of the line. Alternatively, it might



be stated that the I/O interconnect of such a distributed structure is impervious to the parasitic re-sistance, inductance, and capacitance that is indigenous to the signal flow path that couples its input and output ports.

The foregoing transmission line observation suggests the propriety of synthesizing an ac-tive distributed architecture that, in addition to emulating the laudable impedance properties of a match terminated passive line, is capable of providing broadband amplification. Such distributed architectures, which are commonly known as distributed amplifiers or traveling wave amplifiers, hardly constitute a new design concept. About five decades ago, distributed amplification was advanced[5], optimized experimentally[6], and subsequently refined analytically[7] to promote va-cuum tube amplifier frequency responses extending into the mid hundreds of megahertz. These seminal contributions implicitly underlie distributed analog signal processing results reported more recently with respect to chip interconnects[8], amplifiers[9]-[11], and oscillators[12]-[14] realized in CMOS technology. Although these recent results are sufficiently encouraging to warrant fur-ther explorations, on chip transmission lines consume inordinately large surface area and even volume, assuming a multilevel metal availability. Moreover, their attainable performance is li-mited by the effects of induced electric fields, which couple to the substrate[15]. Although design care and layout heroics circumvent many of these field coupling problems[16]-[17], surface area problems remain contentious.

This work continues to subscribe to the viability of distributed amplification architectures in CMOS technology, but offers an alternative to the on chip use of conventional transmission lines. In particular, it advances lumped networks that approximate transmission line I/O beha-vior. Although the subject lumped networks do not behave as ideal distributed structures, they do emulate the I/O properties of transmission lines over satisfyingly broad ranges of signal fre-quency and reveal both interesting and insightful circuit theoretic information.

II. TEE NETWORK

Consider Figure (1a), which depicts a generic passive tee structure commonly used to emulate transmission line characteristics. In this network, the output port is terminated in im-pedance Zo(s), and the input port is driven by a signal voltage, Vs, whose Thévenin impedance is likewise Zo(s). The driving point input impedance, Zin(s), seen by the signal source is

1 1in 2 o

Z (s) Z (s)Z (s) Z (s) Z (s) .

2 2

(1)

A necessary condition for the network at hand to emulate transmission line behavior is that Zin(s) be identical to Zo(s). If Zin(s) in (1) is equated to Zo(s), the requisite value of the terminating load impedance, Zo(s), is found to be

1o 1 2

2

Z (s)Z (s) Z (s)Z (s) 1 .

4Z (s)

(2)

Because of network symmetry, a Thévenin source impedance equated to Zo(s), as per the fore-going expression, produces an output impedance, Zout(s), that is likewise identical to Zo(s).

Let the network in Figure (1a) be realized as the RLC configuration shown in Figure (1b), where



Z (s)/21Z (s)o

Z(s)

2

Z (s)in

Z(s)

o

Z (s)/21 Vo

Vp

Vs

(a).

Z (s)o

Z (s)in

Z(s)

o

Vo

Vp

Vs

(b).

L /2 L /2

R C

Z (s)out

Z (s)out

Figure (1). (a). A Generic Passive Tee Network Terminated at Its Output Port In An

Impedance, Zo(s), And Driven At Its Input Port By A Signal Voltage Whose Thévenin Equivalent Impedance Is Also Zo(s). (b). The Network Of (a) With Z1(s) Represented By Inductive Impedance sL, And Z2(s) Supplanted By The Parallel Combination Of Resistance R And Capacit-ance C.

1

2

Z (s) sL

.RZ (s)

1 sRC

(3)

Using (3), (2) becomes

2l

o ol h

s ω sZ (s) R .

1 s ω ω

(4)

In (4), the resistive parameter, Ro, is given by the familiar expression,

oR L C , (5)

lω 1 RC (6)

is the inverse of the high frequency time constant associated with the shunt RC subcircuit in the diagram, and

h oω 2 LC 2 R C . (7)



As is demonstrated shortly, ωh is intimately related to the radial 3-dB bandwidth of the termi-nated network.

If the resistance, R, which effectively shunts the incident path of the tee coupler in Figure (1b) to signal ground is large, the critical frequency, ωl, in (6) is correspondingly small. Since interest in the circuit at hand is directed to its utilization in very high frequency signal paths, it is reasonable to presume ω >> ωl. Note that in a lossless tee structure, where R is infinitely large, ωl is zero, and the foregoing presumption is perfectly valid. It follows that for ω >> ωl,

2o o hZ (s) R 1 s ω , (8)

which collapses to the pure resistance, Ro, when the signal frequencies applied to the tee network are significantly smaller than the frequency, ωh, defined by (7). Thus, the tee filter of Figure (1b) can be coerced into mirroring the I/O impedance characteristics of an ideal transmission line over frequencies that satisfy the dual constraint, ωl << ω << ωh, if its output port is terminated in the resistance, Ro, given by (5). The resultant single section transmission line emulator is offered in Figure (2). It is to be noted that a cascade of many such sections sustains a low frequency driv-ing point input impedance of Ro at the input port of the first section, as well as at the input ports of all interstage sections, as long as the output port of the final section is terminated in resistance Ro.

Z (s) Rin o

Vo

Vp

Vs

L /2 L /2

R C Ro

Ro

Z (s) Rout o

Figure (2). The Tee Network Of Figure (1b) Terminated At Its Input And Output

Port In A Resistance, Ro, Given By (5). The Input And Output Im-pedances Approximate Ro For ωl << ω << ωh, Where ωl And ωh Are Given By (6) And (7), Respectively.

The determination of the transfer functions, Vo/Vs and Vp/Vs, for the circuit in Figure (2) is a straightforward task that is expedited by the reasonable approximation, Ro << 2R. With varia-ble “p” representing the normalized complex frequency, s/ωh, it can be shown that

oo 2 3

s

V 1 2H (p) ,

V 1 + 2p + 2p + p (9)

which is the transfer characteristic of a three pole, maximally flat magnitude (MFM), or Butter-worth, lowpass filter[18]. Because this relationship reflects a Butterworth response, the norma-lized 3-dB bandwidth of the subject filter is one, thereby implying a radial 3-dB bandwidth of ωh. It is interesting to observe that while the ideal, match terminated lossless transmission line pro-vides frequency invariant attenuation for all signal frequencies, the match terminated lumped cir-cuit transmission line approximation in Figure (2) offers nominally constant attenuation for all frequencies through ωh.



On the other hand, the transfer function, Vp/Vs, is the second order function,

pp 2

s

V 1 2H (p) ,

V 1 + p + p (10)

whose quality factor, Q, is precisely one. Because this transfer characteristic is not MFM, it dis-plays frequency response peaking for which the maximum value, Mp, (over and above the zero frequency value of the transfer characteristic) can be shown to be[19],

p

2

Q 2M ,

1 31

4Q

(11)

which is equivalent to a frequency response “overshoot” of about 15.5%. The subject maximum peaking is evidenced at a normalized frequency, say yp, of

pp 2

h

ω 1 1y 1 ,

ω 22Q (12)

or equivalently, at a signal frequency, ωp, that is approximately 30% smaller than the 3-dB bandwidth of the Butterworth filter response defined by (9). Finally, the normalized 3-dB band-width, yb, of the transfer function, Hp(p), is

0

0.1

0.2

0.3

0.4

0.5

0.6

0.01 0.03 0.10 0.32 1.00 3.16 10.00

Normalized Signal Frequency, ( / h)

Magnitude Response

H p (jy)

H o (jy)

3-dB Frequency Marker

Figure (3). Magnitude Responses Of The Lumped Circuit Transmission Line Emulator Depicted

In Figure (2).



2b

b 2 2h

1 5ω 1 1y 1 1 1 ,

ω 22Q 2Q

(13)

thereby implying a radial bandwidth, ωb, that is slightly more than 27% larger than ωh. The sa-lient features of the foregoing disclosures are displayed graphically in Figure (3).

The peaking revealed by the transfer function, Hp(s), comprises unfortunate baggage when adapting the line in question to an active, quasi-distributed network. In particular, a grounded capacitance, C, is incident with the node at which voltage Vp is extracted in Figure (2). As a re-sult, this node is a natural candidate for a grounded source connection of either the gate or the drain terminals of a MOSFET. In the case of a gate connection, for which a three-section active line emulation is abstracted in Figure (4), a component (likely a dominant constituent) of capa-citance C is implicitly the superposition of gate-source, overlap gate-source, gate-bulk, and Mil-ler-modified gate-drain capacitances. For a drain connection, C is dominated by drain-bulk capacitance and influenced to a lesser extent by gate-drain and overlap gate-drain capacitances. Moreover, resistance R in the drain connection case assumes the stature of the small signal chan-nel resistance of each transistor. In the gate connection architecture of Figure (4), the non-monotonic nature of the frequency responses for Vp1/Vs, Vp2/Vs, and Vp3/Vs sustains potentially unacceptable gate-source signal peaking, and thus, small signal drain current peaking in each de-vice. If an analogous quasi-distributed line couples the drain terminals of the indicated transis-tors, this peaking is exacerbated by further frequency response overshoot evidenced in the drain voltage responses of all transistors.

Vp1

Vs

L /2

RoRo

Vp2 Vp3

L L L /2

Figure (4). Basic Schematic Abstraction Of A Three Section Common Source Amplifier. Biasing

Details Are Not Shown. With Reference To Figure (2), Resistance R Is The Very Large Resistance Between Each Gate And Source Terminal, While Capacitance C Is The Net Effective Gate-Source Capacitance Of Each Active Device.

The peaking problems addressed in the foregoing paragraph can be mitigated, but not completely resolved, by the modified tee section shown in Figure (5)[19], where Ro remains given by (5). In this network, parameter m is selected to reduce the amount of frequency response peaking within the passband, which remains limited nominally by radial frequency ωh, as de-fined by (7). For m = 1, the network in Figure (5) reduces to that of Figure (2), for which the ob-served peaking is about 15.5%. Manual analyses and computer simulations confirm that 0.7 ≤ m ≤ 0.8 yields a 4% -to- 5% reduction in peaking. Further decreases in parameter m continue to re-duce the peaking, but at the expense of incurring frequency notches within the passband. The



need of a third inductor -per- filter section hardly justifies the less than inspiring improvement in frequency response.

Z (s) Rin o

Vo

Vp

Vs

mL /2 mL /2

R mC

Ro

Ro

Z (s) Rout o

m

(1 m )L 2

4m

Figure (5). A Modified Version Of The Tee Section Network In Figure (2). Pa-

rameter m Is Selected To Mitigate The Frequency Response Peaking Problems Evidenced In The Former Network.

III. PI NETWORK

An alternative emulation of a distributed line is the generic pi architecture appearing in Figure (6a), which is realized as the RLC network shown in Figure (6b). Note that only one in-ductor appears in this circuit, whereas two are deployed in the tee structure considered in the preceding section. The driving point input impedance, Zin(s), as well as the driving point output impedance, Zout(s), is given by

Z (s)o

2Z(s)

1

2Z(s)

1

Z (s)in

Z(s)

o

Z (s)2 Vo

Vs

(a).

Z (s)o

Z (s)in

Vs

(b).

L

2R 2RC/2 C/2

Z (s)out

Z(s)

o

Vo

Vp

Z (s)out

Figure (6). (a). A Generic Passive Pi Network Terminated at Its Output Port In An Impedance,

Zo(s), And Driven At Its Input Port By A Signal Voltage Of Internal Impedance Is Zo(s). (b). The Network Of (a) With Z1(s) Represented By The Parallel Combination Of Resis-tance 2R And Capacitance C/2, And Z2(s) Supplanted By The Inductive Impedance, sL.



in 1 2 1 oZ (s) 2Z (s) Z (s) 2Z (s) Z (s) . (14)

The value of Zo(s) that renders Zin(s) = Zo(s) can be shown to be

1 2o

2

1

Z (s) Z (s)Z (s) .

Z (s)1

4Z (s)

(15)

With Ro and ωh defined by (5) and (7), respectively, it can be shown that the application of (15) to the network in Figure (6b) results in

oo

2

h

RZ (s) ,

s1

ω

(16)

provided Ro << 2R. If Zo(s) is set to resistance Ro, which reflects the tacit presumption that all radial signal frequencies of interest are much smaller than ωh, the notable attribute uncovered for the circuit in Figure (6b) is that its voltage transfer function, Vo/Vs, is identical to the MFM But-terworth form predicted by (9). In (9), it is understood that p is the normalized complex frequen-cy variable, s/ωh, while the frequency, ωh, remains specified by (7).

Recalling (7) and (9), the phase response, φ(y), is

21

2

y 2 yφ(y) ,

1 2ytan

(17)

where

hy ω ω (18)

denotes the radial signal frequency normalized to radial 3-dB bandwidth ωh. Equation (17) es-tablishes an envelope delay response, Td(y), which derives from

2 4

h d 6

dφ(y) 2 y 2yω T (y) .

dy 1 y

(19)

As is to be expected from the maximally flat magnitude nature of the I/O transfer function and as is depicted in Figure (7), this delay is not maximally flat over frequency. Observe a zero fre-quency envelope delay of

d oh

2T (0) R C LC .

ω (20)

Because the I/O transfer functions of both the pi and the tee structures are identical, the phase and delay expressions of (17) -through- (20) apply equally well to the tee architecture in Figure (2).

The maximally flat nature of the voltage transfer function, Vo/Vs, combines with the pres-ence of shunt capacitance to render the output port in Figure (6b) a natural candidate for the con-



nection of either the gate-source or drain-source terminals of a MOSFET. It is tempting to prof-fer the same statement for the input port at which signal voltage, Vp, is established. Unfortunate-ly, the transfer function, Vp/Vs, is not MFM in that it contains complex left half plane zeros. Specifically,

0

0.5

1

1.5

2

2.5

3

0.01 0.03 0.10 0.32 1.00 3.16 10.00

Normalized Signal Frequency, ( / h )

Normalized Delay, T d (y)

Figure (7). The Input/Output Envelope Delay Response Of The Filter Section In Figure (6b).

2p

p 2 3s

V 1 1 2 p 2 pH (s) ,

V 2 1 2 p 2 p p

(21)

whose frequency response is shown in Figure (8).

IV. HYBRID NETWORK

At this juncture, the pi lumped network in Figure (6), whose output port branch capacit-ance renders it amenable to a realization of a quasi-distributed, common source transmission line, has been shown to deliver an I/O voltage transfer function whose frequency response is MFM. Moreover, the input impedance to a multi-lump pi architecture is impervious to all induc-tances and capacitances of the network over a broad passband extending to frequency ωh, which is defined by (7), as long as the final lump is terminated at its output port in the resistance, Ro, given by (5). Unfortunately, the transfer function between the signal source applied to the pi structure and the pi network input port is not MFM. On the other hand, the I/O transfer characte-ristic of the tee network in Figure (2) delivers an MFM frequency response. Like its pi counter-part, the tee architecture delivers an input impedance that approximates Ro, provided the output port of the tee is terminated in Ro. Since the input impedance of the suitably loaded pi network is



Ro, these observations suggest the use the hybrid tee-pi configuration offered in Figure (9). It is to be noted that since the output port of the tee network is terminated in the pi structure input port impedance, which is approximately Ro, the magnitude responses of both Vo/Vs and Vp/Vs ex-ude MFM properties. Hence, the nodes at which both responses Vo and Vp are extracted are suit-able for gate or drain terminal incidence of a common source amplifier.

0

0.2

0.4

0.6

0.8

0.01 0.03 0.10 0.32 1.00 3.16 10.00

Normalized Signal Frequency, ( / h )

Transfer Function Magnitude

Figure (8). Magnitude Response Evidenced At The Input Port Of The Filter Shown In Figure

(6b).

Z (s) Rin o

Vp

Vs

L /2 L /2

R C

RoL

2R C/22R C/2

Vo

Z (s)out

Ro

Figure (9). A Hybrid Tee-Pi Emulation Of An Ideal Transmission Line. The Frequency Responses

Implicit To Both Vo/Vs and Vp/Vs Can Be Rendered Maximally Flat Over a Broad Fre-quency Passband Extending To The 3-dB Bandwidth Of The Structure.

V. FOUR SECTION HYBRID DESIGN

The engineering propriety of the foregoing analyses is best demonstrated via a design ex-ample. To this end, consider the design of a four-section hybrid coupler that is capable of deli-vering a 3-dB bandwidth of 9.5 GHz when driven by a 50 ohm signal source. The shunting resistance R, is 10 KΩ. Aside from delineating the straightforward computation of pertinent in-ductance and capacitance values, the detailed design methodology submitted herewith also post-



ures circumvention procedures for mitigating the impact of the various approximations invoked in the course of network analysis.

A. FIRST LEVEL DESIGN

With Ro = 50 Ω and ωh = 2π(9.5 GHz), (7) yields C = 670.1 fF, which implies that in the pi section, C/2 = 335.1 fF. Using (5), the pi section has L = 1.675 nH, while in the tee structure, L/2 = 837.7 pH. With R = 10 KΩ, ωl in (6) is 2π(23.75 MHz). Figure (10), divorced of resis-tance R because of the fact that ωl is 400-times smaller than ωh, illustrates the first level design realization. Figure (11) displays the HSPICE frequency response simulations pertinent to the transfer functions, Vp1/Vs, Vp2/Vs, Vp3/Vs, and Vo/Vs in the circuit schematic diagram of Figure (10).

Z (s) 50in

Vp1

Vs

0.838

670.1

50 1.675

670.1

Vo

50

0.838

335.1

1.675

670.1

1.675

335.1

Vp2 Vp3

Figure (10). First Level Design Of A Four-Section Hybrid Coupler Designed For A 3-dB Bandwidth

Of 9.5 GHz With 50 Ω Source And Load Terminations. All Resistances Are In Ohms, Inductances Are In Nanohenries, And Capacitances Are In Femtofarads.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.0 3.2 10.0 31.6 100.0

Signal Frequency (GHz)

Magnitude Response

V p1

V p2

V p3

V o

Figure (11). Frequency Responses Pertinent To The Delineated Ports In The First Level

Design Of Figure (10).



Z (s) 50in

Vp1

Vs

0.838

670.1

50 0.530

211.9

Vo

50

0.838

106

0.530

211.9

0.530

106

Vp2 Vp3

Figure (12). Second Level Design Of A Four-Section Hybrid Coupler Designed For A 3-dB Band-

width Of 9.5 GHz With 50 Ω Source And Load Terminations. The Pi Sections Are De-signed For 3-dB Bandwidths That Are Larger Than 9.5 GHz By A Nominal Factor Of Root Ten. All Resistances Are In Ohms, Inductances Are In Nanohenries, And Capa-citances Are In Femtofarads.

0.0

0.2

0.4

0.6

1.0 3.2 10.0 31.6 100.0


Magnitude Response

V p1

V o

V p2

V p3

Figure (13). Frequency Responses Pertinent To The Delineated Ports In The Second Level Design

Of Figure (12).

B. SECOND LEVEL DESIGN

The abominable quality of the responses in Figure (11) renders a confirmation of the bandwidth design objective pointless. The fundamental problem is that in the neighborhood of the 3-dB bandwidth, ωh, the driving point input impedance given by (16) can no longer be ap-proximated by the frequency invariant resistance Ro, defined by (5). Indeed, the input imped-ances to the pi section filters become predominantly capacitive, which gives rise to resonance with the predominantly inductive nature of the high frequency output impedance established by the tee section. To mitigate this shortfall, the network in Figure (10) is redesigned so that the first stage tee section realizes the desired 9.5 GHz bandwidth, but all succeeding pi sections are designed for a significantly larger bandwidth. Figure (12) shows the resultant revision, where



the pi sections are designed to deliver 3-dB bandwidths that are larger than 9.5 GHz by a factor of root ten. This bandwidth enhancement factor results in pi section input impedances at fre-quency ωh that lie within 5.4% of the desired reference resistance, Ro. Figure (13) displays the resultant frequency responses.

C. THIRD LEVEL DESIGN

A tacit inspection of the responses shown in Figure (13) confirms the effectiveness of the second level design tack. Specifically, the responses at all four output ports are now well be-haved through at least 18 GHz. Over this 18 GHz passband, the 3-dB bandwidths of Vp1/Vs, Vp2/Vs, Vp3/Vs, and Vo/Vs are respectively 9.71 GHz, 9.74 GHz, 9.52 GHz, and 9.39 GHz, which are all within 2.2% of the 9.5 GHz design objective. Unfortunately, there are substantive re-sponse resonances, and particularly in the Vp1/Vs frequency response, at 31.6 GHz, which cu-riously is approximately equal to the 3-dB bandwidth constraint imposed on the pi sections. Although these peaked responses are outside of the 9.5 GHz passband of the entire filter, they can pose problems when the lowpass structure is ultimately transformed to a bandpass filter cen-tered at a frequency appreciably larger than 9.5 GHz. Accordingly, the need of a notch filter is suggested. To this end, the generalized filter structure given in Figure (14) provides notching at radial frequency ωn with a quality factor of Q, while sustaining a constant input impedance that matches the terminating load resistance (Rs) over all signal frequencies[20]. Since the sharpness of the effected notch is not an issue outside of the 9.5 GHz passband, Q can be chosen to be uni-ty. The subject notch filter can be introduced between the signal source and the input port of the tee subcircuit. However, since the pi section filters are designed for very large bandwidth and therefore deliver input impedances over the filter passband that are very nearly the desired 50 Ω objective, it is more advantageous to interpose the notch structure between the output port of the tee subcircuit and the input port of the first pi section. The resultant coupling filter with the notch unit designed for ωn = 2π(31.62 GHz), Q = 1, and Rs = 50 Ω, is the third level design, whose topology appears in Figure (15).

RsRs

Vs

Rs

QRs

n

QRs n

Rs

Qn

QRs n1

Vo

Z (s) = Rin s

Figure (14). Generalized, Constant Resistance Notch

Filter Whose Quality Factor Is Q And Whose Radial Notch Frequency Is ωn.



Vp1

Vs

0.838

670.1

50 50

0.530

211.9

100.7

100.7

Vo

50

0.8380.252

1060.252

0.530

211.9

0.530

106

Vp2 Vp3

Notch Filter

Figure (15). Third Level Realization Of A Four-Section Hybrid Coupler Designed For A 3-dB

Bandwidth Of 9.5 GHz With 50 Ω Source And Load Terminations. The Notch Struc-ture Is Incorporated To Remove The Significant Response Peaking Evidenced In The Second Level Design At A Frequency That Nominally Equals The 3-dB Bandwidth Of Each Of The Pi Filter Sections. All Resistances Are In Ohms, Inductances Are In Na-nohenries, And Capacitances Are In Femtofarads.

0.0

0.1

0.2

0.3

0.4

0.5

1.0 3.2 10.0 31.6 100.0


Magnitude Response

Figure (16). Frequency Responses Pertinent To The Four Delineated Ports In The Third Level De-

sign Of Figure (15).

The resultant simulated frequency responses offered in Figure (16) show that the undesira-ble resonances at nominally 31 GHz have been almost completely extirpated. The four response curves are virtually indistinguishable over the filter passband. However, an assiduous examina-tion of the simulated data yields 3-dB bandwidths for Vp1/Vs, Vp2/Vs, Vp3/Vs, and Vo/Vs of 9.48 GHz, 9.49 GHz, 9.28 GHz, and 9.16 GHz, respectively, which are collectively within 3.6% of the 9.5 GHz bandwidth design objective. The corresponding phase responses offered in Figure (17) are well behaved through signal frequencies that approach the center frequency of the incorpo-



rated notch section. These phase responses imply the group delays plotted in Figure (18). This last figure exhibits a group delay, Tp1, from signal source -to- the port at which voltage response Vp1 is extracted of nominally 40 pSEC -to- 50 pSEC for signal frequencies in the range of 1 GHz -to- 12 GHz. Using (20), 33.5 pSEC of this observed delay can be attributed to the tee structure, while the remaining delay derives from the inserted notch configuration. The average group de-lay from the Vp1–port -to- the Vp2–port, which is (Tp2 – Tp1), is 10.63 pSEC, from the Vp2–port -to- Vp3–port, (Tp3 – Tp2) = 10.62 pSEC, and from the Vp3–port -to- the Vo–port, (Tpo – Tp3) = 11.06 pSEC. These differential delays are all within 4.3% of the 10.60 pSEC zero frequency delay computed from (20) for each of the pi section subcircuits.

-900

-720

-540

-360

-180

0

1.0 1.6 2.5 4.0 6.3 10.0 15.9 25.1 39.8 63.1 100.0


Ph

as

e A

ng

le (

de

g)

V p1

V p2

V p3

V o

Figure (17). Phase Responses For Each Of The Four Output Ports In The Third Level Filter

Architecture Shown In Figure (15).



0

10

20

30

40

50

60

70

80

90

1.0 1.6 2.5 4.0 6.3 10.0


Group Delay (pSEC)

T p1

T p2

T p3

T po

Figure (18). Group (Steady State) Delay Responses For Each Of The Four Output Ports In The Third

Level Filter Realization Of Figure (15).

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 200 400 600 800 1000

Time (pSEC)

V p1

V p2

V p3

V o

Response (volts)

Figure (19). Unit Step Responses For Each Of The Four Output Ports In The Third Level Filter Reali-

zation Of Figure (15).



The final response of interest is the transient response to pulse input excitation. To this end, the signal source, Vs, in the circuit of Figure (15), is set to a one-volt, 500 pSEC pulse hav-ing 2 pSEC rise and fall times. The resultant transient responses appear in Figure (19). Note that settling to within 10% of quasi-steady state takes place in under 150 pSEC, while overshoots for all four responses are smaller than 11%.

R

L

C

L 1/ Lo

2

C

1/ Co

2

R

Lowpass Bandpass

Figure (20). The Elemental Aspects Of The Lowpass -

To- Bandpass Frequency Transformation. The Radial Center Frequency Of The De-sired Bandpass Circuit Is ωo, While The 3-dB Bandwidths Of The Lowpass And Band-pass Configurations Are presumed to Be Identical.

Vp1

Vs

0.838

670.1

100.7

50

50

0.530

17.87

100.7

Vo

50

0.838

0.252

0.0450.252

0.00

68

0.04

5

0.530 0.530

Vp2 Vp3

5.37 5.37 8.5 8.5

17.87

106

0.04

3

211.9

0.02

1

8.5

211.9

0.02

1

106

0.04

3

Figure (21). Bandpass Realization Of The Four Section Hybrid Coupler, Whose Lowpass Prototype Architec-

ture Is Given In Figure (15). The Bandpass Unit Is Designed For A Radial Frequency Of 2π(75 GHz) And A 3-dB Bandwidth That Is Identical To The 9.5 GHZ Bandwidth Of The Lowpass Structure. All Resistances Are In Ohms, Inductances Are In Nanohenries, And Capacitances Are In Femtofarads.

D. FOURTH LEVEL DESIGN

In view of the foregoing disclosures, which confirm that the lowpass filter realization in Figure (15) is functioning acceptably in both the frequency and the time domains, the only re-maining task is to transform the subject filter to a bandpass topology. To this end, the well-known lowpass -to- bandpass frequency transformation can be exploited[21]. The salient features



of this transformation are reviewed in Figure (20), for the case in which the desired radial center frequency is ωo and the 3-dB bandwidth of the lowpass prototype is identical to the 3-dB band-width of the desired bandpass filter. In particular, resistors in the lowpass domain remain resis-tors of identical resistance values in the bandpass configuration. Moreover, an inductance, L, in a lowpass prototype is replaced by the series combination of inductance L and a capacitance of value 1/ωo

2L. Finally, a capacitance of value C in the lowpass circuit transforms to a bandpass architecture as a capacitance C connected in shunt with an inductance of value 1/ωo

2C.

0.0

0.1

0.2

0.3

0.4

0.5

60.0 67.5 75.0 82.6


Magnitude Response

Figure (22). Magnitude Responses (All Four Output Ports) Of The Bandpass Filter In Figure (21).

The Frequency Axis Is A Linear Scale.

Figure (21) displays the result of transforming the lowpass architecture of Figure (15) to a bandpass filter whose radial center frequency is set to ωo = 2π(75 GHz) and whose 3-dB band-width remains identical to the 9.5 GHz bandwidth indigenous to the lowpass prototype. The cor-responding frequency responses observed at the four indicated output ports are shown in Figure (22). All four responses are largely identical and are reasonably flat over a simulated 3-dB bandwidth of 9.44 GHz, which is only 0.64% smaller than the design objective. A slight amount of peaking is evidenced at approximately 61 GHz. Since this frequency is outside the passband of the bandpass unit, no attempt is made herewith to annihilate the observed peaking.

VI. CONCLUSIONS

The work described in this document establishes a foundation for the realization of active distributed networks that are capable of providing gain over ultra broad passbands centered at ex-tremely high frequencies (EHF). It confirms the plausibility of realizing lowpass networks hav-



ing bandwidths of at least 9.5 GHz, while maintaining reasonably constant 50 ohm driving point input and output port impedances. In a lowpass embodiment of a quasi-distributed active lumped filter, two filter structures of the form shown in Figure (15) are required; one for the in-put ports of the utilized active devices and one for the output ports. To wit, Figure (23) is sub-mitted to depict the realization of a four lump quasi-distributed amplifier in MOS technology, where biasing details are omitted in the interest of clarity. Each active unit is a common source amplifier to which a common gate cascode is appended to mitigate Miller multiplication of the net gate-drain capacitance of the common source unit. In this architecture, note that part, or per-haps most, of the shunting 106 fF and 211.9 fF capacitances in the filter of Figure (15) are com-prised of either the net gate -to- ground capacitance or the net drain -to- ground capacitance of each common source-common gate amplifier. An inspection of the subject topology suggests that the transistor stages are effectively connected in shunt with one another, subject to the provi-so that their input and output capacitances are respectively isolated by the 50 Ω lumped lines. The output response, Vo, materializes as a net signal current flowing through the 50 Ω output re-sistance termination, and this net current is proportional to the sum of device drain signal cur-rents flowing through each active composite. Clearly, the MOS devices can be supplanted by SiGe bipolar transistors or indeed, by any gain stage that emulates transconductance I/O charac-teristics.

Vs

0.838

670.1

50 50

100.7

100.7 50

0.8380.252

Ci1

0.252

0.5300.5300.530

Ci2 Ci3 Ci4

0.83

8

670.1

50

50

100.

7

100.7

Vo

50

0.8380.252

Co1

0.252

0.5300.5300.530

Co2 Co3 Co4

Figure (23). Conceptual Realization Of A Four Lump, Common Source-Common Gate Cascode, Quasi-

Distributed Amplifier. Biasing Details Are Omitted In The Interest Of Simplicity. All Resistances Are In Ohms, Inductances Are In Nanohenries, And Capacitances Are In Femtofarads.



VII. REFERENCES

[1]. A. J. Burdett and C. Toumazou, “Analog Amplifier Architectures: Gain-Bandwidth Trade-Offs,” in Trade-Offs in Analog Circuit Design, C. Toumazou, G. Moschytz, and B. Gilbert (eds.). Bos-ton: Kluwer Academic Publishers, 2002, chap.7.

[2]. R. G. Meyer, “Gain and Bandwidth in Analog Design,” in Trade-Offs in Analog Circuit Design, C. Toumazou, G. Moschytz, and B. Gilbert (eds.). Boston: Kluwer Academic Publishers, 2002, chap.8.

[3]. “News” (Press Release), Federal Communications Commission, Oct. 16, 2003. [4]. T. K. Ishii, “Transmission Lines,” in The Circuits and Filters Handbook, 2nd ed., W-K. Chen (ed.).

Boca Raton, Florida: CRC Press, 2003, pp. 1165-1181. [5]. E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed Amplification,” Proc.

IRE, vol. 36, pp. 956-969, Aug. 1948. [6]. W. H. Horton, J. H. Jasberg, and J. D. Noe, “Distributed Amplifiers: Practical Considerations and

Experimental Results,” Proc. IRE, vol. 38, pp. 748-753, July 1950. [7]. D. V. Payne, “Distributed Amplifier Theory,” Proc. IRE, vol. 41, pp. 759-762, June 1953. [8]. B. Kleveland, T. H. Lee, and S. S. Wong, “50-GHz Interconnect Design in Standard Silicon Tech-

nology,” IEEE MTT-S Int’l. Microwave Symp., June 1998. [9]. B. Kleveland, C. H. Diaz, D. Dieter, L. Madden, T. H. Lee, and S. S. Wong, “Monolithic Silicon

Distributed Amplifier and Oscillator,” IEEE ISSCC Dig. Tech. Papers, pp. 70-71, Feb. 1999. [10]. B. M. Ballweber, R. Gupta, and D. J. Allstot, “A Fully Integrated 0.5-5.5 GHz CMOS Distributed

Amplifier,” IEEE J. Solid-State Circuits, vol. 35, pp. 231-239, Feb. 2000. [11]. T. H. Lee, and S. S. Wong, “CMOS RF Integrated Circuits at 5 GHZ and Beyond,” Proc. IEEE,

vol. 88, pp. 1560-1571, Oct. 2000. [12]. L. Divina and Z. Skor, “The Distributed Oscillator at 4 GHz,” IEEE Trans. Microwave Theory

Tech., vol. 46, pp. 2240-2243, Dec. 1998. [13]. H. Wu and A. Hajimiri, “A 10 GHz CMOS Distributed Voltage Controlled Oscillator,” Proc.

IEEE Custom Integrated Circuits Conf., pp. 581-584, May 2000. [14]. H. Wu and A. Hajimiri, “Silicon-Based Distributed Voltage-Controlled Oscillators,” IEEE J. Sol-

id-State Circuits, vol. 36, pp. 493-502, Mar. 2001. [15]. H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of Microstrip Line on Si–SiO2 System,”

IEEE Trans. Microwave Theory Tech., vol. MTT-19, pp. 869-881, Nov. 1971. [16]. C. P. Yue and S. S. Wong, “On-Chip Spiral Inductors With Patterned Ground Shields for Si-Based

RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998. [17]. A. Zolfaghari, A. Chan, and B. Razavi, “Stacked Inductors and 1 -to- 2 Transformers in CMOS

Technology,” Proc. 2000 Custom Integrated Circuits Conf., May 2000. [18]. W-K. Chen, Passive and Active Filters: Theory and Implementations. New York: John Wiley &

Sons, 1986, pp. 51-58. [18]. J. Choma and W-K. Chen, Linear Feedback Network Analysis and Concepts. Singapore: World

Scientific Press, pub. Scheduled for 2004, chap. 1. [19]. J. Millman and H. Taub, Pulse, Digital, and Switching Waveforms. New York: McGraw-Hill

Book Co., 1965, pp. 800-808. [20]. J. Choma, “Passive Filter Characteristics and Interstage Matching Networks for Analog RF Inte-

grated Circuits,” Univ. Southern California, Tech. Rept. #1402-001 (part of course notes in EE 402), Aug. 2002.

[21]. J. Choma, Electrical Networks: Theory and Analysis. New York: Wiley Interscience, 1985, pp. 697-700.

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