design convention

7/27/2019 Design Convention

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DESIGN CONVENTION


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Central Processing Unit (CPU)

The CPU has four main components:

1. The Control Unit

2. Arithmetic Logic Unit3. The Register Set

4. An Internal Bus System.

Arithmetic Logic Unit, Register Set and BusSystem are collectively known as datapathunit.


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INTRODUCTION

Any HDL is based on the fact that most digitalsystem can be partitioned into a controlsection and data pathsection.

The control circui t causes register transfertotake place in the data section by sendingsignals on a set of control lines.

In some circuits the sequencing of control willbe influenced by branching information fedback from the data section.


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Data\Control Partition

Data Registers

and Logic

Control

Sequential

Circuit

Data Input Data Output

Control Input

Control Signals

Branching

information


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MICRO OPERATIONS

A micro operation is an elementary operationperformed on the information stored in one or moreregisters in one clock cycle. For examples shift, count,clear, load

There are four categories of the most common microoperations:

1. Register transfer.

2. Arithmetic.3. Logic.

4. Shift.


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The basic arithmetic micro operations are

addition, subtraction, increment, decrement,

and shift. Example of addition: R3 R1 +R2.

Subtraction is most often implemented

through complementation and addition.

Adding the contents of R1 to the 2s

complement of R2 is equivalent to subtracting

Multiply and divide are not included as micro

operations since it cantbe executed in oneclock pulse.


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REGISTER TRANSFER NOTATIONS

Much of the activity of digital system consist oftransferring bits of information from one registerto another. For example:

A B;

A B + C;

Since bits of information are often treateduniformly, these logical computation can beexpressed as vector notation.

It is quiet possible to view a digital system as acollection of registers among which data may betransferred.


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Register Transfer Language

The symbolic notation used to describe themicro operation transfers among register is

called a register transfer language

A convenient tool for describing the internalorganization of digital computers

Can also be used to facilitate the design

process of digital systems.


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RTL Notations Capital letters and Numbers are used to

denote Registers. For examples:MAR2, IR

Parentheses () is used denote a part ofregisters. For example PC(H), ACC(3:0).

Arrow denotes transfer of informationamong register. For example A B.

Comma , separates two micro operation. For

example A B, C D Two micro operation separated by comma are

executed on the same clock cycle.


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Conditional Transfer: If the transfer is to occur

only under a predetermined control condition,

designate it by

If(P = 1) then (R2 R1)

or P: R2 R1,

where P is a control function that can be either 0

or 1.

Every statement written in register transfer

notation implies the presence of the required

hardware.


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Electronic Realization of Register Transfer

Two methods are popular for register transfer:

1. Gating method of Register Transfer.2. Busing method of Register Transfer.

The majority of register transfers in a digital system areclocked, i.e. synchronized by a system master clock.

Mostly D-flip-flop or JK-flip-flop are used for realizationof register transfers.

Both control section and data section are synchronizedwith clock.

All logic level changes and transfers are assumed to takeplace at the time of leading edge (+ve triggered) ortrailing edge (-ve triggered) clock pulse.

Often, control signal is ANDed with the clock in gatingmethod of register transfer.


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CSL

CLOCK

CSP

CONTROL

SEQUENTIAL

CIRCUIT

CSL

CLOCK

CSP

Old Data in BR New Data in BR


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CSL

CLOCK

CSP

AR0

Q QBAR

D

C BR0

Q QBAR

AR1

Q QBAR

D

C BR1

Q QBAR

AR2

Q QBAR

D

C BR2

Q QBAR

Clocked transfer between two register (BR


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Register Transfer Contd

Very often there may be more than one vector to betransferred into a same register.

This transfer may take place in separate step or may beexpressed in the same step as a conditional transfer.

Bank of AND gates are used where each flip flop of the

register is gated with the control signal. For example, Implement a circuit which performs the

following expression:

I f (CSL1= 1) then (CR AR)

I f (CSL2=1) then (CR BR)AR, BR, CRare 4-bit register.

It is assumed that CSL1and CSL2can never be 1simultaneously.


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AR

D

C CR1

Q QBAR

D

C CR2

Q QBAR

D

C CR0

Q QBAR

BR

CSL1

CSL2

CLOCK


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AR

D

C CR3

SL1

SL2

CLOCK

BR

Q QQ Q Q QQ Q

D

C CR2

D

C CR1

D

C CR0


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Problem: Implement the following logic by using

gating method of register transfer.

I f (CSL1= 1) then (BR 0, 0, 0, 0)

I f (CSL2= 1) then (BR 1, 1, 1, 1)

I f (CSL3= 1) then (BR AR)

AR, and BRare 4-bit register.


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NOTE

In register transfer through gating method, data

transfer operation occur among register, and thetransfer operation is synchronized with a common

system clock. Mostly D-flip-flop are used for

realization of register transfer operation. Thecontent of every bit of each source register is

ANDed with the controlling signal which initiates

transfer from that source register provided the

number of source register is more than one. For

ANDing a bank of AND gate is required.


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BUSING Many times, transfers of information among several

registers is required.

The direct extension of gating method results highlyexpensive circuits, since bank of AND gates increasesdrastically.

An alternate method that is generally less expensive inthe use of an interconnection bus also known as busingmethod of register transfer.

The number of wires will be excessive if connectionsare made between the outputs of each register and the

inputs of the other registers. A more efficient schemefor transferring information in a system with manyregisters is to use a common bus.

Transfer of data through Bus is a two step process.


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Simplified Busing Method of Register Transfer

AR

CR

BUS

BR

DR


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AR

CSL1 CSL2

BUS

BR

Q QQ Q Q QQ Q

CRCSL1

Q QQ Q DRQ QQ Q

CLK

CSL2

CLK


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Busing Contd

Transfer of data through Bus is a two step

process.

Both steps are accomplished in one clock cycle.

The first step routes the data to the output of the

bus.

The data remains at the output of the bus as long

as control level remains 1.

In the second step, the data at the output of thebus are copied in the destination register, in the

same clock cycle.


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Possible Hardware Saving.

Suppose, it is desired that a path be madeavailable for the transfer of information from one

ofn register to any one of m destination register.

In gating method, nmbanks ofAND gate will

be required together with mbanks ofORgate.

If we assume b bit in each register then total

number of gates required = (n

m + m) * b.Number of gates using Busing = (n+ 1) * b.


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Tri State Buffer(Tri-state Logic)

A three-state buffer is a digital circuit thatexhibits three states.

Two of the states are signals equivalent tologic 1 and 0 as in a conventional gate.

The third state is a high-impedance state. Thehigh-impedance state behaves like an opencircuit which means that the output is

disconnected and does not have a logicsignificance.

It is distinguished from a normal buffer byhaving both a normal input and a control input.


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Tri State Buffer Contd

Input A

Control input C

Output B

If (C==1) then B =A.

If (C==0) then device goes to high impedance

state.

Symbolic Notation


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SEQUENCING OF CONTROL A program will always have a sequence of

instruction mainly Register TransferOperations. For

example:#1 MOV A B;

#2 MOV D A + C;

#3if ( q ==1) then

#4 ADD D, A;

For each instruction, one control signal has to beprovided by the control unit.

Hence a sequence of control signal has to beprovided for execution of a program.

The generation of this control signal and feeding thissignal into the data path unit is known as

sequencing of control.


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ELECTRONIC REALIZATION OF CONTROL UNIT

Realization of control unit is possible with a varyingamount of combinational logic and flip flop.

Realization of control unit is separated from the

realization ofdatapath unit. For realization of hardwired control unit one flip-

flop per state model (per instruction) is required.

For realization of micro-programmed control unit, nflip flop is required for instructions 2n.


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CONTROL UNIT REALIZATION

#1 AB

#2 C D

(a, b)/(4, 3)

#3 C A +B

#4 D A+B

D1 Q1

C

D2 Q2

C

CLOCK

Inst. #1 Inst. #2D4 Q4

C

D3 Q3

C

a

b

Inst. #3

Inst. #4


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Start

CLOCK

Q1

Q2

Q3

Q4

If (a=1)

If (b=1)


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Problem: Show the control unit realization of thefollowing AHPL code:

#1. R X

(abar & bbar, a, abar & b)/(1, 2, 4)#2. R R1

(bbar)/(4)

#3. R R3#4. Z=R

(1)


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CONDITIONAL TRANSFER Conditional branch offers a method of choosing

between two or more transfer which might beaccomplished at a particular point in timedepending on which of a set of input or feedbackcontrol values are 1.

Suppose, for example A B if (a=1) or D C if(b=1). For realization of its control unit, sequenceof instruction has to be written.

#1 Inst.

(a, b)/(2, 3)

#2. AB

(4)

#3. DC


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Conditional Transfer Notation A B (Unconditional)

A * a B

A B* a

(A!B!C)*(f, g, h) D

(A!B!C)*(a, b, c) (D!E!F)*(d, e, f)

Asterisk (*) in the right of an register signifies ifcondition.

Above example can be represented in AHPL as

A*a B; D*bC


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An asterisk or a condition on the left side of the

transfer expression always indicates that a control

pulse will arrive at the clock inputs to the flip-flop

of the destination register iff condition is satisfied.For ex: (B!C)*(b, c) A

Conditions on the right side of the transfer

expression specify busing network for the datavector to be selected to the right side of the

transfer expression

For ex: A(B!C)*(b, c)


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D1 Q1C

D4 Q4

CD3 Q3

C

Inst. #1D2 Q2

C

A B

a

b

C D

Inst. #4

Branch and Convergence

A B


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D1 Q1

C

Inst. #1

D2 Q2

C

A B or

C D?

D4 Q4

C

D1 Q1

C

Inst. #1

D2 Q2

C

A B

D4 Q4

C

C D

a b

Conditional

Transfer

design convention

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