design considerations for high resolution pipelined adcs in digital cmos technologies

8/3/2019 Design Considerations for High Resolution Pipelined ADCs in Digital CMOS Technologies

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ESPRIT Project 29 261 ESD-MSD Cluster, Malta 3 September 2001 1

Design Considerations for High ResolutionPipeline ADCs in Digital CMOS Technology

Jorge Guilherme P. Figueiredo Joo Vital P. [email protected] [email protected] [email protected] [email protected]

G. Minderico A. Leal Jos [email protected] [email protected] [email protected]

IST Center for MicrosystemsIntegrated Circuits and Systems Group

INSTITUTO SUPERIOR TECNICOAv. Rovisco Pais 1, 1096 Lisboa Codex,

PORTUGAL

CHIPIDEA MicroelectrnicaEdificio Inovao IVSala 733 2780-920

PORTO SALVO - PORTUGAL


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Outline

Introduction

Pipeline overall noise contributions

Trade offs between noise and power in single stage amplifiers

Trade offs between noise and power in two stage amplifiers

Optimization of the compensation capacitor

Pipeline example architecture

Conclusions


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Stage 1

SHAAnaloginput

Stage i Stage n

Registers

Digital Correction

Digital Output

Ni- bitADC

Ni- bitDAC

G

G=2Ni

residueamplifier

+

+

+=2

2

2

1

2

2,

2

1

2

1,

2

&,

111 GG

V

G

VVV

MDACnoMDACnoHSno

ni

Block diagram of an N-bit and Ni-stage pipeline ADC

Noise contribution of each stage

The main noise contributioncomes from the input stages


4/21ESPRIT Project 29 261 ESD-MSD Cluster, Malta 3 September 2001 4

Noise budget relation:

Quantization noiseNNq 2

2

212

1

=

Thermal noise KT/C

Quantization noise > Thermal noise

Excessive power dissipation, no advantage

Quantization noise < Thermal noise

Loss of resolution

Best trade off

Quantization noiseThermal noisebut

Difficult to achieve



1

2

Vin

Vref

Ron

Ron

CDAC

Cf

CL

Cp

Gm

1

222

, 42 GiVnBKTRC

KTV ampeqON

DAC

MDACno

++=

eqeqeq C

gm

C

gm

B 422 ==

( )

f

PDACL

PLDACeqC

CCCCCCC

++++=

Simplified noise model of the MDAC

MDAC output noise

Noise bandwith of the amplifier



C

difpair

Load

Telescopic

C

gm

gmKT

Vn

3

12

+

=

The amplifier has one of the mostimportant noise contributions

Low noise amplifierstopologies should be chosen

The telescopic cascode yields thelowest noise since only two

transistors contribute to the totalnoiseBias

Load

gnd

Bias

Cc

M1

M3

M2

M4

Cc

vdd

diffpair

The noise can be controlled by Ccand gmof transistorsCascode compensation achives

higher GBW for the same power asMiller compensation

Two stage telescopic cascode amplifier



( )

++++

==

F

PDACLPDACL

C

CCCCCC

gmGBWBW

2

CDAC

Cf

CLCp

Gm

Vout

Residue amplification phase

Single stage amplifier

Close loop dominant pole

BW GBW

A0

f

OVDB VIgm 2=

)2ln(B

N =

Number of time constants for afirst order system

SR

A

eqOVD

B

B

TFs

CVI

)2ln(

CMOS transcondutance relation

IB doubles for each increasing bit !( )

f

PDACL

PLDACeqC

CCC

CCCC

+

+++=


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CC

gmGBW

2=

PfDAC

fC

SR

A

OVDB

BCCC

CC

TFs

VI++

)2ln(

CDAC

Cf

CL

CpGm

Vout

Cc

Output

stage

Gmload

Residue amplification phase

Two stage amplifier

The GBWdepends on Cc

PfDAC

f

CCCC

CC

gmBW

++

=

2

CL influences thephase margin of theamplifier


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+

=

difpair

Load

C

DAC

gm

gm

CC

1

3

2IF !

DAC

ampC

KTVn

2

For typical designs gmload< gmDiffpair

In the order of 2-3 times

CDAC 0.75 Cc

Leads to a higher output polesince Ccis higher than CDAC

CL

gmPole Loadoutput

Helps improving stability

Noise of theamplifier


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2

12

21218

+=

N

difpair

LoadC

VrefgmgmKTC

A two stage amplifier has at least 4 legsThe gmof the output needs be higher than the input by 2-3 times, due to stabilityFor the same overdrive voltage the output current will be 2-3 times the input current

BDDstage IVP 8

Ni

DACf

CC2

=

Is the fraction of quantization noiseattributed to the S/H and first MDAC

Assuming equal noise contributionsfor the S/H and MDAC

Cc will be the starting point of thedesign optimization

PfDAC

fC

SRA

OVD

B

DDstageCCC

CC

T

Fs

VVP

++

)2ln(8


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First stages will be noise limited if

Stage gain precision not limitted by matching

Use of analog or digital calibration techniques

Remaining stages will be matching limited and area dictates the powerdissipation

Total power dissipation will be a trade off between the noise and matching

First stages should use large resolution 4-5 bits

Final solution obtained by a optimization program

High resolution ADCs optimization


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FLASH

6b

15b Out

Digital Error Correction Logic

Inp

Clk10b

1.5 b/stage

pipeline ADC

BackendDAC

3R

17R

Unity c urrent-

source matrix

Iref

3R17R

S/HInn

CAL-DAC

VbgVrefbp

Vrefbn

SAR

Backend Vref Generation

Vrefp

Vrefn

Switches

Vbg

Frontend Vref Generation

Vrefp

Vrefn

Comparator

CAL-DACSAR

DAC full-scale

current generation

Backend input-

range calibration

amp. o ffset calibration

3R

3R

17R

17R

Architecture for 15bit@10MS/s ADC


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Noise contribution of the Front-end Pipeline Blocks

Vin

Csh

Csh

2

2

1

1

1'

DACFlash

Inputsamplingcapacitors

S/H amplifier

DAC

Resistors

Residue amplifier

MHzFoFn 702

==

RVod

FnIdTKVndac

=

3

16

f

Vdsat

Vdsat

Cc

TKVnamp 7

11

3

2+

=

RFnTKVr = 4

Kelvin 1998The resistors and the DAC inject large noise!

The DAC noise current is proportional to gm


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dBVnampVr

VndacVrVnampC

TKVref

Vref

SNR

N

78

32

.2.2.2.24

2

2.12

22

1

log1022

222

2

2

2

=

+++++

+

=

SNR system calculation

C= 10 pFCc= 10 pFIdac= 1mA

Rstring= 1000 ohm

Noise Bandwidth of a 2 pole system = 0.7854 Fo helpsreducing the noise from the DAC and resistors

Noise distribution by block

Quantization 26%KT/C 17%Resistors 20%

DAC 16%Amplifiers 21%

Trade off between power,noise and resolutionobtained by program


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SNR system simulation

dB

oiseSimulatedN

Cs

TKVref

Vref

SNR

N

6.78..2

212

2

1

210log.10

2

2

2

2

=

++

=

Simulated noise

Noise from the DAC


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Bias

vdd

gnd

Bias

Cc

VinP

OutP

I

M1

M3

M9

M2

M4

M5 M6

M7 M8

I

OutNCc

M10

M11 M12

M13M14

M15

VinN

Main schematic of the amplifiers used in the S/H and residue amplifiers

f

Vdsat

Vdsat

Cc

TKVnamp 7

11

3

2+

=

CcCLCcCCLCCT ..1.1 ++=

( )

( )22

2

2

3

2

2

.2

9.3.1.

.2

.9.3.1..3

..29.3.2

1

)(

CTC

gmgmgmsCTC

CcgmgmsCT

CcgmCcCLgms

sCcCgmgmCTC

gm

sH

+++

+

=

The amplifiers where designedbased on the noise allowed to itdependent on Cc

A telescopic cascodecompensation topology waschosen to minimize power

From Ccand GBWwe obtainedthe gmand current of the inputdiferential pair

CCgmGBW2

=


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Front-end Amplifiers

Resistor model

2

2nCR

Rsquare=8*8um^2

3R

3R

17R

17R

3R

3R

17R

17R

Vo2 Vo3Vo1

C

C

ph1

ph1

ph2

ph2

ph1a

A1 A2 A3Vin

C

R

C C

R R R

Effect of Resistor L variation

3

833.0

iCL

Cascade of 3 amplifiersclose loop pole

Resistor area (matching) limits the settlingNeed of gain calibartion


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Block diagram of the calibration network

Calibration Control SAR l

Calib

Clockstart

Data

Calibration DAC 1

SAR 2

Data

Calibration DAC 2

end start end

control controlend

Comparatorout

controlResidue amplifier

Backend Vref

VCM

Offset Voltage of the

Io Io

Residue AmplifierBackend Vref Voltage

Comp

Calibration Operation

The first stage needs calibration of the gain

Calibration network


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0 0 .01 0 . 02 0 . 03 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 80

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

10 0

Yie ld for 6 b i t DAC with 15 , 14 an d 1 3 b it p rec is ion vs . r e la t ive a c c urac y

S t d . dev. Un it y Cur ren t S our ce [% ]

Yield[%]

Current steering DAC requirements: random errors

Current source sizing: std dev(I/I) = 0.027% for 13 bit linearity

Vod = 0.76V ==> total current source DAC transistor area = 0.817 mm2

Hierarchical symmetrical switching scheme used to compensate systematic errors

Current Steering DAC


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Chip Layout

Resolution 15 bitConversion rate 10Ms/sPower consumption 320 mWPower supply 2.7-3.3VInput range 1.1VSNDR 78.6 dB

ENB 12.7 bitChip area 3.23 mm*4.75 mmCore area 2.8 mm * 4.3 mm

Process technology 0.35 m CMOSsingle poly 5-metal

Summary


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Conclusions

Identification of the main noise contribution to highresolution pipeline ADCs.

Some trade offs between noise and power were discussedfor single stage and two stage amplifiers.

Noise limited stages can be optimized by chosing suitablecompensation capacitor as starting point of design.

An example of a pipeline 15 bit architecture was discussed

design considerations for high resolution pipelined adcs in digital cmos technologies

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