S. Reda EN1600 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 31: Array Subsystems (PLAs/FPGAs)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson - Maxfield]

S. Reda EN1600 SP’08

Using ROMs to implement logic

ROM(truth table)

Inputs Outputs

In most designs, using ROMs can be extremely inefficient in terms of area

S. Reda EN1600 SP’08

Programmable logic arrays

• A Programmable Logic Array performs any function in sum-of-products form.

• Literals: inputs & complements• Products / Minterms: AND of literals• Outputs: OR of Minterms• Example: Full Adder

out

s abc abc abc abc

c ab bc ac

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b coutc

Minterm

s

Inputs Outputs

S. Reda EN1600 SP’08

NOR-NOR PLAs

• ANDs and ORs are not very efficient in CMOS• Dynamic or Pseudo-nMOS NORs are very efficient• Use DeMorgan’s Law to convert to all NORs

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

S. Reda EN1600 SP’08

PLA schematic and layout

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

S. Reda EN1600 SP’08

PLAs vs. ROMS

• PLAs are more flexible than ROMs– No need to have 2n rows for n inputs– Only generate the minterms that are needed– Take advantage of logic simplification

• PLAs are popular for small-scale circuits that have 2-level implementations

• PLAs are not scalable to implement large designs

S. Reda EN1600 SP’08

Programmable logic blocks (lookup tables)

|

&ab

cy

y = (a & b) | !c

Required function Truth table

1011101

0000010100111001011101111

y

a b c y

00001111

00110011

01010101

10111011

SRAM cells

Programmed LUT

8:1

Mul

tiple

xer

a b c

Programming information could be stored in SRAM or FLASH4-input LUT is the typical size

S. Reda EN1600 SP’08

FPGA architecture

Programmableinterconnect

Programmablelogic blocks

4-inputLUT

flip-flop

clock

muxy

qe

abcd

Switchbox

S. Reda EN1600 SP’08

To implement in FPGAs, designs need to be decomposed and mapped to LBs

Map to a LUT in a LB

[Figure form Cong FPGA’01]

S. Reda EN1600 SP’08

Programmable interconnects (local)

S. Reda EN1600 SP’08

Programmable interconnects (global)

Switchbox

S. Reda EN1600 SP’08

Example

S. Reda EN1600 SP’08

Programming the FPGA

Configuration data in

Configuration data out

= I/O pin/pad

= SRAM cell

S. Reda EN1600 SP’08

FPGAs versus custom chips

• Offer flexibility → FPGAs can be reprogrammed to perform different logic functions

• No layouts, no masks, no custom fabrication → huge savings for low, med-volume production

• Larger overhead in area, performance, and power