design and implementation of pipeling architecture in soc platform
DESCRIPTION
design a router architecture based on the pipelining technique which reduce the latency and to achieve high QoS.Clock frequency scaling and ILP exploitation have hit power wallSingle-threaded performance is leveling offFurther performance increases rely on exploiting parallelismTRANSCRIPT
Design and implementation of pipeling architecture in SoC platform
By,Sakthi.B
Adhavan.V.P Ram prasath.N
Ranjith kumar.S
Guide, Mr.P.Senthil.,M.E
Objective
To design a router architecture
based on the pipelining technique which
reduce the latency and to achieve high
QoS.
Requirements
Software requirement
ModelSim, Quartus
HDL
Verilog
Hardware requirement FPGA- cyclone II
Introduction
Clock frequency scaling and ILP exploitation have hit power wall
Single-threaded performance is leveling offFurther performance increases rely on exploiting
parallelismKey problems:
– Scalability– Energy efficiency– Design complexity
Modules
5port Round Robin Arbiter
128bit 16word SRAM input buffer
5x5 128-bit Multiplexer Crossbar
Router 5x5 128-bit
Router 5x5 128-bit
Router consist of following stages
Input Buffering
Routing Computation
VC Allocation
Switch Allocation
Output Buffering
Pipeline Router Microarchitecture
7
Cro
ssB
ar
Stage 1 Stage 2 Stage 3 Stage 4 Stage 5
VC Allocation
LT & IB (Input Buffering)LT & IB (Input Buffering)
RCRC
VCAVCA
SASA
ST & Output BufferingST & Output Buffering
Input buffers
Input buffers
DEM
UX
Physi
cal
channel
Link
Contr
ol
Link
Contr
ol
Physi
cal
channel
MU
X
DEM
UX M
UX
Output buffers
Link
Contr
ol
Output buffers
Link
Contr
ol
Physi
cal
channel
Physi
cal
channel
DEM
UX M
UX
DEM
UX M
UXRouting
Computation
Routing Computation
Switch Allocation
128bit 16word SRAM input buffer
Array of 2-port SRAM cells Four 512-bit messages
Buffer desgin
SRAM cells consisting of w columns and b rows
number of columns w is equal to flit size Flit size = port width rows b = 2048/32 = 64 Hence, 64-word 32-bit SRAM for the
flit size is 32-bits
5-port Round Robin Arbiter
Simple to implement Arbiter operates by assigning a low priority
to a request that has just been granted access to the crossbar
Ending requests will be serviced before the priority rotates (credit signal )
5x5 128-bit Multiplexer Crossbar
Multiplexer is used for switching Each input port connects to a multiplexer
at the output ports, and the select line is used to choose the appropriate input port for each output
Multiplexer & Matrix switching difference
Matrix switchingA matrix switcher can route any input to any outputIt can feed the same input to multiple outputs simultaneouslyHigh latency
Multiplexer switchingIt typically puts multiple inputs on one output simultaneouslyLow latency
Completed modules
5port Round Robin Arbiter
128bit 16word SRAM input buffer
Reference
[1] Axel Jantsch and Hannu Tenhunen. Networks on Chip.Springer, 2004
[2] Kim, J.; Dally, W.J.; Towles, B.; Gupta, A.K., "Microarchitecture of a high radix router," Computer Architecture, 2005. ISCA'05.Proceedings. 32nd International Symposium on, pp. 420-431, 4-8 June 2005.
