design and implementation of low power and high performance 4 bit carry … · 2018-06-17 · 2.9...

DESIGN AND IMPLEMENTATION OF LOW POWER AND HIGH

PERFORMANCE 4 BIT CARRY LOOKAHEAD FULL ADDER

USING FINFET TECHNOLOGY

By

LIM NGUK JIE

A Dissertation submitted for partial fulfillment of the

requirement for the degree of Master of Science (Electronic Systems

Design Engineering)

August 2015

ii

ACKNOWLEDGEMENT

First and foremost, I would like to express my sincere appreciation to

my supervisor, Dr Nor Muzlifah Mahyuddin for her suggestion, supportive,

encouragement and guidance in finishing this project. My appreciation also

goes to my family and my friends who has been so patient and supports me.

Thanks you for giving me previous advices, encouragement, guidance and

consistent supports throughout the completion of this project.

It is a pleasure to offer my regards and thanks to those who made this

thesis possible and those who helped me during the research. This dissertation

could not have been written without their help and support. Thanks for their

encouragement, support and tolerance.

Last but not least, I would like to thank the Dean and staff of the School

of EE, USM for their valuable support. In particular, I would like to thank

Madam Ong Bee Leng and Pn Mazlin who has helped me during my

candidature period in USM. Thank you.

iii

TABLE OF CONTENTS

Acknowledgement ii

Table of Contents iii

List of Tables vi

List of Figures viii

List of Appendices xi

List of Symbols xiii

Abstrak xiv

Abstract xv

Chapter 1 – Introduction 1

Overview 1 1.1

Problem Statements 3 1.2

Aims and Objectives 4 1.3

Scope of Study 4 1.4

Thesis Outline 5 1.5

Chapter 2 – Literature Review 7

Introduction 7 2.1

MOS technology 7 2.2

Full Adder 12 2.3

Ripple Carry Adder (RCA) 14 2.3.1

Carry Look-Ahead Adder (CLA) 15 2.3.2

Carry Select Adder (CSlA) 17 2.3.3

Carry Skip Adder (CSkA) 18 2.3.4

Carry Save Adder (CSA) 19 2.3.5

Carry Increment Adder (CIA) 20 2.3.6

Logic Circuit Topology 22 2.4

Complementary Static CMOS 22 2.4.1

iv

Pseudo-nMOS Full Adder 23 2.4.2

Transmission Gate Logic 24 2.4.3

Complementary Pass-Transistor Logic 26 2.4.4

Mirror Adder Logic 27 2.4.5

Comparison of Advantages and Disadvantages of 2.4.6

Static Adders 28

Performance Metric 30 2.5

Power Dissipation 31 2.5.1

Propagation Delay 33 2.5.2

Power Delay Product 35 2.5.3

Standard Cell Library Characterization 36 2.6

Characterization Flow Chart 36 2.6.1

Liberty format Standard Cell Library 37 2.6.2

Electrical Characteristic 39 2.6.3

Review of Previous Works 40 2.7

Summary 43 2.8

Chapter 3 - Methodology 45

Introduction 45 3.1

Design Flow 46 3.2

The Block of Transmission Gate (TG) Logic Style Based 3.3

1-bit Full Adder 48

The Block of Mirror Logic Style Based 1-bit Full Adder 51 3.4

Proposed 4-Bit Carry Look-Ahead (CLA) Full Adder 54 3.5

Simulation on 4-bit ALU 61 3.6

Standard Cell Library Characterization 63 3.7

Synthesis Flow 65 3.8

Summary 67 3.9

Chapter 4 – Result And Discussion 68

Introduction 68 4.1

Performance Analysis between Transmission Gate (TG) Logic 4.2

Style Based 1-bit Full Adder and Mirror Logic Style Based 1-bit

Full Adder 68

v

Performance Analysis on Proposed 4-Bit Carry Look-Ahead Full 4.3

Adder in Transmission Gate (TG) logic style 72

Synthesis Result 74 4.4

Summary 76 4.5

Chapter 5 – Conclusion and Recommendations 77

Conclusion 77 5.1

Recommendation 78 5.2

vi

LIST OF TABLES

1.1 Optimized Parameters for PMOS and NMOS Transistor 5

2.1 Minimum Feature Size 10

2.2 Truth Table of 1-bit Full Adder 13

2.3 Comparison of Static Adders 28

2.4 Comparison of 4-bit Transmission Gate Based Full Adders41

2.5 Power Dissipation Comparison of 8-bit Ripple Carry Adder

At Different Supply Voltage 43

2.6 Delay Comparison of 8-bit Ripple Carry Adder 43

2.7 Power Delay Comparison of 8-bit RCA 43

3.1 Optimized Parameters for PMOS and NMOS Transistors 48



4.1 Cell Leakage Power Comparison (uW) 69

4.2 Cell Area Comparison 69

4.3 Cell Delay (ps) Comparison 70

4.4 Cell Power (fJ) Comparison 70

4.5 Overall 1-bit Full Adder Libraries Summaries 71

4.6 Result Comparison of the 4-bit CLA based on the

Previous Topology 72

4.7 Result Comparison of the 4-bit CLA Among 22nm and

14nm Based on Proposed Topology 73

vii

4.8 Result Comparison of the 4-bit CLA with Supply Voltage

0.4V, 0.70V, and 1.40V 74

viii

LIST OF FIGURES

2.1 MOS Transistor 8

2.2 Symbols of N and P-MOS transistors 8

2.3 FinFET and Planar FET 9

2.4 Interconnect Scaling 10

2.5 Transistor Fin Improvement 10

2.6 Transistor Performance versus Leakage 11

2.7 Schematic of 1-bit Full Adder 14

2.8 Symbol Diagram of 1-bit Full Adder 14

2.9 4-bit Carry Ripple Adder 15

2.10 1-bit Carry Look-Ahead Adder 17

2.11 4-bit Carry Look-Ahead Adder 17

2.12 16-bit Carry Select Adder 18

2.13 Carry Skip Adder 19

2.14 32-bit Carry Save Adder 20

2.15 Carry Increment Adder 21

2.16 Conventional FinFET Full Adder 23

2.17 Pseudo-nMOS Full Adder 23

2.18 CMOS Transmission Gate (TG) 25

2.19 1-bit Transmission Gate (TG) Full Adder 26

2.20 1-bit Complementary Pass-Transistor Logic (CPL)

Full Adder 27

ix

2.21 Circuit Diagram for Mirror Fula Adder Topology (MFA)

, with 28 transistors 28

2.22 Components of Power Dissipation 32

2.23 Propagation Delay 34

2.24 Transition and Delay 35

2.25 Characterization Flow 36

2.26 Liberty .lib File Library Level Attributes 38

2.27 Hierarchy of Liberty Format Library 39

2.28 Power Analysis from Netlist 41

2.29 Carry Generator for CLA using Transmission Gate 42

3.1 Design Flow 47

3.2 Schematic Transmission Gate Logic Style Based 1-bit

Full Adder 49

3.3 Layout Transmission Gate Logic Style Based 1-bit

Full Adder 50

3.4 Simulation Output of Transmission Gate Logic Style

Based 1-bit Full Adder 51

3.5 Schematic of Mirror Logic Style based 1-bit Full Adder 52

3.6 Layout of Mirror Logic Style based 1-bit Full Adder 53

3.7 Simulation Output of Mirror Logic Style based 1-bit Full

Adder 53

3.8 4-bit Carry Look-Ahead Adder Schematic 55

3.9 Block Diagram of 4-bit Carry Look-Ahead Adder 56

3.10 Existed TG 1-bit Full Adder Schematic 57

3.11 Proposed Topology TG 1-bit Full Adder Schematic 58

3.12 XOR circuit in Proposed Topology TG 1-bit

Full Adder Schematic 59

3.13 XOR circuit in Proposed Topology TG 1-bit

Full Adder Schematic 60

x

3.14 Transmission gate XOR 61

3.15 1-bit ALU Building Block 62

3.16 4-bit ALU Building Block 62

3.17 Simulation of 4-bit ALU Building Block 63

3.18 Propagation Delay Points 64

3.19 Slew Threshold Points 64

3.20 Hierarchy Block of 4-bit CLA Full Adder 66

3.21 Gate Level of 4-bit CLA Full Adder 66

4.1 Power Analysis on 14nm 4-bit Carry Look-Ahead

Full Adder 75

4.2 Power Analysis on 22nm 4-bit Carry Look-Ahead

Full Adder 76

xi

LIST OF APPENDICES

A.1 Overall 1-bit Full Adder Libraries Summaries 84

A.2 Leakage Power (uW) Comparison between Transmission

Gate and Mirror 1-bit Full Adder 85

A.3 Delays (ps) Comparison when: "!b&c" between

Transmission Gate and Mirror 1-bit Full Adder 86

A.4 Power (fJ) Comparison between Transmission Gate and

Mirror 1-bit Full Adder 87

B.1 Overall Sumaries 4-bit CLA between 22nm and 14nm

based on the Proposed Topology 88

C.1 Liberty Library Level 0f 4-bit Carry Look-Ahead Adder

(CLA) 89

C.2 Liberty Cell Level 0f 4-bit Carry Look-Ahead Adder

(CLA) 90

D.1 Leakage Power (nW) of 4-bit Carry Look-Ahead Adder

(CLA) supply voltage 0.40V 91

D.2 Delay (ps) of 4-bit Carry Look-Ahead Adder (CLA) with

supply voltage 0.40V 92

D.3 Power (fJ) of 4-bit Carry Look-Ahead Adder (CLA) with








xii







E.1 Power (in mW) Distribution Graph 100

E.2 Area (in μm2) Distribution Graph 100

E.3 Gate Count Graph 101

E.4 Graph for Delay (in ns) 101

E.5 Area, Delay and Power Dissipation of Adders 102

E.6 Synthesis Result Parameter Comparison Listing 102

F.1 Configuration File in Characterization Flow 103

xiii

LIST OF SYMBOLS

ASIC - Application Specific Integrated Circuit

ALU - Arithmetic Logic Unit

DSP - Digital Signal Processing

MOSFET - Metal Oxide Semiconductor Field-Effect Transistor

RCA - Ripple Carry Adder

CLA - Carry Look-Ahead

CSlA - Carry Select Adder

CSkA - Carry Skip Adder

CSA - Carry Save Adder

CIA - Carry Increment Adder

PDP - Power Delay Product

PFA - Partial Full Adder

LEF - Library Exchange Format

MW - MilkyWay

DRC - Design Rule Check

LVS - Layout Versus Schematic

CCS - Composite Current source

CPL - Complementary Pass-Transistor Logic

LER - Line-Edge Roughness

xiv

REKA BENTUK DAN PELAKSANAAN 4 BIT PENAMBAH BAWA

LIHAT KE DEPAN YANG BERKUASA RENDAH DAN BERPRESTASI

TINGGI DENGAN MENGGUNAKAN TEKNOLOGI FINFET

ABSTRAK

Unit Aritmetik Logik (ALU) adalah litar digital dan ia digunakan untuk

melaksanakan semua operasi aritmetik dan operasi logik. Selain itu penambah

adalah bahagian yang paling penting di kalangan ALU kerana ia telah

digunakan dalam operasi aritmetik lain. Sekarang terdapat tiga parameter

prestasi utama iaitu Dimensi, Kelajuan dan Kuasa tertumpu oleh pereka VLSI

untuk penambahbaikan reka bentuk mereka. Maka, peningkatan kelajuan di

penambah akan mempercepatkan pelaksanaan semua operasi aritmetik lain.

Penambah Bawa Lihat Ke Depan (CLA) telah dipilih kerana ia

mempercepatkan pengiraan dengan mengurangkan jumlah masa dalam

penentuan bit untuk menjalankan operasi penambahan dengan lebih cepat. 4-bit

CLA boleh dilaksanakan dengan pelbagai jenis transistor, seperti FinFet dan

Transistor Kesan Medan Separuh Pengalir Oksida Logam (MOSFET). Di

project ini, CLA yang menggunakan teknologi 14nm FinFET dalam

Penghantaran Pintu (TG) telah mengesahkan kebolehan teknologi baru ini di

dalam reka bentuk penambah penuh terdapat pengurangan kira-kira 52% dalam

nilai parameter pelesapan kuasa berbanding teknik 22nm CMOS.

Kesimpulannya, ia telah menunjukkan bahawa litar CLA yang dicadangkan

dalam 14nm FinFET dalam TG dapat menyediakan kelajuan yang lebih baik

dengan kuasa pelesapan-kurangnya berbanding dengan kerja-kerja sebelumnya.

xv

DESIGN AND IMPLEMENTATION OF LOW POWER AND HIGH

PERFORMANCE 4 BIT CARRY LOOKAHEAD FULL ADDER USING

FINFET TECHNOLOGY

ABSTRACT

An Arithmetic Logic Unit (ALU) is a digital circuit and used to perform

all arithmetic operations and logic operations. Addition is the most important

part among of the ALU since it has been used in other arithmetic operation.

Now there are three main performance parameters i.e. area, speed and power are

focused by VLSI designer to optimize their design. Therefore, improving the

speed of addition increase the performance of all other arithmetic operations.

The Carry Look-Ahead Adder (CLA) has been chosen because it speeds up the

carry computation by reducing the amount of time to determine carry bits. The

4-bit CLA Full Adder can be implemented with different types of transistor,

such as FinFET and Metal Oxide Semiconductor Field-Effect Transistor

(MOSFET), which may have difference performance in supply voltage variation.

In this project, the analysis of the simulated results confirm the feasibility of the

14nm FinFET techniques in Transmission Gate (TG) style full adder design and

shows that there is reduction of approximately 52% in the value of power

dissipation parameter as compared to CMOS 22nm technique. In conclusion, it

has been shown that the proposed CLA circuit in 14nm FinFET in TG provides

better speed with the least power dissipation compared to the previous works.

CHAPTER 1

INTRODUCTION

Overview 1.1

An Arithmetic Logic Unit (ALU) is a digital circuit and used to perform

all logic operations and arithmetic operations, namely addition, subtraction,

multiplication and division. The ALU has been used in microprocessor, digital

signal processing (DSP) and data processing system.

Addition is the most important part among of the ALU since it has been

used in other arithmetic operation. Many processing operation like counting,

filtering and etc. usually involve addition. It involves a carry propagation step

which propagates a carry signal from each bit to next higher bit position. In the

past, the major challenge for VLSI designer is to reduce the area of chip. Now

there are three main performance parameters i.e. area, speed, power are focused

by designer to optimize their designs.

Carry Look-Ahead Adder (CLA) is a very important building block for

digital circuit. Most of other arithmetic operations are implemented using

addition therefore, improving the speed of addition able to speed up the

performance of all other arithmetic operations. The Carry Ripple Adder (CRA)

is the simplest adder but the carry propagation time is the major speed limiting

factor. In the CRA, the result in the next stage is obtained after the carry

generated by the previous stage is produced. The sum of the most significant is

only available after the carry-out of the full adder has rippled from the least

2

significant stage to the next most significant stage. Thus, the final sum and carry

bits will be valid after a considerable delay. Therefore, the CLA has been

chosen because it speeds up the carry process by reducing the amount of time to

determine carry bits. The CLA is able to generate carries before the sum is

produced using propagate and generate logic to make addition much faster.

FinFET is a new alternatives structure for MOSFET which allows

transistors to be scaled down to smaller sizes. It has been reported that FinFET

devices has more advantages over conventional MOSFET such as lower gate

leakage current [1], excellent control of short-channel effects [2], and also

relative immunization to the gate line-edge roughness (LER) [4].

A standard cell library contains the high quality timing, power, parasitic

models that accurately and efficiently capture behaviors of standard cell. These

metrics are written in a different files format since it is widely used in many

design tools for various purposes, such as static timing analysis, power analysis,

logic synthesis and so on. The Synopsys Liberty-format (.lib) is one of the

important kits which is widely utilize for static timing analysis and logic

synthesis [3].

The contribution of this project is in three-fold. Firstly, the 4-bit Carry

Look-ahead (CLA) Full Adder standard cell has been created by using 14nm

FinFET devices. Next, full adder has been characterized in Liberty format at

two type of supply voltage to get the behaviors of standard cell such as timing,

power, delay and parasitic models. Finally the delay and power consumption of

14nm CLA have been compared with the previous work using Synopsys Design

Compiler and the results indicate that the proposed 4-bit CLA circuit have lower

power and delay values as compared to previous work.

3

Problem Statements 1.2

Carry Look-Ahead (CLA) and Ripple Carry Adder (RCA) is a type of

adder used in digital logic. In the previous work [22], designers have designed

three different 4-bit Transmission Gate Based Full Adders namely Ripple Carry

Adder (RCA), Adder, Carry Look-Ahead Adder (CLA) and Carry Select Adder

(CSA). The average power consumption, delay and number of transistors have

been compared among three different adders in the project. In the project, the

result shows that the delay in CLA is less than RCA and CSA. Although the

RCA is the simplest adder but the carry propagation time is the major speed

limiting factor. So, to defeat the speed limitation in CRA, the CLA Full Adder

design solves this problem by calculating the carry signals in advance.

According to Moore’s law, the number of transistors in an area should

double every months [26]. When scaling down the device channel length, the

short channel effects are raised and these effects are captured by new

technology FinFET. FinFET able to reduce the short channel effect of the scale

down devices because of their better electrostatic control over the channel[26].

Besides, FinFET has more advantages than MOSFET technology in term of

leakage power, operating power, transistor gate delay and leakage current [26].

Based on the previous paper [26], Jency proposed a 4-bit full adder using

FinFET at 45nm technology with power supply of 0.7V. The target of the

project is to reduce the leakage power of a 4-bit full adder using FinFET.

Furthermore, the performance of a full adder circuit depends greatly on

the type of design used for implementation and also on the logic function

realized using the particular design style. In the previous work [28], different

logic styles have been used by designers to analyze the performance of a full

adder such as conventional CMOS full adder, parallel prefix adders, hybrid full

adders, and mirror full adders, adders using transmission gates and multiplexer

logic. Based on the performance analysis, designers concluded that the

Transmission Gate logic style provides better speed and the least power

dissipating adder compared to the Mirror logic style.

4

Therefore, the low power of 4 bit Carry Look-Ahead Full Adder using

Transmission Gate (TG) logic style in 14nm FinFET Technology will be

designed and developed to improve the efficiency and performance of power

management.

Aims and Objectives 1.3

The aim of the research as follow:

i. To design a low leakage power and high performance of the 4 bit

CLA full adder digital standard cell in generic 14nm FinFET

technology.

ii. To verify the 4 bit CLA full adder digital standard cell to ensure the

proposed adder cell is good choice in low power design.

Scope of Study 1.4

The project is focused on development of low power 4-bit Carry Look-

Ahead Full Adder using Transmission Gate (TG) logic style. All the circuits

presented in the project are designed using Cadence Virtuoso environment and

have been done on 14nm FinFET technology. The range of supply voltage is

0.40V-1.80V. The parameter of width of both n-type and p-type is tabulated in

Table below.

5

Table 1.1 Optimized Parameters for PMOS and NMOS Transistor

Transistor

Width (um) Length (um)

Technology = 14nm

PMOS 0.084 0.014

NMOS 0.084 0.014

Schematic of 1-bit Transmission Gate (TG) Full Adder and 1-bit Mirror

Style Full Adder have been design and comparison with the existing design for

power and performance are undertaken in this phase to study and evaluate the

effectiveness of the proposed design. Then, 4-bit Carry Look-Ahead Full Adder

is developed using Transmission Gate (TG) Logic style based full adder and

evaluate the circuit to analyze the result in order to meet the objectives of the

project.

Thesis Outline 1.5

This thesis is organized into five chapters.

The first chapter contains overview, problem statements, aims and

objectives, scope of the study and thesis outline.

The chapter two consist literature review of the topology used in

implement the full adder design. Literature review basically contained all the

concept, theory, basic operation and designs of Carry Look-Ahead Full Adder.

Besides, the characterization process will be discussed in this chapter. Finally,

6

the chapter will address the better strategy aimed at improving previous existing

design to provide the low power and high performance for full adder circuit.

The next chapter outlines the design and implementation of the 4-bit

CLA full adder and also including the reason for choosing the type of CLA used

in the full adder circuit. A flow chart is used to describe the flow of project and

block diagram of the system is also discussed in this chapter. The flow starts

from the schematic design until characterization process.

In the chapter four, the result of 1-bit Transmission Gate (TG) Full

Adder and 1-bit Mirror style Full Adder have been analyze and compared. Then,

4-bit Carry Look-Ahead Full Adder is developed using Transmission Gate (TG)

Logic Style Based Full Adder and the result is evaluated and analyze. The

strategy is benchmark against the previous existing design to evaluate its

effectiveness in low power and high performance analysis.

In the chapter five, it consists of conclusions of the project as well as the

findings or contribution of the project. It also highlighted the future work that

can be done by other peoples as a continuation of this research.

CHAPTER 2

LITERATURE REVIEW

Introduction 2.1

This chapter discusses the fundamental knowledge of MOS technology

and Full Adder. In the adder circuits’ design, the design of high performance

and low-power adder can be addressed at different levels, such as adder

architectures, logic styles and the process technology. Apart from that, previous

works have been reviewed and discussed in this chapter.

MOS technology 2.2

The MOS transistor and the symbol of N and P-MOS transistors are

shown in Figure 2.1 and Figure 2.2 respectively [29]. Ideally a transistor consist

three regions, Source, Drain, and Gate. The source is the main source of charge

carriers which is called terminal or node. The charge carriers leave will leave

from the source and travel to the drain. In the case of a P channel device

(PMOS), the source is the more positive of the terminals whereas in the case of

an N channel device (NMOS), the source is the more negative of the terminals.

There is the channel formed under the gate oxide. But it needs voltage to form

the channel, normally the voltage at which the transistor start conducting which

a channel starts to form between the source and the terminal is called the

threshold voltage, the transistor is said to be in the ‘linear region’. When there is

no channel formed under the gate oxide, the transistor at this point is called to

8

be in the ‘cut off region’. The transistor is said to be in the ‘saturation region’

when no more charge carriers leave from the source and travel to the drain [5].

Figure 2.1 MOS Transistor [29]

Figure 2.2 Symbols of N and P-MOS transistors [29]

The goal of the transistor is to work as a high speed electrical switch.

The switch must be on (conducting) to allow current flows from the source to

the drain. There are three functions of the transistor included allow as much

9

current to flow when it is on(active current), allow as little current to flow when

it is off(leakage current), and switch between on and off states as quickly as

possible(performance).

FinFET is a new alternative structure for Metal Oxide Semiconductor

Field-Effect Transistor (MOSFET). The FinFET and Planar FET are shown in

Figure 2.3. A FinFET is new type of multi-gate 3D transistor where the mode of

operation is same as the planar MOSFET [6] [7]. The gate of the device wraps

over the conducting drain-source channel as Figure 2.3 with the purpose of

forming several gate electrodes on each side. This help in providing lower

threshold voltages, better electrical properties and improve the performance as

well as reduction in both leakage and dynamic power compared to the existing

planar CMOS devices.

Figure 2.3 FinFET and Planar FET [29]

Moving on the capabilities and specification on the 14nm process, Intel

had provided the minimum feature size data for three main critical feature size

measurements included transistor fin pitch, transistor gate pitch, and

interconnect pitch. These features have been reduced in size between 22% and

35% from 22nm to 14nm. In the 14nm node, there are 35% reduction in the

minimum interconnect pitch which is better than normal interconnect scaling as

Figure 2.4 and Table 2.1[8].

design and implementation of low power and high performance 4 bit carry … · 2018-06-17 · 2.9...

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