Design and Implementation of an Industrial VectorControlled Induction Motor Drive

Jose Titus, Vamsikrishna M, Sekhar B, B J Rajendranath, Kamalesh Hatua, Krishna VasudevanDept. of Electrical Engineering, IIT Madras, Chennai, Tamilnadu, India.

A Koteswara Rao, Shoubhik Mukherjee, S Eswara Rao, Bishnu P MuniBharat Heavy Electricals Limited, Hyderabad, Andhra Pradesh, India.

Abstract—Vector controlled induction motor drives arequite popular in the industry in applications that demandhigh dynamic performance. This paper describes theimplementation of a complete industrial vector controlleddrive for a 30 kW induction motor. The control algorithmsfor the drive are implemented using a TMS320F28335Digital Signal Controller (DSC). Various monitoring andprotection functions for the drive are implemented using aCyclone IV FPGA that communicates with the DSC, andacts as the master controller for the drive. The FPGA alsocommunicates with a Human Machine Interface (HMI)to provide a simple graphical control interface to theoperator.

Index Terms—Digital Signal Controller (DSC), FieldOriented Control, Human Machine Interface (HMI), In-dustrial Drive, Induction motor and Vector Control

I. INTRODUCTION

AC induction motor drives using vector controltechnique are widely employed in industrial ap-plications requiring high dynamic performance. Atypical example of such an application is the driveused in a steel rolling mill. The drives are usedin power levels varying from a few kW up to theMW ranges. Modern day drives also include variousbuilt-in facilities for monitoring, protection and faultdiagnosis, in addition to the basic functionality.IEEE Std 1566[1] specifies the standards and someof the desired features for an industrial drive of largerating. Also, these additional facilities should notinterfere with the accuracy and speed of executionof the main control algorithms. Therefore, typicalcontrol hardware for industrial drives generally em-ploy two separate processing units, one of whichacts as a master controller and the other as a slave.The slave unit is dedicated for executing the maindrive control algorithms, while the master controls

the slave and also takes care of the monitoring,protection and diagnosis functions. The master unitalso has additional non-volatile memory interfacedwith it for data logging of critical drive parameters.Additionally, industrial drives also have a user inter-face, that allows the operator to control the drive andalso remotely monitor various drive parameters[2].An overall block diagram of such an industrial driveis shown in Fig.1.

Machine

Interface

Human

(HMI)

Induction

Motor

Controller

(FPGA)

Master

Controller

(DSC)

Slave

Converter

Power

Non−Volatile

Memory

Feedback signals

Fig. 1. Block diagram of an industrial drive

This paper describes the implementation of acomplete standalone industrial drive for an induc-tion motor, as described above. The drive is de-signed to operate with or without a speed sensor.The implemented drive is provided with additionalspecial functions like self-commisioning capabil-ity, power loss ride-through and on-the-fly startingcapability. The control algorithms for the driveare implemented using a TMS320F28335, whichis a 32-bit floating point Digital Signal Controller(DSC). The various monitoring, protection and diag-nostic facilities are implemented using a Cyclone IVFPGA device, that also acts as the master controller.The user interface for the drive is designed arounda G306A modular process controller from Red LionControls Inc. The paper explains the manner in

which the communication between the master andslave controller is implemented, and also the se-quence of processes that happen during the starting,running and stopping or tripping of the drive. Theimplementation of the protection and fault diagnosisfacilities in the drive are also explained in detail.

Section II describes the organisation of the drivein detail. The DSP-FPGA communication and theoverall communication between various units of thedrive are explained. The sequence of actions duringvarious phases of drive operation are also described.Section III describes the additional functionalities ofthe drive like self-commissioning and ride-throughcapability. The implementation of various moni-toring and diagnosis functions are also explained.Section IV presents and discusses some of theresults obtained from the implementation of thedrive. Section V discusses the conclusions from thepresent work.

II. DRIVE ORGANISATION

A. Power Structure of the drive

The power structure of the drive is as shown inFig.2. The power converter is a 35 kVA, two-level,IGBT based Voltage Source Inverter (VSI) operatedat a switching frequency of 2 kHz. The rated DCbus voltage of 600 V is obtained from a front endthree phase diode bridge rectifier. The firing pulsesto the drive are generated from the DSC runninga sensorless vector control algorithms with a loopsampling time of 100 µs. Hall effect sensors areused to sense the line currents of the machine andthe DC bus voltage of the inverter, for feedback. Animproved flux estimation algorithm, as reported in[3] is used for control, to obtain an excellent fieldorientation. With this control scheme, low-speed,

M

Fig. 2. Power structure of the drive

sensor-less operation upto 2.5 Hz stator frequencyis achieved.

B. Control platform

A powerful control board is designed to take careof the sophisticated needs of the drive. The boardhouses the DSC and FPGA devices. Additionalexternal Analog-Digital Converters (ADC) are alsointerfaced with the FPGA device. The board in-cludes circuitry for signal conditioning of the sensedanalog signals from the drive, so as to make itsuitable to be fed to the ADC channels of the con-trollers. Additionally, level shifting and differentialtransmission circuitry are provided to condition thePWM signals generated from the controllers. Theboard also includes transcievers for several commu-nication protocols and Digital to Analog Converter(DAC) circuits connected to both the DSC and theFPGA. It also includes additional memory chips,both volatile and non-volatile, interfaced with thecontrollers. All the ICs used in the board are chosento be of industrial grade.

C. Communication flow

A block diagram showing the vaious communi-cations in the drive is shown in Fig.3. The FPGAdevice is the master controller which communicateswith both the HMI and the DSC. The FPGA pro-cesses the commands input to the HMI from theuser, and controls the DSC accordingly. The com-munication between the HMI and FPGA is imple-mented via a serial link using a RS-485 transceiverIC ADM2587. A provision for RS-232 link isalso provided for the HMI-FPGA communication.Further, provisions for CAN communications isprovided for both the DSP and FPGA by interfacinga CAN transceiver IC with the controllers. These,along with the serial communication links may beused for future expansion by interfacing to SCADAor EMS systems.

The communication between the DSP and theFPGA is based on the External Interface (XINTF)peripheral of the TMS320F28335. This peripheralallows external devices to be connected to the DSCas memory mapped peripherals. The DSC has threedifferent XINTF zones (0, 6 and 7) each havingits own chip-select, read-enable and write-enablesignals. In the present drive, the XINTF zone-0 is

Controller

Master

(FPGA)

Controller

Slave

(DSC)

RAM−1

RAM−2

EEPROM

Red Lion

User Interface

(HMI)

Control Board

SCADA Interface for future expansion

SPI

RS

−2

32

RS

−4

85

RS

−2

32

RS

−4

85

CA

N

CA

N

Fig. 3. Various communications in the drive

used for implementing the DSC-FPGA interface.The XINTF is configured in the 16 bit mode with a150 MHz clock signal. Eight GPIO lines of the DSCare configured as the address lines and connected tothe FPGA, so as to address a total of 256 memorylocations. Also, another 16 GPIOs are configuredas the data bus and connected to the FPGA. Bi-directional communication is established betweenthe master and slave device using two SARAMblocks configured within the FPGA. These are con-nected to the DSC via the XINTF. This communi-cation is also shown in Fig.3. RAM-1 is an array of128 memory locations of 16 bit width. The DSP isonly allowed to write to these locations, while theFPGA can only read from these locations. RAM-2 is similar to RAM-1, except that only the FPGAcan write to it while the DSP can only read fromit. Thus the communication from FPGA to DSP isestablished by writing into pre-determined locationsof RAM-2. Similarly, communication from DSP toFPGA is achieved by writing into the locations ofRAM-1.

D. Protection and Fault Diagnosis

Protection and Fault Diagnosis are a vital compo-nent of any drive system. It prevents operation of thedrive under abnormal conditions like over-currents,over-voltages, over-speed etc. In the present system,the protection is provided at three different levelsin the system. The primary protection is provided

by an analog protection card, based on fast opampcomparators, whose output is given to the set inputof an RS latch, through a wired AND logic. Thecomparators compare the actual signals from thedrive with a reference voltage. The output of theRS latch is used to generate an ENABLE signal thatwill block the PWMs on detection of any fault. Faultdiagnosis is provided by additional latches wired toindividual comparator outputs, whose outputs areused to drive LEDs to indicate the type of fault.

Fig. 4. Fault Annunciation in the HMI

Secondary backup protection is provided from theFPGA side where the FPGA compares the digitalsignal from the ADCs with set reference values. Thetripping is done by pulling the trip zone pin of theDSC low. This blocks the PWM generation from theDSP in a fast manner independent of the processor.Appropriate fault message is also sent to the HMIfor display. Tertiary backup protection is providedfrom the DSC side using the sensed signals fromthe ADC. Whenever the sensed signal exceeds thereference limits, a software trip event is initiated,and the appropriate fault message information istransmitted to the FPGA for display on the HMI.However, this is a slower protection due to theexecution loop time of the DSC. Fig.4 shows thedisplay on the user interface for an over-current tripfrom the analog protection card.

E. Drive operating sequencesThe operation of the drive is divided into spe-

cific sequences namely START, RUN and STOPsequences. These sequences describe the state of

Healthy?

Drive

(FPGA)

Drive faulty

on HMI

(FPGA)

Retrieve default

parameters from

DSC

(FPGA)

User modifies the

(HMI)

default valuesmodified values

Receives the

(FPGA)

option to start the drive

HMI boots up with

all Control Cards

Power Supply to

Sends the modified

(FPGA)

values to the DSC

Charging contactor

close command

(FPGA)

DC volt > 80 %

in 2 seconds?

Drive faulty

on HMI

(FPGA)

Open Charging Contactor

Close Main Contactor and

(FPGA)

RUN command

to DSC

(FPGA)

Release PWM

(DSC)

signals

START DSC

FPGA resets

NO

YES

YES NO

Fig. 5. Start sequence for the drive

the drive and the response of the drive to externaluser actions or faults. The logics and program flowduring each of these sequences, are described below:

a) START sequence: The START sequencedescribes the course of events that happen when theuser issues a START command to the drive from theHMI. Initially, when the control supply is extendedto the drive, the HMI will boot up and present theuser with an option to START the drive. At thisstage, the DSC is held in a reset condition by theFPGA, by pulling its RSTn pin low. When the usergives a start command, the DSC is brought out ofRESET by the FPGA. The FPGA then retrieves thedefault values of the reference quantities and thevarious parameters and displays it to the user onthe HMI. The user can modify these parameterson the HMI. The FPGA then receives the modifiedparameters and sends it to the DSP via the FPGA.The FPGA then checks for drive healthiness bymonitoring a signal from the analog protection cardof the drive. If the drive is healthy, the FPGA issuescommands to close the charging contactor. Then,the FPGA waits for 2 seconds and checks to seeif the DC bus voltage has risen to at least 80 %of its rated value. If the DC voltage has been builtup, the FPGA now issues commands to open thecharging contactor and close the main contactor.FPGA then issues the RUN command to the DSP.

The DSP upon receiving the run command executesthe control algorithms and releases the PWM pulsesto the power converter. The complete flow diagramfor the START sequence is shown in Fig.5.

b) RUN sequence: In the RUN sequence, theDSP keeps on executing the control algorithms,while the FPGA continuously communicates withthe HMI to display the drive status and parameters.Fig.6 shows a display page on the HMI during therun sequence showing the various parameters ofthe drive. The RUN mode continues until a stop

Fig. 6. Parameter monitoring during RUN sequence

command is received or the drive is tripped on aprotection.

c) STOP sequence: Whenever the drive re-ceives a stop command from the operator via theHMI, the FPGA withdraws the RUN command byclearing the appropriate location in RAM-2. Thisblocks all PWM pulses to the drive. The FPGAthen pulls the reset pin of the DSP low and issuesa command to open the main contactor.

III. ADDITIONAL FEATURES

A. Self Commissioning schemeA self commissioning scheme as reported in [3],

has been implemented in the drive. The user hasto enter the nameplate details of the drive at thebeginning. With this scheme, the parameters ofthe machine like stator resistance, stator and rotorleakage inductance, magnetising inductance and therotor time-constant are determined automatically bythe drive before starting. These are then used to tunethe control loops for vector control.

The leakage inductance is determined by applyinga short pulse of 80 µs duration to one of thephases with the machine at standstill. Under theseconditions, the machine presents only the statorresistance and leakage inductance impedance to theapplied voltage. The voltage equation can be writtenas

Vs = Rsis +σLsdisdt

(1)

where σLs, which denotes the stator transient in-ductance, can be shown to be approximately twicethe stator leakage inductance. Thus with the appliedstep voltage pulse, the current rises linearly. Theleakage inductance can be calculated directly fromthe slope of the current trace. Stator resistance isobtained by injecting a dc current into one phaseusing the inverter, while the machine is at standstill.The voltage applied to the machine is calculatedfrom the PWM duty ratio, which is then used tocalculate the stator resistance. The rotor resistanceand leakage inductance are assumed to be equalto that of the stator. The rotor time constant isestimated by applying a step dc current into oneof the phases and measuring the induced statorvoltage. It can be shown that this voltage fallsexponentially with a time constant equal to therotor time constant. The initial slope of this falling

TABLE IESTIMATED PARAMETERS

Parameter Self Commissioning No-load and

Scheme Blocked Rotor test

Rs = Rr 0.1255 Ω 0.1273 Ω

Lls = Llr 1.15 mH 1.34 mH

τr 0.3587 sec 0.366 sec

voltage gives the rotor time constant. The entireestimation process is completed in less than oneminute time, before the machine is started. Theself-commissioning scheme is not required to berun each time before starting the machine. It is aspecial function which the user can invoke if sorequired. Table I compares the parameters obtainedfrom the self commissioning scheme with thoseobtained from no-load and blocked rotor tests onthe machine.

B. Power Loss Ride-throughPower Loss Ride-through refers to the ability of

the drive to withstand a momentary power supplyinterruption at the grid side, without tripping. Thedrive should also be able to smoothly continueoperation when the supply is restored. In the presentdrive, a regenerative scheme of ride-through asreported in [4] is implemented. In this method, themachine is made to regenerate whenever a powersupply interruption is sensed. The developed torque

Fig. 7. Waveforms during regenerative ride-through Ch1- DC Busvoltage, Ch2- Angular speed, Ch3-isq, Ch4- R-phase current (Scale:X-axis: 1.0 s/div, Ch1- Y-axis: 200 V/div, Ch2- Y-axis: 455 rpm/div,Ch3- Y-axis: 15.15 A/div, Ch4- 20 A/div).

Fig. 8. Starting and a step change in speed reference. (Ch1- q-axiscurrent, Ch2- R-phase current,Ch3- Mechanical speed in pu Scale:X-axis: 1.52 s/div, 2379 Y-axis: Ch1,Ch3- 0.225 pu/div Ch2-10 A/div)

in an induction machine can be written as

Md = Kt imrisq (2)

where imr denotes the rotor magnetising current,isq denotes the stator q-axis current and Kt is amachine parameter. Thus, by making isq negativeduring a supply interruption, the machine can bemade to regenerate. The regenerated power is usedto maintain the DC bus voltage during ride-through.With this scheme, the drive is able to withstandsupply interruptions of duration up to 2 secondwithout tripping. However, the drop in speed isdependent on the mechanical load on the machine.Fig.7 shows the waveforms in the drive for a ride-through condition at no-load. The drop in speed andthe smooth restart after supply is restored is clearlyvisible.

IV. RESULTS

The designed drive is tested under various oper-ating conditions. Some of the results obtained arepresented below.

Fig.8 shows the response of the R-phase currentin the machine during starting with no-load and astep change in speed reference. The variation inspeed and the q-axis current of the machine is alsoshown.

Fig.9 shows a photograph of the developedcontrol platform that houses the DSC and theFPGA, along with all the necessary communicationtransceivers, signal conditioning circuits and otherperipherals.

Fig. 9. Developed Control Platform

V. CONCLUSION

This paper described an overview of the imple-mentation of a complete industrial drive using sen-sorless vector control for an induction motor. Thecontrol organisation and the sequence of activitiesinvolved in starting, running and stopping of thedrive are explained in detail. The communicationand co-ordination between various units of the drive,and the implementation of the DSC-FPGA commu-nication using the external interface peripheral ofthe DSC, are also described. The additional featuresof the drive like self-commissioning, ride-throughand remote status monitoring are also explained.Finally, some of the results from the hardwareimplementation are also presented.

REFERENCES

[1] “IEEE standard for performance of adjustable-speed ac drivesrated 375 kw and larger,” IEEE Std 1566-2015 (Revision of IEEEStd 1566-2005), pp. 1–74, Feb 2015.

[2] D. Zimmer and D. Rhodes. Human-machine interfaces. IndustryApplications Magazine, IEEE, 12(2):29–35, March 2006.

[3] T. Bhattacharya and L. Umanand. Improved flux estimationand stator-resistance adaptation scheme for sensorless control ofinduction motor. Electric Power Applications, IEE Proceedings,153(6):911–920, November 2006.

[4] J. Holtz, W. Lotzkat, and S. Stadtfeld, “Controlled ac driveswith ride-through capability at power interruption,” IndustryApplications, IEEE Transactions on, vol. 30, no. 5, pp. 1275–1283, Sep 1994.

[5] W. Leonhard. Control of Electrical Drives. Engineering onlinelibrary. Springer Berlin Heidelberg, 2001.