design and implementation of a 5 ghz radio front-end...

Design and implementation of a 5 GHz radio

front-end module

Anders BackströmMats Ågesjö

9th November 2004

Preface

This report is the result of a Master Thesis work done at the Department of Science andTechnology (ITN) of Linköpings University. The report is the nal step towards a Mas-ter of Science exam in Electronics Design Engineering at the University of Linköping,Campus Norrköping.

Special thanks are dedicated to Toshiba and Maxim for their contribution of com-ponents. Our thanks go to Prof. Johan Liu, Dr. Zonghe Lai and Gang Zou at theIndustrial Research and Development Corporation (IVF) in Gothenburg, Sweden, forthe help when assembling ip-chip components. Thanks also go to Patrick Blomqvist atAcreo for the use of their heat plate, and to Andreas Larsson at Elektrotryck for the helpwith the routing of the PCBs.

We also thank Professor Shaofang Gong, Adriana Serban, Magnus Karlsson andAlan Huynh at ITN for useful discussions and suggestions during the project.

I

Abstract

The overall goal of this diploma work is to produce a design of a 5 GHz radio front-end using Agilent Advanced Design System (ADS) and then build a working prototype.Using this prototype to determine if RF circuits at 5 GHz can be successfully producedusing distributed components on a laminate substrate.

The design process for the radio front-end consists of two stages. In the rst stagethe distributed components are designed and simulated, and in the second stage allcomponents are merged into a PCB. This PCB is then manufactured and assembled.

All measurements on the radio front-end and the test components are made using anetwork analyser, in order to measure the S-parameters.

This diploma work has resulted in a functional design and prototype, which hasproved that designing systems for 5 GHz on a laminate substrate is possible but by nomeans trivial.

II

Sammanfattning

Det övergripande målet för det här examensarbetet är att skapa en design av en 5 GHzradio front-end med hjälp av Agilent Advanced Design System (ADS) och att byggaen fungerande prototyp. Prototypen används sedan för att avgöra om RF kretsar somanvänder distribuerade komponenter kan tillverkas på laminerade substrat vid 5 GHzmed goda resultat.

Designförloppet av radio front-end modulen utförs i två steg. I det första stegetkonstrueras och simuleras de distribuerade komponenterna och i det andra steget sam-manfogas komponenterna till en komplett kretskortsdesign. Sedan tillverkas kretskortetoch komponenterna monteras.

Alla mätningar på radio front-end modulen och test komponenterna utförs med ennätverksanalysator, för att kunna mäta S-parametrarna.

Det här examensarbetet har resulterat i en användbar design och en fungerandeprototyp, vilket visar att konstruktion av RF kretsar på laminerade substrat vid 5 GHzär möjligt men på inget sätt trivialt.

III

Contents

Terminology X

1 Introduction 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 RF Theory 3

2.1 General RF Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.1 Transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.2 Lossless transmission line . . . . . . . . . . . . . . . . . . . . . . . 52.1.3 S-Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Distributed Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 Low Noise and Power Ampliers . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.1 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3.2 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Design Process 13

3.1 Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1.1 Design Specication . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.1 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2.4 RF Choke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2.5 LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.2.6 PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3 Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Implementation 30

4.1 PCB Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.2 Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

IV

5 Measurement Setup 31

5.1 Initial meas. problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Results 33

6.1 Component Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.1 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.1.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.1.4 RF Choke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.1.5 LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.1.6 PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2 Radio Front-End Measurements . . . . . . . . . . . . . . . . . . . . . . . 46

7 Discussions 53

8 Conclusions 57

9 Further work 58

Bibliography 59

A Tools 60

B PCB Layout 63

C Schematics 65

D Additional simulations and measurements 67

V

List of Figures

2.1 Lumped-element model of a transmission line splited into a ∆z-long section 42.2 Transmission line terminated with a load impedance ZL . . . . . . . . . . 62.3 Two port network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.4 Stability, Gain and Noise circles in Smith Chart . . . . . . . . . . . . . . 11

3.1 Schematic representation of radio front-end . . . . . . . . . . . . . . . . . 143.2 Switch overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3 Signal path in Case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4 Signal path in Case2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5 S21 in Case1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.6 S21 in Case2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.7 PIN-Diode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.8 Schematic representation of the Switch in ADS . . . . . . . . . . . . . . . 183.9 Layout representation of the Switch in ADS . . . . . . . . . . . . . . . . 183.10 Layout Component in Schematic . . . . . . . . . . . . . . . . . . . . . . 193.11 Fourth-order bandpass lter of coupled-line and hairpin coupled-line type 193.12 Coupled section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.13 Simulation comparison between schematic and layout . . . . . . . . . . . 203.14 Final lter dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.15 Dierent balun types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.16 RF choke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.17 RF choke dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.18 S2P block in ADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.19 Rolett factor for unstabilised LNA . . . . . . . . . . . . . . . . . . . . . . 243.20 Footprint of LNA and resistor pads . . . . . . . . . . . . . . . . . . . . . 253.21 LNA input matching network . . . . . . . . . . . . . . . . . . . . . . . . 253.22 LNA IMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.23 LNA OMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.24 Matched LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.25 PA IMN in Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.26 PA OMN in Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.27 PA IMN in Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.28 PA OMN in Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.29 SMD pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.30 LNA Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.31 PA Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.32 PCB layer denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VI

5.1 Rohde&Schwarz network analyser . . . . . . . . . . . . . . . . . . . . . . 315.2 SMA-connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.3 SMA soldered to the edge of the PCB . . . . . . . . . . . . . . . . . . . . 32

6.1 Switch test component . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.2 Simulated S21 and S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.3 Measured S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.4 Measured S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.5 Simulated S21 and S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.6 Measured S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.7 Measured S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.8 Simulated lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.9 Measured lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.10 Balun test components type 1 (top) and type 2 (bottom) . . . . . . . . . 376.11 Simulated S21 and S31 for type1 . . . . . . . . . . . . . . . . . . . . . . . 376.12 Measured S21 for type1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.13 Measured S31 for type1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.14 Simulated S21 and S31 for type2 . . . . . . . . . . . . . . . . . . . . . . . 386.15 Measured S21 for type2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.16 Measured S31 for type2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.17 Simulated and measured S21 . . . . . . . . . . . . . . . . . . . . . . . . . 406.18 RF choke test component . . . . . . . . . . . . . . . . . . . . . . . . . . 406.19 LNA test component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.20 Simulated S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.21 Measured S21 at 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.22 Measured S21 at 2.2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.23 Measured S11 at 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.24 Measured S11 at 2.2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.25 Simulated S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.26 Measured S22 at 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.27 Measured S22 at 2.2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.28 Simulated S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.29 PA test component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446.30 Measurement S21 at 1.5V bias . . . . . . . . . . . . . . . . . . . . . . . . 446.31 Measurement S21 at 1.9V bias . . . . . . . . . . . . . . . . . . . . . . . . 446.32 Measurement S11 at 1.5V bias . . . . . . . . . . . . . . . . . . . . . . . . 456.33 Measurement S11 at 1.9V bias . . . . . . . . . . . . . . . . . . . . . . . . 456.34 Measurement S22 at 1.5V bias . . . . . . . . . . . . . . . . . . . . . . . . 456.35 Measurement S22 at 1.9V bias . . . . . . . . . . . . . . . . . . . . . . . . 456.36 Simulation Rx S21 & S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . 466.37 Measurement Rx S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.38 Measurement Rx S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.39 Simulation Rx S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.40 Measurement Rx S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.41 Simulation Rx S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.42 Measurement Rx S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

VII

6.43 Simulation Rx S33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506.44 Measurement Rx S33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506.45 Measurement Tx S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516.46 Measurement Tx S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526.47 Measurement Tx S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1 Substrate model comparison in simulation . . . . . . . . . . . . . . . . . 547.2 Simulated large pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557.3 Measured large pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557.4 Simulated small pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557.5 Measured small pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557.6 S21 measured on a transmission line with SMA-connectors . . . . . . . . 56

A.1 Calculate transmissionlines using LineCalc in ADS . . . . . . . . . . . . . 60A.2 Select source impedance in Smith Chart . . . . . . . . . . . . . . . . . . 61A.3 Smith Chart tool in ADS . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

B.1 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63B.2 Adjusted Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63B.3 DC Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63B.4 Ground Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63B.5 Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64B.6 Shutdown Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64B.7 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64B.8 Power Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

C.1 Schematic of the LNA test PCB . . . . . . . . . . . . . . . . . . . . . . . 65C.2 Schematic of the PA test PCB . . . . . . . . . . . . . . . . . . . . . . . . 66

D.1 Simulation of front-end Rx S21 with soldermask model . . . . . . . . . . 67D.2 Measured front-end Rx S21 . . . . . . . . . . . . . . . . . . . . . . . . . 68D.3 Simulated switch S21 & S31, new PIN diode model . . . . . . . . . . . . 68D.4 Measured switch S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69D.5 Measured switch S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69D.6 Simulated switch S21 & S31, new PIN diode model . . . . . . . . . . . . 70D.7 Measured switch S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70D.8 Measured switch S31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

VIII

List of Tables

3.1 Main Design Specications . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2 Substrate Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3 Amplier Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4 Stabilising LNA at 5.25 GHz . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Balun attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2 Balun phaseshift in degrees . . . . . . . . . . . . . . . . . . . . . . . . . 396.3 LNA S21 at key frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 416.4 LNA S11 at key frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 426.5 LNA S22 at key frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 436.6 PA s-parameter values at 1.5 V bias . . . . . . . . . . . . . . . . . . . . . 456.7 PA s-parameter values at 1.9 V bias . . . . . . . . . . . . . . . . . . . . . 45

7.1 Soldermask properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IX

Terminology

Abbreviation Explanation

ADS Advanced Design System. Simulation tool

Balun Balanced to unbalanced

EM Electromagnetic

IMN Input Matching Network

LNA Low Noise Amplier

NF Noise Figure

OMN Output Matching Network

PA Power Amplier

PCB Printed Circuit Board

RF Radio Frequency

RX Receiver

SMD Surfaced Mounted Device

TX Transmitter

UCSP Micro chip-scale package

VSWR Voltage Standing Wave Ratio

WLAN Wireless Local Area Network

Z0 Characteristic line impedance

ZL Load impedance

λ/2 Half wavelength

λ/4 Quarter wavelength

X

Chapter 1

Introduction

1.1 Background

Wireless communication, emphasising on wireless local area networking in this project,is growing rapidly. Increasing number of users requires more bandwidth and thus higherfrequency. The 5 GHz band is nothing new but it brings new problems for implemen-tation on laminated substrates. It is therefore of interest to study how a circuit usingdistributed components behaves at 5 GHz.

1.2 Goal

The overall goal of this project is to produce a design using Agilent ADS and then builda working prototype. Using this prototype to determine if RF circuits at 5 GHz canbe successfully produced using distributed components on a laminate substrate. A sidegoal for this project is to learn to use Agilent ADS as it is a very powerful design toolfor RF applications.

1.3 Method

Information on the radio front-end and its components is obtained from literature andthe internet.

Agilent ADS is used to make the entire design, from initial simulations to the nallayout. The design process is mainly carried out in three steps, Schematic, Layout andnally Schematic representation using Layout Components.

Measurements are made using a Rohde&Schwarz Vector Network Analyser.

1.4 Outline

This report is organised in several sections. To give readers an overview of the reportthese sections will be introduced.

1

1.4. OUTLINE CHAPTER 1. INTRODUCTION

• Chapter 2 consists of RF theory. This is an introduction to the general conceptof RF design, how distributed components work and how to use ampliers in RFapplications. There is also a subsection on the ROGERS 4350B substrate.

• Chapter 3 covers the entire design process from project specication, referencedesign and components to complete radio front-end design and Layout.

• Chapter 4 describes the implementation of the 5 GHz radio front-end design.

• Chapter 5 describes the measurment setup, and initial measurment problems.

• Chapter 6 displays the simulated and measured results for the 5 GHz radio front-end and the components.

• Chapter 7 contains the discussions regarding the results obtained by this project.

• Chapter 8 contains the conclusions that can be drawn by the obtained results.

• Chapter 9 gives suggestions on future work in this area.

2

Chapter 2

RF Theory

This chapter is intended to give some basic understanding of RF theory and design. Formore comprehensive knowledge please see the books listed in the bibliography.

2.1 General RF Theory [1][2]

Dealing with low frequency AC and DC circuits, conventional Kircho's voltage and cur-rent laws are used as analysis tools. Heading into higher operating frequencies those lawscan no longer be applied without losing too much precision. Analysing a low frequencycircuit, a conductor between two elements always assumes to have the same potentialregardless where on the conductor one looks. When it comes to higher frequencies thanaround 500 MHz the previous assumption may no longer be correct. The reason forthis is that the wavelength of the signal becomes so small that voltage and current willpropagate as waves and therefore magnitude and phase vary along the conductor.

Instead of using Kircho's laws one must deal with electromagnetic waves and issueslike propagation constant β, phase velocity vp and skin depth δ become important. Thepropagation constant and phase velocity highly depend on the medium surrounding theconductor and they will determine the wavelength for a specic frequency. Since thesurrounding medium is a crucial design parameter, choosing a good substrate is one ofthe rst design steps in RF-design. Skin eect is a consequence that also occurs dueto the electromagnetic wave nature and this eect forces the majority of the energy toow close to the surface of the conductor. Penetration of the signal into the conductoris measured in skin depth δ. When the energy is focused in just a few percent of theconductor the result is a decrease in eective cross-sectional area. As a consequence,loss due to higher resistance will occur. Changing the copper thickness will have littleeect on trace resistance at high frequencies, while changes in width and length willhave the greatest eect on resistance at high frequencies.

2.1.1 Transmission lines

In RF circuit design transmission lines are used due to their good behaviour at highfrequencies. Transmission lines are nothing more than conductors with a known distanceto a ground reference. Examples of transmission lines are Two-Wire lines, coaxial lines

3

2.1. GENERAL RF THEORY CHAPTER 2. RF THEORY

and microstrip lines. Within these lines voltage and current propagate as waves andhence magnitude and phase vary over its length. Since Kircho's voltage and currentlaws do not take those spatial variations on transmission lines into account they cannotbe used straight ahead. By breaking down a transmission line into small (in the limitinnitesimally small) segments, Kirchos's laws can still be applied.

Figure 2.1: Lumped-element model of a transmission line splited into a ∆z-long section

In the schematicall representation of the innitesimal transmission line, the valuesR, L, G and C are the resistance, inductance, conduction and capacitance per unitlength, respectively. Kircho's laws can now be applied to the lumped element circuitin gure 2.1, leading to the following equations:

v(z, t)−R∆zi(z, t)− L∆z∂i(z, t)

∂t− v(z + ∆z, t) = 0 (2.1a)

i(z, t)−G∆zv(z + ∆z, t)− C∆z∂v(z + ∆z, t)

∂t− i(z + ∆z, t) = 0 (2.1b)

Dividing equation 2.1a and 2.1b by ∆z and taking the limits as ∆z → 0, followingequations appear:

∂v(z, t)

∂z= −Ri(z, t)− L

∂i(z, t)

∂t(2.2a)

∂i(z, t)

∂z= −Gv(z, t)− C

∂v(z, t)

∂t(2.2b)

With sinusoidal steady-state condition only propagation in z-direction can be ob-served, and therefore equations 2.2a and 2.2b are simplied to:

dV (z)

dz= −(R + jωL)I(z) (2.3a)

dI(z)

dz= −(G + jωC)V (z) (2.3b)

4


Wave equations for V (z) and I(z) are found by solving equations 2.3a and 2.3b:

d2V (z)

dz2− γ2V (z) = 0 (2.4a)

d2I(z)

dz2− γ2I(z) = 0 (2.4b)

Where γ =√

(R + jωL)(G + jωC) and is called the complex propagation constantand is a function of frequency. Solution for equation 2.4a and 2.4b can be found andwritten as:

V (z) = V +0 e−jγz + V −

0 ejγz (2.5a)

I(z) = I+0 e−jγz + I−0 ejγz (2.5b)

The term e−jγz represents wave propagation in positive z-direction, and ejγz representwave propagation in the negative z-direction. The following relation is recieved whencombining equation 2.3 and 2.4.

I(z) =γ

R + jωLV (z) (2.6)

Which gives the characteristics impedance:

Z0 =V (z)

I(z)=

√R + jωL

G + jωC(2.7)

Z0 is not a function of the propagation waveform, the length of the conductor or time.It is a function of the model parameters only and may therefore easily be modied byadjusting the conductor dimensions and distance to the ground plane, which changethe inductance and capacitance per unit length of the conductor. At higher frequen-cies the conductive and resistive terms become insignicant compered to the inductiveand capacitive terms. By neglecting the conductive and resistive terms characteristicimpedance can be written as:

Z0 =

√L

C,which is a constant. (2.8)

2.1.2 Lossless transmission line

In equation 2.8 the conductor is lossless and the ratio between voltage and current isconstant. Terminating the transmission line shown in gure 2.2 with a load impedanceZL 6= Z0 will change the ratio. If an incident wave has the form V +

0 e−jβz and is generatedfrom a source at z < 0 where β = ω

√LC, when the wave hits ZL some part of the wave

5


Figure 2.2: Transmission line terminated with a load impedance ZL

will pass through and the other part reects back. The total current or voltage on thetransmission line is equal to the sum of incident and reected waves, se equation 2.9.

V (z) = V +0 e−jβz + V −

0 ejβz (2.9a)

I(z) = I+0 e−jβz + I−0 ejβz (2.9b)

WhereV +

0

I+0

= Z0 =−V −

0

I−0(2.10)

At z = 0 the ratio between voltage and current is:

ZL =V (z)

I(z)=

V +0 + V −

0

V +0 − V −

0

Z0 (2.11)

Ratio of the voltage amplitude between the reected and incident wave is known asthe voltage reection coecient Γ and is dened as:

Γ =V −

0

V +0

=ZL − Z0

ZL + Z0

(2.12)

If Γ = 0 there is no reected wave. This can be obtained if the load impedance ZL

is equal to the characteristic impedance Z0, see equation 2.12. In that case the loadimpedance ZL is matched to the line since there is no reection of the incident wave.

2.1.3 S-Parameters

Scattering parameter or more commonly referred as S-parameter representation playsan important role in RF systems regarding measurement and technical documentation.This importance is due to the fact that normal system characterisations like open-or short-circuit measurements can no longer be accomplished as it is done in a low-frequency application. Measurement methods for low-frequency systems usually strive

6


to measure the total voltage or current as a function of frequency. At high frequenciesgood measurement results using these methods are very hard to achieve. Instead theS-parameters were developed, which are dened as the ratio of normalised power wavesand are easier to measure.

Figure 2.3: Two port network

Figure 2.3 shows two dierent two port representations, the left one shows the deni-tion for voltage and current and the right one shows the normalised incident power wavean and normalised reected power wave bn. The normalised power waves are dened asfollows:

a1 =V1 + Z0I1

2√

Z0

=voltage wave incident on port 1√

Z0

(2.13)

a2 =V2 + Z0I2

2√

Z0

=voltage wave incident on port 2√

Z0

(2.14)

b1 =V1 + Z0I1

2√

Z0

=voltage wave reected from port 1√

Z0

(2.15)

b2 =V2 + Z0I2

2√

Z0

=voltage wave reected from port 2√

Z0

(2.16)

Where Z0 is the characteristic impedance of the two-port network. S-parameters aredetermined by measuring the magnitude and the phase of the incident, reected andtransmitted voltage waves. Depending on which port that is terminated dierent S-parameters for a two-port network can be found.

S11 =b1

a1

∣∣∣∣a2=0

S21 =b2

a1

∣∣∣∣a2=0

S22 =b2

a2

∣∣∣∣a1=0

S12 =b1

a2

∣∣∣∣a1=0

(2.17)

Conditions a1 = 0 and a2 = 0 mean that no power waves are returned to thenetwork at either port 1 or port 2. This can only be accomplished when the connectedtransmission lines are terminated into their characteristic impedance. To clarify themeaning of S-parameters it can be said that S11 and S22 specify how much of theincident signal is reected at port 1 and port 2, respectively. S21 and S12 specify howmuch of the incident wave that pass through the device from port 1 to port 2 and fromport 2 to port 1, respectively.

7

2.2. DISTRIBUTED COMPONENTS CHAPTER 2. RF THEORY

2.2 Distributed Components

Design of RF circuits can be made using lumped elements of inductors and capacitorsor use distributed elements, i.e., transmission lines. Both techniques have their advan-tages and drawbacks. Lumped elements are quit small and an RF-component can beimplemented in a small area. An Drawback with lumped elements is that at a highfrequency when their size is no longer much smaller than the wavelength, characteris-tics other than the desired will occur. With distributed elements the drawback is thatthe size depends on frequency. Lower frequencies have longer wavelength than higherfrequencies. For a distributed RF-component the size often becomes too large to be im-plemented in a real useful application. However nowadays when more applications areusing high frequencies, the large size issue becomes less of a problem. Another drawbackis that good substrates for distributed components are very expensive. Advantage withdistributed components is that some of the design parameters like length and width canvary a certain degree but the component still maintain its desired function [3]. Thisdiploma work focuses on distributed components for implementation of the 5GHz radiofront-end module.

A known and important term regarding distributed components is the quarter wave-length (λ/4). Referring to the Smith chart, at a matched impedance condition, anyextra length of transmission line does change the input impedance. Starting with anopen circuit, one λ/4 away results in a short circuit. Starting from a short circuit, oneλ/4 away result in open circuit. Thus one can create an RF open circuit that is a DCshort circuit. This behaviour is used in this diploma work to create the switch and theRF choke circuits.

2.3 Low Noise and Power Ampliers [1]

Designing RF circuits using ampliers diers signicantly from the traditional low fre-quency design methodology. At high frequencies much consideration must be taken intoaccount, such as voltage and current waves, matching networks to reduce the VoltageStanding Wave Ratio (VSWR) and undesirable oscillations. Therefore, one of the mostimportant tasks of designing an RF amplier circuit is to ensure circuit stability. Whenthe amplier is stable, gain and noise circles can be drawn in the Smith Chart to de-termine the circuit properties. Designing RF ampliers is always a trade-o betweenstability, noise and gain.

2.3.1 Stability

In order to stabilise an amplier the S-parameters for the amplier at the frequencyrange of interest are needed. With the help of these S-parameters stability circles canbe drawn in the Smith chart, in order to determine if the amplier is stable in the desiredregion.

The stability of an amplier circuit can also be studied with the help of the Rolettfactor. This is more useful when viewing larger frequency spectra.

8

2.3. LOW NOISE AND POWER AMPLIFIERS CHAPTER 2. RF THEORY

k =1− |S11|2 − |S22|2 + |∆|2

2|S12||S21|> 1 (2.18)

Where

|∆| = |S11S22 − S12S21| (2.19)

To design an unconditionally stable amplier circuit, which implies that the amplierremains stable within the entire domain of the Smith Chart at the selected frequencyand the given bias conditions, the following conditions must be met.

|S11| < 1 & |S22| < 1 (2.20)

As well as

k > 1 & |∆| < 1 (2.21)

If an RF amplier is determined to be unstable, and its function calls for stablility,a stabilising network is needed. One way to stabilise an RF amplier is to add a seriesor shunt resistor to either input or output port, preferably to the output port since aresistor produces noise which is undesirable to amplify.

2.3.2 Gain

To determine the gain of an RF amplier circuit a method using constant operatinggain circles can be applied. This method allows the representation of gain in the SmithChart. The rst step when using this metod is to determine the maximum gain of theamplier with the source and load terminations. This can be done by using the followingexpression.

GT =power delivered to the load

available power from source=

(1− |ΓL|2)|S21|(1− |ΓIN |2)|1− S22ΓL|2

When the maximum gain is determined other values of gain can be chosen and drawnin the Smith Chart, this will prove to be a useful property when considering noise. Thisis done by selecting values smaller than the maximum gain GT , preferably integers, andthen using the two following equations to calculate the center and radius of the constantgain circle.

Center dg0 =g0(S22 −∆S∗

11)∗

1 + g0(|S22|2 − |∆|2)(2.22)

Radius rg0 =

√1− 2kg0|S11S21|+ g2

0|S12S21|2|1 + g0(|S22|2 − |∆|2)|

(2.23)

9


Where k is the Rolett factor and g0 is an intermediate term for the following expres-sion.

g0 =G

|S21|2Where G = 10(Desired gain in dB)/10 (2.24)

Using these circles a suitable load reection coecient ΓL can be chosen and bysolving the following expression, the corresponding source reection coecient ΓS canbe found.

ΓS =

(S11 −∆ΓL

1− S22ΓL

)∗

(2.25)

These reection coecients can now be used to design a matching network.

2.3.3 Noise

The design of the LNA circuit is a compromise between stability, gain and noise gureand the maximum gain cannot be obtained simultaneously. In order to eciently designan LNA circuit a representation for the noise gure as part of the Smith Chart mustbe used. This enables the designer to view gain, noise gure and stability propertiessimultaneously.

There are three key parameters that are needed for the noise gure analysis of anRF amplier.

• Minimum noise gure NFmin, that depends on the biasing condition and operatingfrequency of the device.

• Equivalent noise resistance Rn

• Optimum reection coecient Γopt

Given these parameters the noise gure can be determined at any given source re-ection point ΓS in the Smith Chart.

F = Fmin +4Rn

Z0

|ΓS − Γopt|2

(1− |ΓS|2)|1 + Γopt|2(2.26)

Previously circles of constant gain have been drawn in the ΓL-plane. However, sincethe noise gure depends on ΓS it would be useful to map the constant gain circles inthe ΓS-plane instead. Remembering that ΓS and ΓL depend on each other (see equation2.25) the following equations can be deduced.

Center dgS=

(1− S22dg0)(S11 −∆dg0)∗ − r2

g0∆∗S22

|1− S22dg0|2 − r2g0|S22|2

(2.27)

10


Radius rgS=

rg0|S12S21|∣∣|1− S22dg0|2 − r2g0|S22|2

∣∣ (2.28)

With the circles of constant gain now mapped in the ΓS-plane the noise circles canbe added.

Center dFk=

Γopt

1 + Qk

(2.29)

Radius rFk=

√(1− |Γopt|2)Qk + Q2

k

1 + Qk

(2.30)

Where

Qk = |1 + Γopt|2(

Fk − Fmin

4Rn/Z0

)Fk > Fmin (2.31)

The gain and noise circles can now be displayed, as shown in gure 2.4. By studyingthe circles and taking the design specication into account, a source reection pointthat, if possible, satises the design requirements can be chosen. Then a matching loadreection point can be found by using equation 2.25.

Figure 2.4: Stability, Gain and Noise circles in Smith Chart

When the source and load reection points are determined the input and outputmatching network are designed. Matching networks can be made with lumped compo-nents, distributed components or a mix of both.

11

2.4. SUBSTRATE CHAPTER 2. RF THEORY

2.4 Substrate

In RF applications the choice of substrate material can aect the overall performancedrastically. When designing RF circuits it is desirable to control parameters that aectsignal loss, which occurs either through impedance missmatch or dielectric loss. Thesubstrate can add to impedance missmatch in transmission lines due to dierences in thethickness of the dielectric. This thickness aects the spacing between signal trace andthe groundplane thus changing the characteristic impedance (Z0) of the transmissionline, which induces signal reections. Dielectric losses are caused by the conductancebetween traces and the groundplane, due to the Loss Tangent (tg δ), which indicateshow much of the propagating signal is lost to the dielectric. Besides good properties itis also important that these properties are stable, as high variations in these propertieswill cause even worse eects than what is gained from that material. Knowledge aboutthese parameters is a good step towards a stable design.

12

Chapter 3

Design Process

The design is, as previously stated, made using the Agilent ADS tool. The design processis mainly carried out in three steps.

The rst step is a schematic representation of circuits and components. This impliesthat component values and behaviour are close to ideal. This will be referred to as theSchematic representation or simply Schematic.

When the initial reference design in Schematic is satisfactory the second step of thedesign process can begin. By converting the Schematic design into a Layout design,physical simulations on the actual transmission lines and traces can be made using theMomentum tool in ADS. These simulations will give a result that is closer to the "truth"than the Schematic simulations since the electromagnetic simulation take adjacent com-ponents into account.

Finally, when a component layout is completed, this component can be used inSchematic by converting it into a Layout Component. This allows for entire systemsimulations using both Schematic and Layout designs. This is the third step in thedesign process.

3.1 Design Overview

The purpose of the radio front-end is to act as an interface between a transciever andantennas. When receiving a signal it will lter, amplify and in this case balance thesignal before downconversion. During transmitting it will lter and amplify the signalafter upconversion.

This radio front-end has a dual antenna capability that enables antenna diversity.The Tx/Rx switch determines if the front-end is in transmit or receive mode. No controllogic is incorporated in this design, allowing the user to implement preferred controlmethods. The receiver part consists of a MAX2649 Low Noise Amplier and a balun thatconverts the amplied unbalanced signal into a balanced signal. When transmitting, thesignal is ltered and then amplied using the MAX2840 Power Amplier. As previouslymentioned the goal of this design is to incorporate distributed components, using asfew lumped components in the signal path as possible. This will be explained in thefollowing sections.

13

3.1. DESIGN OVERVIEW CHAPTER 3. DESIGN PROCESS

Figure 3.1: Schematic representation of radio front-end

3.1.1 Design Specication [3]

Table 3.1: Main Design SpecicationsParameter Desired Value

RF Pass-Band 5.15−5.35 GHzRecieve Gain ≥ 10 dB

Transmitting Gain ≥ 18 dB

Out Band Signal Power < −100 dBmAntenna Impedance 50 Ω

Supply Voltage 3 V

Table 3.2: Substrate PropertiesMaterial RO4350B

Dielectric thickness 0.254 mm

Dielectric constant 3.48 ± 0.05

Dissipation factor 0.004

Metal thickness 0.045 mm

Metal conductivity 5.8× 107 S/m

Surface roughness 0.001 mm

The only design restriction is the minimum line width and separation, which is 75µm.This measure is taken from the PCB manufacturer Elektrotyck's design rules.

14

3.2. COMPONENTS CHAPTER 3. DESIGN PROCESS

Table 3.3: Amplier PropertiesFunction LNA PA

Part number MAX2649 MAX2840

Operating Frequency range 4.9-5.9 GHz 5-6 GHz

Gain 17 dB 22dB

Typical Noise gure 2.1 dB N/A

IIP3 0 dBm N/A

Supply voltage +2.7V to +3.6V

Size 1 x 1.5mm 2 x 1.5mm

Package UCSP

Leads 2 x 3 3 x 4

3.2 Components

This section describes the designed components in depth, describing the componentfunction and how that function is achieved, as well as giving a thorough insight in thedesign process of the component.

3.2.1 Switch

The purpose of the switch is to select a signal path using a control voltage. This switchcan be used in either direction, using port 1 as input and port 2 & 3 as output or port2 & 3 as input and port 1 as output.

Figure 3.2: Switch overview

This function is achieved by using two PIN diodes. The resistor is a current limiterthat limits the current though the circuit to 3 mA at a 3 V supply voltage.

To further explain the function two cases will be used. In case 1 the supply voltageis 0 V and in case 2 the supply voltage is 3 V.

Case 1: With the supply voltage set to 0 V the PIN-diodes are deactivated and will

15


Figure 3.3: Signal path in Case 1

act as signal blockers, only allowing the signal to go between port 1 and 2. This shouldgive a signal path with transmission line properties.

Figure 3.4: Signal path in Case2

Case 2: To access port 3 the supply voltage is set to 3 V. Now the PIN-diodeswill conduct. Remembering the properties of a λ/4 transmission line in conjunctionwith a ground reference it is now visible that junction 1 (see gure 3.4) will now betreated as a "high impedance" in the direction of port 2, thus forcing the signal to gothough the PIN-diode. On the other side of the PIN-diode the same method is appliedto force the signal towards port 3. This time a λ/4 transmission line in conjunctionwith a λ/4 radial stub is used to create a virtual ground reference, creating the signalblocking "high impedance". Since the distributed component approach is dependent ontransmission line length, and thus a single frequency, using the radial stub allows for alarger bandwidth.

In order to design this circuit the main building blocks and component models hadto be determined. First the λ/4 transmission line length had to be determined. Sincesignal velocity and thus wavelength is dependent on the substrate properties these mustbe entered in the transmission line calculating tool (see Appendix A.1). Using LinCalc

16


Figure 3.5: S21 in Case1 Figure 3.6: S21 in Case2

the transmission line width which determines the characteristic impedance (Z0) of thetransmission lines, with the given substrate parameters, can be calculated. In this casethe width is 0.535 mm.

In order to use the PIN-diode in ADS a PIN-diode model must be assigned. Valuesfor the PIN-diode can be found in the data sheet for the TOSHIBA JPD2S05FS PIN-diode.

Figure 3.7: PIN-Diode Model

Once the λ/4 transmission lines and PIN-diodes are determined the remaining circuitcan be designed. In order to assemble the PIN-diodes and the resistor surface mountingpads are needed, specic dimensions for these are given in the PCB layout section. Theremaining transmission line lengths are arbitrary but should be kept short.

With an acceptable design in schematic it is now necessary to convert the designto a layout representation (see gure 3.9). However, since this design contains lumped

17


Figure 3.8: Schematic representation of the Switch in ADS

components, simulations cannot be performed in the momentum simulator. The way togo is to use the layout component function in ADS. This allows for momentum/schematicco-simulation, using EM-simulation on all copper traces while schematic combines theseresults with the lumped components in the schematic representation.

Figure 3.9: Layout representation of the Switch in ADS

After converting the Layout into a Layout Component it can be added to theschematic by using the component library.

18


Figure 3.10: Layout Component in Schematic

3.2.2 Filter

The function of a bandpass lter is to lter out signals outside the desired frequencyspectrum. In this case the pass-band is between 5.15 and 5.35 GHz. For frequenciesbelow 4.95 GHz and above 5.55 GHz the lter is supposed to attenuate all signals withat least 20 dB.

Using distributed elements desired lter characteristics are achieved by combiningseveral coupled transmission lines elements. To save space on the PCB one of the mostpopular and common way is to bend those coupled lines like hairpins and they are hencecalled coupled hairpin lters.

Figure 3.11: Fourth-order bandpass lter of coupled-line and hairpin coupled-line type

Characteristics of coupled line lter depend on several parameters (see g. 3.12), themost important parameter is length (l) in the coupled region, the spacing (S) betweenthe couplings and the line width (W). The length of the coupled regions is expected to besome were around λ/4 of the desired center frequency. Spacing has most impact on theattenuation while width and length have a larger impact on the behaviour regarding tothe centre frequency, impedance and ripple within the passband but it is the combinationthat matters. The order of the lter depends on how many coupled regions are used,for the same order, hairpin lters have one more coupled region than normal coupledline lters. Higher order lters have steeper slopes but the drawback is that attenuationwithin the passband becomes larger.Designing the lter in ADS was done by using a design guide for passive circuits withmicrostrip lines. Choosing a desired lter type, hairpin in this case, lter order and/or

19


Figure 3.12: Coupled section Figure 3.13: Simulation comparison be-tween schematic and layout

desired pass- and stop-bands the program generates a good starting point for a designin schematic. The rst thing to check on the generated design is that all physicaldimensions pass the design restriction. In this case the minimum line separation of 75µm was not fullled since one of the coupled region had a separation of only 38 µm.When the desired characteristics were achieved with fullled design restrictions a layoutwas generated and simulated. Simulation results on the layout showed a much narrowerpassband than desired and hence a lot of parameter adjustment must be done at thelayout level. An example of how large the dierence can be between schematic andlayout simulations with the exact same parameters is seen in gure 3.13.

Figure 3.14: Final lter dimensions

When the desired lter characteristics were obtained at the layout level, the nextstep is to create a layout component so it can be used in schematic together withother components but still be simulated with Momentum. A schematic view with alldimensions of the nal fourth order hairpin lter is showed in gure 3.14.

20


3.2.3 Balun

Balun is an abbreviation of balanced to unbalanced, this implies that the signal pathis transformed from balanced to unbalanced or vice versa. The purpose of the balun inthis design is to transform a singlended output to dierential outputs. The signal is splitinto two paths and hence the attenuation of the measured output signal will be at least3 dB lower than the input signal. A balun can be done in several ways. In this diplomawork two dierent types (see gure 3.15) were designed and measured, but only type2 was used in the nal front-end layout. Both types make use of half the wavelength(λ/2) to separate the signal into two signals with a phase dierence of 180 degree. Withthe chosen substrate parameters a λ/2 is close to 17.5 mm.

Figure 3.15: Dierent balun types

Type 1 is designed with a single-ended signal coming in from port P1, while portP2 and P3 are the output for the balanced dierential signals. The line connected toP1 is a λ/2 microstrip with a open end, while the two lines connected to P2 and P3 areλ/4 with shorted ends. Signal outputs from P2 and P3 are supposed to have a phasedierence of 180 degree over the whole passband, this is achieved quite easyily withbalun type 1 and is therefore the major advantage for this type. The disadvantage withbalun type 1 is the narrow bandwidth with respect to attenuation. This is mainly dueto the design restriction of 75 µm line spacing.

Balun type 2 is a much simpler design. It just splits the signal up in half and let oneof the signals travel a distance of λ/2 longer than the other and in that way create thephase dierence of 180 degree. This design provides a much wider bandwidth than thetype 1 balun, but the phase shifting of 180 degree is highly frequency dependent and isonly achieved well for the center frequency.

The design of these components was mainly done on the layout level, this is due tothe experience gained from the lter design when large dierence in behavior betweenschematic and layout were observed. There is no Design Guide in ADS for this type ofcomponent, the design must be done manually. The design process is to set the lengthto a value near the λ/2 and λ/4, and then simulate and modify the parameters untilthe desired behaviour is achieved. The next step is to generate a layout component sothe component can be simulated together with the rest of the system.

Two dierent baluns were designed, the reason for this was that balun type 1 reduced

21


the bandwidth for the whole system too much when it was put together with the rest ofthe system. For the interest of testing, balun type 1 was still produced and measured.

3.2.4 RF Choke

Both the LNA and the PA output terminals must be connected to the DC supply. Withboth the RF-signal path and the DC path connected at the same terminal a componentthat can separate the two is needed. The RF choke component is used for this purpose.By using the λ/4 eect it is possible to prevent the RF-signal from escaping through theDC network. Recalling the distributed components section in chapter 2, if a transmissionline has its starting point in a short circuit, λ/4 away will be an open circuit. To generatean RF short circuit a radial stub is used, in the point where the radial stub is attachedto the transmission line an RF-short circuit is created. At this point an RF-signalwill experience a very low impedance (virtual ground). Connecting this known lowimpedance to a λ/4 transmission line an RF-signal high impedance (open circuit) pointis generated at the opposite end of the transmission line.

Figure 3.16: RF choke

Functional verication of this component was rst done in schematic with both one andtwo radial stubs. With two radial stubs in both sides of the transmission line a widerbandwidth for the virtual ground reference is achieved. The extra bandwidth is notneeded since one radial stub has enough bandwidth for this project, for that reason andto save space on the PCB the single stub version was chosen.

The design of the single stub RF choke moved on to the layout representation. Theparameters that aect the behaviour of the radial stub are the length, the angle of thestub and the size of the junction connecting the radial stub with the λ/4 transmissionline. Since almost all transmission lines in this project have the width of 0.535 mm, theonly parameter that can be adjusted for the λ/4 line is just the length. Using LinCalcwith the Rogers 4350B substrate parameter gives a λ/4 of 8.78 mm. On the layoutlevel the desired behaviour of the component were found and the nal combination ofparameters can be seen in gure 3.17. This is simulated without either DC or signalpath connected. A layout component with the required parameters is now generatedand used in the rest of the system.

22


Figure 3.17: RF choke dimensions

3.2.5 LNA

The main function of a Low Noise Amplier (LNA) is to amplify the signal while addingas little noise as possible.

Since most commercial LNA circuits are often unstable and not matched to a stan-dard impedance (such as 50 Ω), stabilisation and matching networks are needed. Thisallows the designer to customise the LNA circuit to t dierent requirements. In thiscase the most critical requirement is the noise gure, which must be < 2.1 dB.

Figure 3.18: S2P block in ADS

In order to work with an active component in ADS a data le is needed. For theMAX2649, MAXIM supplies a s-parameter le, which is available from their website.Using this s-parameter le the amplier can be simulated in ADS by using a S2P block(see gure 3.18). To simulate the amplier properties an amplier design guide in ADSis used. This design guide makes a data display template representing all gures ofinterest such as Gain, noise gure and Rolett factor etc.

As seen in the simulation of the Rolett factor for the unstabilised LNA (see gure3.19), the value is less than 1 (= unstable) above 3.7 GHz.

Four dierent attempts to stabilise the LNA gave the results in table 3.4. As seenin the table any type of resistor stabilisation on the input side yielded a substantially

23


Figure 3.19: Rolett factor for unstabilised LNA

Table 3.4: Stabilising LNA at 5.25 GHz

Placement of Resistor Input Output

Alignment Shunt Series Shunt Series

Resistance (Ω) 38 6 117 9

Rolett faktor (k) 1.013 1.005 1.001 1.043

Max Power Gain (dB) 17.327 17.595 17.841 16.743

NFmin (dB) 3.324 3.245 1.910 1.920

Gain when matched to NFmin (dB) 13.233 13.206 12.959 12.695

higher NFmin than the stabilisation on the output side. As these values already exceedthe preferred noise gure of 2.1 dB this stabilisation method is rejected. Thus the choicestood between shunt or series stabilisation on the output side. The shunt alternativewas chosen due to the fact that it yielded a higher gain and a more manageable resistorsize.

Realising that the stabilisation resistor could hardly be mounted directly on theoutput terminal of the LNA chip, as in the case when regarding the ideal simulationresults, the foot print was studied (see gure 3.20). The stabilisation point must beshifted 1 mm out from the RF-out pad and the transmission line joining the pad mustbe 0.2 mm wide, in order to avoid interference from other pads. Thus a new stabilisationresistance must be calculated.

Simulating the LNA with the added transmission line reveals that the output im-pedance has changed and that the amplier must be stabilised with a 37 Ω shunt resistor.At this point the input and output matching networks can be designed. In order to de-sign these matching networks the source and load impedances must be found. UsingADS and the amplier design guide the preferred source impedance is simply picked ina Smith Chart (see gure A.2). Once these impedances are determined the design of

24


Figure 3.20: Footprint of LNA and resistor pads

the matching networks can begin.

Figure 3.21: LNA input matching network

Designing the input matching network (IMN) requires two impedances, not only thepreviously determined source impedance of the LNA but also the output impedance ofthe switch. The input impedance of the IMN is set to 50 Ω and the output impedanceis the complex conjugate of the LNA source impedance. Applying these values in theSmith Chart tool, a matching network can be designed. Using the Smith Chart tooloption "Build ADS Circuit" produces a network of transmission lines (see gure 3.21). Inorder to produce a layout the ideal transmission lines must be converted to microstriplines. This can be done by synthesising width and length in LinCalc by using theobtained elecrical length and characteristic impedance. Replacing the transmission linesin the matching network with microstrip lines enables the design to be converted toa layout representation. When simulating the IMN with microstrip lines instead oftransmission lines an apparent dierence is observed, since these components behavein a more realistic fashion in terms of parasitic eects, the stability of the circuit isaected. This calls for a new stabilisation resistance. The new stabilisation resistance isdetermined to be 47 Ω. An important thing to do before conversion is to add T-junctionsbetween the microstrip lines. Otherwise the junctions will be treated as oating andthus causing alignment problems when converted to the layout.

After conversion to the layout representation (see gure 3.22) the IMN must besimulated in Momentum. Since the schematic and layout simulations are dierent inprinciple, results will vary. Therefore the IMN must be adjusted such that it producesthe desired imdedances. This can be done by changing the length of the microstrip lines.

25


Figure 3.22: LNA IMN Figure 3.23: LNA OMN

Once the IMN is adjusted to the desired input and output impedances a layoutcomponent can be produced. The layout component is then used with the amplierdesign guide to see if the amplier is matched as intended.

The design of the output matching network (OMN) is almost identical to the IMN,the only dierence is that instead of matching to 50 Ω, the LNA must be matched tothe input impedance of the balun.

Figure 3.24: Matched LNA

When the design of both the matching networks is complete the matched LNA issimulated to determine if the matching is adequate. With stabilisation and matchingnetworks completed the LNA is now ready for use in the radio front-end.

26


3.2.6 PA

The Power Ampliers (PA) function is as its name implies to amplify the signal power.These ampliers are commonly used when transmitting signals. Since this kind of am-plier usually is the last active device in the transmitter chain a low noise gure is notas critical as in a LNA, thus allowing for more gain.

Port impedances of PA at 5.25 GHz

RF-In (Ω) 11 + j14

RF-Out (Ω) 13 + j5

The design of this amplier circuit was carried out in a slightly dierent manner withregard to the LNA. Since no s-parameter le was available the IMN and OMN must bedesigned using impedances obtained from the MAX2841 data sheet. This also impliedthat the design could not be simulated in ADS.

Since the port impedance of the Switch and the Filter are approximately 50 Ω, thePA must be matched to 50 Ω at both sides. As in the case of the LNA the Smith Charttool is used to produce a matching network template. Using LinCalc the obtained theproduced transmission lines are converted to microstip lines (see gure 3.25 and 3.26).

Figure 3.25: PA IMN in Schematic Figure 3.26: PA OMN in Schematic

Figure 3.27: PA IMN in Layout Figure 3.28: PA OMN in Layout

The matching networks are converted to the layout representation (see gure 3.27and 3.28) and simulated using Momentum. The networks are adjusted to producethe desired input and output impedances. When acceptable values are acquired thematching networks are converted to layout components.

Joining these matching networks with the PA-footprint a usable layout for the PAis now complete.

27

3.3. PRINTED CIRCUIT BOARD LAYOUT CHAPTER 3. DESIGN PROCESS

3.3 Printed Circuit Board Layout

Once all components were completed the entire system could be integrated. The primarytask was to arrange all components and add DC blocking capacitors to prevent leakage.DC blocking is needed at all external ports except the Tx-port, since the lter preventsDC currents. DC blocking is also needed between the switches and the LNA/PA. DCblocking is done by connecting a small capacitor between two microstrip lines. The sizeof the capacitor is determined by the frequency, since the capacitor must behave as ashort circuit at the operating frequency. In order to mount the DC blocking capacitorsSMD pads are needed. Dimensions of these pads are taken from a soldering guidecomposed by the company AVX, sizes for wave soldering are used due to that both waveand manual soldering require fairly large pads.

Figure 3.29: SMD pad Dimensions

In this design 0805 size components are used for resistors and 0603 size are usedfor capacitors. In order to perform measurements on the radio front-end, SMA con-nectors are needed. The SMA connector is surface mounted, though the component isdesigned for trough hole mounting. Through hole mounted pins are used for DC andcontrol. Since a soldermask is used to dene solderable surfaces, soldermask layers forprimary and secondary side are dened. These layers are used for all SMD components(Capacitor, Resistor, PIN-Diode, SMA, LNA & PA) and the through hole mounted pins.

LNA & PA footprints are designed using recommended dimensions, found in thedatasheets (see gure 3.30 & 3.31, dimensions in mm).

Figure 3.30: LNA Footprint Figure 3.31: PA Footprint

Once all the radio front-end components and DC block capacitor pads have beenplaced the layout is examined in order to detect any layout conict. As expected, layout

28

3.3. PRINTED CIRCUIT BOARD LAYOUT CHAPTER 3. DESIGN PROCESS

conicts occur. The LNA IMN and PA OMN overlap, creating a short circuit (AppendixB.1). The PA IMN and LNA OMN are also too close to allow for DC and control signaltraces. The LNA & PA input matching networks are repositioned and bent in order toaccommodate DC and control traces. The matching networks are once again simulatedto ensure the proper function (Appendix B.2).

Now that the signal path layout is complete the DC and control traces can be applied(Appendix B.3). All DC carrying traces are complemented with decoupling capacitors(Appendix B.5) to remove high frequent noise. Designs for SHDN networks (Shutdownwhen 0V) are taken from the MAXIM evaluation kit design (Appendix B.6). The PAbiasing and power determination (P_DET) networks are also taken from the evaluationkit design (Appendix B.7 & B.8). RF chokes are added to both LNA & PA RF outports.

The last step in the layout process is to design the primary side ground plane. Themost important parameter to control is the isolation distance to the microstrip lineswhich should be at least 1mm, this to decrease signal crosstalk. Once the primaryside ground plane (Appendix B.4) is dened, microvias connecting the primary andsecondary side ground planes are placed.

Since the thickness of the RO4350B substrate is only 0.254 mm, an additional sub-strate of FR4 is added to provide some rigidity to the entire PCB. The two substratesare fused together with a FR4 prepreg (see gure 3.32).

Figure 3.32: PCB layer denitions

29

Chapter 4

Implementation

In order to study the individual components, small test PCBs for each component aredesigned. The purpose of these test PCBs is to allow closer examination of speciccomponents, and possibly to determine which component that causes unexpected eects.The layout of these test PCBs is kept as close as possible to that in the entire radiofront-end.

4.1 PCB Manufacturing

Since PCBs are manufactured in panels an entire panel layout must be created. Thepanel dimension chosen for this design is 305x460 mm, which allows for 269x424 mmusable area for placing PCB designs.

Once the components are placed in the panel layout the design must be convertedinto a le type that can be managed by the PCB manufacturer, in this case GerberX.This conversion produces a layout where each layer is dened separately, allowing themanufacturer to select a specic layer for a specic process.

For this design the following layers were used:

• Primary & secondary side soldermask layers (negatives) dene where an openingin the solder mask should be made.

• Metal layers 1-4 dene the 4 metal layers.

• The hole layer denes the position of the vias.

• The routing layer denes how the PCBs will be cut from the panel.

4.2 Assembly

The assembly except the LNA & PA devices is performed inhouse. Since there is noip-chip mounting equipment in this institution, the ip-chip assembly was made at IVF(Industrial Research and Development Corporation in Gothenburg).

30

Chapter 5

Measurement Setup

To perform measurements in the RF region a Rohde&Schwarz ZVM Vector NetworkAnalyser is used, which can measure from 10 MHz up to 20 GHz. Most of the measure-ments in this project are done between 4 and 6 GHz and some between 1 and 10 GHz.

Figure 5.1: Rohde&Schwarz network analyser

Measuring in the RF region requires the use of S-parameters. A network analyser uses asource to sweep the frequency within a desired interval and with a test device connectedbetween port 1 and 2 the incident, reected and transmitted waves are detected andS-parameters can be presented. Recalling from chapter 2, S-parameters that representtransmission from port 1 to port 2 and from port 2 to port 1 are S21 and S12, respec-tively. Magnitude represented with logarithmic scale (dB) as a function of frequency isnormally used to present S21 and S12. Presenting how well a port on the test device isimpedance-matched S11 (port 1) and S22 (port 2) are used. The network analyser canpresent results in a Smith Chart diagram.

To be able to do the measurements with the network analyser the test devices areconnected to the ports with two coaxial 50-Ω cables. SMA-connectors are mounted onthe PCBs so the cables can be attached.

31

5.1. INITIAL MEAS. PROBLEMS CHAPTER 5. MEASUREMENT SETUP

5.1 Initial measurement problems

The SMA-connectors used are intended to be through-hole-mounted, but in this projectthey are used for edge mounting. To the left in gure 5.2 is the SMA-connector and itconsists of ve legs, the one in the middle is the signal connector and the other four areground connectors. When used as a surface-mounted component it is attached on theedge of the PCB and two ground connectors are connected on the secondary side, thesetwo connectors work both as ground connection and to x the SMA-contact to the PCB.Since two of the ground legs are not in use, they are removed to prevent unexpectedeects. The signal connector is also modied (see gure 5.2) it is cut to reduce thelength and in that way prevent it from introducing unwanted parasitic eects on thesignal.

Figure 5.2: SMA-connectors Figure 5.3: SMA soldered to the edge ofthe PCB

Initial measurements on the lter, which was the rst component to be measured, showedcharacteristics very far away from the expected. The reason for this was found to bethe SMA-pads. The original SMA-pad size used in designing the components had awidth of 2 mm and a length of 3 mm, which is quite large according to the substratethickness of 0.254 mm. The pad together with the ground plane works as a capacitorand hence introduces a lot of undesired capacative eects. The width of the pads werereduced to t the width of the transmission lines, i.e. 0.535 mm. The other reason ofthe unexpected characteristic was a mistake when dening via holes between dierentground planes. This resulted in a oating ground plane. The solution was to solder onthe edges of the cards and the SMA-connectors such that a good ground connection wasachieved, see gure 5.3. Measurement results were now closer to the expected and theseprocedures were done on every component before measurement.

32

Chapter 6

Results

Simulation and measurement results are presented in this chapter.

6.1 Component Measurements

Measurement results for the test components are presented in this section.

6.1.1 Switch

Since the switch has three ports that must be measured and the network analyser onlyhas two, the third port on the switch is matched to 50 Ω by using a terminator. Tocreate the control signal a voltage source producing 3 V is used.

The most important property of the switch is the forward transmission (S21 andS31), since it denes the signal attenuation of the dierent paths in the switch.

Figure 6.1: Switch test component

33

6.1. COMPONENT MEASUREMENTS CHAPTER 6. RESULTS

Figure 6.2: Simulated S21 and S31

Figure 6.3: Measured S21 Figure 6.4: Measured S31

Figures 6.2, 6.3 and 6.4 present the simulation and measurement results when theswitch has a control voltage of 0V. In this case S21 should be close to -0.1 dB, whichcan be seen in the simulated results. The measured results show a S21 of -2.8 dB st5.25 GHz. S31 on the other hand should be as high as possible, isolating port 3 fromthe signal. Simulated results for S31 show -50 dB while measurement shows -12 dB.

34


Figure 6.5: Simulated S21 and S31

Figure 6.6: Measured S21 Figure 6.7: Measured S31

Figures 6.5, 6.6 and 6.7 present the simulation and measurement results when theswitch has a control voltage of 3V. In this case S31 should be close to -0.5 dB at 5.25GHz, attenauation increases slightly compared to the previous case due to the resistancein the PIN diode. The measured results show that S31 is -4.2 dB at 5.25 GHz. S21 onthe other hand should be -16 dB at 5.25 GHz according to simulations. The measuredresult shows that S21 is -7.2 dB at 5.25 GHz.

35


6.1.2 Filter

Figure 6.8: Simulated lter Figure 6.9: Measured lter

Simulated and measured S21 results for the lter are showen in gures 6.8 and 6.9.The measured lter has a displacement of 250 MHz for the pass-band and the centrefrequency is 5 GHz. At this new pass-band the signal is attenuated -4.2 dB. Simulatedlter is attenuated -3.2 dB within its pass-band. Simulated S11 = 39.3−j1.65 and S22 =39.9− j2.75 at 5.2 GHz. Measured values are S11 = 69.3+ j44.3 and S22 = 97.0+ j28.9.

36


6.1.3 Balun

When measuring the balun the port that is unused must be terminated to 50 Ω. Simu-lated and measured S21 and S31 results for balun type 1 are showen in gures 6.11, 6.12and 6.13. Comparing to the simulated results, the pass-band is displaced by 350 MHzin the frequency band.

Figure 6.10: Balun test components type1 (top) and type 2 (bottom)

Figure 6.11: Simulated S21 and S31 fortype1

Figure 6.12: Measured S21 for type1 Figure 6.13: Measured S31 for type1

37


Figure 6.14: Simulated S21 and S31 for type2

Figure 6.15: Measured S21 for type2 Figure 6.16: Measured S31 for type2

Simulated and measured S21 and S31 results for balun type 2 are showed in gures6.14, 6.15 and 6.16.

Table 6.1: Balun attenuationBalun type1 type2

Simulated at 5.25 GHz S21 (dB) -3.9 -3.55

Measured av 5.25 GHz S21 (dB) -17.1 -4.95

Simulated at 5.25 GHz S31 (dB) -3.9 -3.68

Measured av 5.25 GHz S31 (dB) -11.4 -4.17

Within the pass-band the attenuation for balun type2 is much better than for type1.For type2, measured S31 is only 0.49 dB lower than the simulated, see table 6.1. Astrange dipping eect within the pass-band pulls down the performance of balun type1.Looking in the displaced pass-band for type1 the attenuation is larger than 5 dB andtype 2 outperform type1 even taking this into account.

Phaseshift for the two types at 5.25 GHz are 154.9 degree for type1 and 195.6 degree

38


Table 6.2: Balun phaseshift in degreesBalun type1 type2

Simulated at 5.0 GHz 180.4 188.9

Measured at 5.0 GHz 192.5 186.4

Simulated at 5.25 GHz 180.0 180.0

Measured av 5.25 GHz 154.9 195.6

for type2, simulated result is 180 degree. At 5.0 GHz both types shows better results,phaseshift for type1 is 192.5 degree and for type2 186.4 degree, see table 6.2. At thisfrequency type2 show better measured result then simulated.

39


6.1.4 RF Choke

Measuring the RF choke is done by measuring the attenuation in the signal path. Aground reference is connected instead of the DC network. The S21 results is seen ingure 6.17. At 5.25 GHz simulated S21 = −0.1dB and measured S21 = −1.33dB.

Figure 6.17: Simulated and measured S21

Figure 6.18: RF choke test component

6.1.5 LNA

When measuring the LNA the RF-input port is connected to port 1 on the networkanalyser and RF-output is connected to port 2. A voltage of 3 V is applied to SHDNand DC-supply pins. As maximum gain was obtained with a supply voltage of 2.2 Vthese results are also shown.

40


Figure 6.19: LNA test component Figure 6.20: Simulated S21

Figure 6.21: Measured S21 at 3V Figure 6.22: Measured S21 at 2.2V

Figures 6.20, 6.21 & 6.22 display the parameter S21 in dB as a function of frequency.The simulated result (gure 6.20) shows a gain of 12 dB at the frequency 5.25 GHz,which coincides with the measured result using a 2.2 V supply voltage. While themeasured result using a supply voltage of 3 V has a gain of 10 dB at 5.25 GHz.

Table 6.3: LNA S21 at key frequenciesFrequency (GHz) 5.15 5.25 5.35

Simulated (dB) 12.1 12 11.6

Measured at 3V (dB) 10.2 10.3 9.8

Measured av 2.2V (db) 12.2 12.5 12.2

41



Figure 6.25: Simulated S11

Table 6.4: LNA S11 at key frequenciesF (GHz) 5.15 5.25 5.35Sim. Ω (79+j101) (132+j123) (266-j60)M. 3V Ω (48-j27) (49-j26) (32-j17)M. 2.2V Ω (63-j35) (34-j28) (25-j27)

Figures 6.25, 6.23 & 6.24 display the parameter S11 in a smith chart. As mentionedpreviously S11 corresponds to the systems input impedance.

42



Figure 6.28: Simulated S22

Table 6.5: LNA S22 at key frequenciesF (GHz) 5.15 5.25 5.35

Sim. Ω (51+j8.6) (44+j2.6) (31-j7.5)M. 3V Ω (55-j35) (37-j13) (61-j1.5)M. 2.2V Ω (57-j45) (31-j10) (66-j8.9)

Figures 6.28, 6.26 & 6.27 display the parameter S22 in a smith chart. S22 correspondsto the systems output impedance.

43


6.1.6 PA

When measuring the PA port 1 was connected to RF-input and port 2 to RF-output.A voltage of 3 V was applied to SHDN to activate the amplier. The supply voltage forthe amplier was set to 3 V. In this design maximum gain was obtained when the biasvoltage was set to 1.5 V,while recomended voltage is 1.9 V. Both cases are measuredand presented. No simulations were possible during the design phase due to the lack ofan S-parameter le.

Figure 6.29: PA test component

Measurements for the PA show that a gain of 22 dB is obtaned at 4.95 GHz withthe bias voltage set to 1.5 V. With the bias voltage set to 1.9 V the gain is 19dB at thesame frequency.

Figure 6.30: Measurement S21 at 1.5Vbias


44






Table 6.6: PA s-parameter values at 1.5 V biasFrequency (GHz) 4.95 5.15 5.25 5.35

S21 (dB) 22.06 17.22 15.63 13.84

S11 (Re+Im)Ω -109.5+j87.96 -31.56-j93.18 -3.891-j66.46 -0.975-j42.97

S22 (Re+Im)Ω 1.245+j52.60 41.36+j163.1 198.2+j180.1 289+j12.25

Table 6.7: PA s-parameter values at 1.9 V biasFrequency (GHz) 4.95 5.15 5.25 5.35

S21 (dB) 18.93 15.16 13.49 11.88

S11 (Re+Im)Ω -126.3+j144 -21.02-j105.9 1.239-j69.45 1.861-j43.74

S22 (Re+Im)Ω 7.033+j55 48.96+j144.6 177.9+j159.9 262.9+j16.20

45

6.2. RADIO FRONT-END MEASUREMENTS CHAPTER 6. RESULTS

6.2 Radio Front-End Measurements

Measurements on the front-end are carried out in two sets. Rx measurements requirethree ports to be measured, in this case a 50 Ω terminator is connected to the port thatisn't currently measured. A voltage of 3 V is applied to SHDN and 2.2 V to DC-supplypins on the LNA. When measuring Tx there is only need for two ports. A voltage of 3V was applied to SHDN to activate the PA. The supply voltage for the amplier is setto 3 V and the bias voltage was set to 1.5 V. Due to poor performance the switches arebypassed in both cases.

Figure 6.36: Simulation Rx S21 & S31

Figures 6.36, 6.37 & 6.38 show the forward transmission for the front-end Rx. Themaximum gain for the simulated front-end Rx path is 4 dB at 5.3 GHz, while themeasured results show a maximum gain of 0 dB at 4.9 GHz.

46


Figure 6.37: Measurement Rx S21


47


Figure 6.39: Simulation Rx S11


48




49




50


Figure 6.45: Measurement Tx S21

Figure 6.45 shows the measured forward transmission for the front-end Tx. Themaximum gain of 17 dB is obtained at 4.8 GHz.

51




52

Chapter 7

Discussions

Measuring the components showed a displacement of the pass-band for all componentsexcept the LNA. The main reason for this is due to the soldermask. During the designprocess the soldermask was not incorporated in the substrate model. The soldermask isa dielectric, thus adding another dielectric layer on top of the microstrip lines causingthe velocity of propagation to decrease. This lowers the center frequency of the entirecircuit.

Table 7.1: Soldermask propertiesMaterial Soldermask

Dielectric thickness 15-25 µmDielectric constant 4.5 ± 0.05Dissipation factor 0.033

Comparing simulations with and without the soldermask shows that displacement.A lter simulation using the two dierent substrate models is seen in gure 7.1. Thesimulation results show a smaller displacement than the measured results. However thecomparison shows that the soldermask is the major reason for the pass-band displace-ment. However the reason why the soldermask dooes not have the eect on the LNAtest component has not been found.

The size of the SMA-pads also aects the signal characteristics. The original SMA-pad size is 2 mm in width and 3 mm in length. The pad together with the ground planeproduces capacitive eects. When designing the components, these large pads werenot taken into account. Simulation done with a model that takes the large pads andthe soldermask into account shows large dierences. Comparison between measuredand simulated results of the lter using these models are seen in gure 7.2 and 7.3.Reducing the width of the pads to t the transmission line, i.e., 0.535 mm, a betterresult is achieved, see gure 7.4 and 7.5. Even with the reduced width, some parasiticsare introduced and will aect the characteristics of the components. Using the substratemodel with soldermask and the small pad-model the simulation of the whole system givesresults similar to the measured ones (see Appendix D.1 and D.2). The soldermask andthe pad size are the major reasons that measured results dier from the expected.

53

CHAPTER 7. DISCUSSIONS

Figure 7.1: Substrate model comparison in simulation

The way that SMA-connectors are used in this project also introduces much parasiticeects. Measurements done on a transmission line connected with two SMA-connectorsgives proof for this assumption. Figure 7.6 shows that a signal is attenuated with almost-0.6 dB and within the pass-band the attenuation is even larger, an attenuation up to-1.4 dB is measured within the pass-band. These eects within the pass-band are alsoobserved in the balun type2 and the RF choke (see chapter 6). One reason for this eectmight be that these components have a signal path that includes a transmission linelonger than λ/4, wich might introduce some missmatch.

As can be seen in the measurement results the switch does not perform well. Theattenuation is much larger than what was expected. A reason for this might be thatthe small capacitance in the pin diodes reduces the isolation when the PIN diodes areturned o. In order to replicate these conditions the PIN diodes are replaced with asmall capacitor (0.32pF) and a large resistor (1.5MΩ). The Simulation in this caseproduces results that are closer to those obtained from measurements (see AppendixD.3, D.4 and D.5). To replicate the on state for the PIN diodes the diode is replacedwith a small capacitor (0.32pF) and a small resistor (1.5Ω). The Simulation in this casealso produces results that are close to those measured (see Appendix D.6, D.7 and D.8).This might prove that the PIN diode model used in ADS has diculties handling theseconditions.

To prevent these eects a compensating network for the PIN diode can be used. Byadding a shunt connected inductor, a resonance can be created for the desired frequency.Given the capacitance of the PIN diode and desired frequency a value for the inductorcan be calculated by using f = 1/(2π

√LC). This network should increase the isolation

in the PIN diode.

54


Figure 7.2: Simulated large pad Figure 7.3: Measured large pad

Figure 7.4: Simulated small pad Figure 7.5: Measured small pad

55


Figure 7.6: S21 measured on a transmission line with SMA-connectors

56

Chapter 8

Conclusions

The goal of this project was to produce a design of a 5 GHz radio front-end using ADS,and use this design to build a prototype. This prototype should then be measured inorder to determine if designs for 5 GHz using distributed components on a laminatesubstrate can be successfully produced.

Since a design has been produced using ADS and a functional prototype has beenbuilt, the goals for this project are reached.

Some conclusions that can be drawn from the obtained results in this project arethe following. When designing a switch for use at the 5 GHz a compensating networkfor the PIN diode must be used in order to achieve a good isolation. Distributed edgecoupled lters at 5 GHz are dicult to produce on a laminate with good results, sincethe PCB process requires a large spacing. This is also true for the edge coupled balun(type 1) in this project. The simpler type of balun (type 2) can be successfully producedwith regard to attenuation but the phase characteristics are more sensitive to processvariations. The measurements for the RF choke show that the expected behaviour canbe obtained. The LNA design can be successfully produced using ADS with expectedresults. Both measurements and simulations show that the soldermask model must beincluded in the design.

Lessons learned from this project are among many things that accurate modellingis crucial for a successful design. In this project this has been most apparent in thesubstrate model, the PIN diode model and the SMA pad model.

57

Chapter 9

Further work

Suggested further work in this area is to develop a multiple layer design, since edgecoupled components like the lter and the balun are dicult to produce with good resultsusing a double layer PCB process. Using proper surface mounted SMA-connectorsand high Q lumped components over 5 GHz could reduce parasitic eects. Anotherinteresting task is to develop a proper compensating network for the PIN diode.

58

Bibliography

[1] Reinhold Ludvig, Pavel Bretchko: RF Circuit Design - Theory and Applications,Prenctice Hall 2000, ISBN 0-13-095323-7

[2] David M. Pozar: Microwave Engineering, ISBN 0-471-17096-8

[3] Shaofang Gong, Magnus Karlsson and Adriana Serban: "Design of a radio front-endmodule at 5 GHz", Proceedings of the IEEE 6th Circuits and System Symposiumon Emerging Technologies, Vol.I, P.241-244, 2004.

[4] Maxim-Ic, http://www.maxim-ic.com, 2004-03

[5] TOSHIBA Semiconductor,http://www.semicon.toshiba.co.jp/eng/index.html, 2004-04

[6] Microvawe Encyclopedia,http://www.microwaves101.com/encyclopedia/index.cfm, 2004-09

59

Appendix A

Tools

To calculate transmission line length and width a tool called LinCalc in ADS can beused.

Figure A.1: Calculate transmissionlines using LineCalc in ADS

60

APPENDIX A. TOOLS

To simulate gain, noise and stability of an RF amplier a design guide is used inADS to view simulated data in a predened data output sheet.

Figure A.2: Select source impedance in Smith Chart

61

APPENDIX A. TOOLS

The Smith Chart tool in ADS can be used to create matching networks. Thesenetworks can then be built in a Smith Chart component and be used to determine theelectric length of the transmission lines.

Figure A.3: Smith Chart tool in ADS

62

Appendix B

PCB Layout

Figure B.1: Signal Path Figure B.2: Adjusted Signal Path

Figure B.3: DC Trace Figure B.4: Ground Plane

63

APPENDIX B. PCB LAYOUT

Figure B.5: Decoupling Capacitors Figure B.6: Shutdown Circuit

Figure B.7: Bias Circuit Figure B.8: Power Determination

• B.5 Decoupling Capacitors remove highfrequent noise in DC traces.

• B.6 Deactivates PA & LNA when set to 0V.

• B.7 Bias voltage for the PA.

• B.8 Power determination function in PA.

64

Appendix C

Schematics

Schematic drawings of the PCBs that require surface mounted components.

Figure C.1: Schematic of the LNA test PCB

65

APPENDIX C. SCHEMATICS

Figure C.2: Schematic of the PA test PCB

66

Appendix D

Additional simulations and

measurements

Simulating the Rx path of the front-end with soldermask substrate.

Figure D.1: Simulation of front-end Rx S21 with soldermask model

Comparing the simulated result that uses the soldermask substrate modell (D.1)with the measured result (D.2) the same shift in the passband can be seen.

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APPENDIX D. ADDITIONAL SIMULATIONS AND MEASUREMENTS

Figure D.2: Measured front-end Rx S21

Figure D.3: Simulated switch S21 & S31, new PIN diode model

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Figure D.4: Measured switch S21


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Figure D.6: Simulated switch S21 & S31, new PIN diode model


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