design and development of a cpld board revised v2.0 1 new version

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Design of a Development Board for a Low-Cost Wireless Automation and Security System in a Condominium

Roger Jay M. Mortos Webster A. Palang Edric Marc E. Peña

James Rex R. Salazar Bianca Divina C. Vales

Technological Institute of the Philippines

Manila

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Table of Contents

Chapter 1. Project Background ...................................................................................................................... 1

The Project ................................................................................................................................................ 1

Project Objectives: ..................................................................................................................................... 2

Specific Objectives: ................................................................................................................................... 2

The Client .................................................................................................................................................. 2

Project Development ................................................................................................................................. 3

Project Scope and Limitations ................................................................................................................... 4

Chapter 2. Design Inputs ............................................................................................................................... 5

The Existing Site ........................................................................................................................................ 5

Project Site ................................................................................................................................................ 6

Wireless Local Area Networks (WLAN)/ Wi-Fi ........................................... Error! Bookmark not defined.

Bluetooth ................................................................................................... Error! Bookmark not defined.

Design Considerations ............................................................................................................................. 18

Energy – per – packet: ........................................................................... Error! Bookmark not defined.

Delay (D) ............................................................................................... Error! Bookmark not defined.

Received Signal Strength Indicator(RSSI) ............................................. Error! Bookmark not defined.

Chapter 3.Project Design ............................................................................................................................. 21

Design 1. CPLDs .................................................................................................................................... 22

Option 1.Altera ......................................................................................................................................... 23

Altera Components List ....................................................................................................................... 25

Option 2: Xilinx ........................................................................................................................................ 31

Xilinx Components List ........................................................................................................................ 45

Design 2: Microcontroller ......................................................................................................................... 45

Option 1 ATMEL ...................................................................................................................................... 63

Arduino Component Lists .................................................................................................................... 64

Option 2.Zilog .......................................................................................................................................... 66

Zilog Components List ......................................................................................................................... 75

Chapter 4. Constraints, Trade – offs, and Standards ..................................................................................... 3

Design Constraints .................................................................................................................................... 3

Economic ............................................................................................................................................... 3

Manufacturability.................................................................................................................................... 3

Sustainability ......................................................................................................................................... 3

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Design Standards ...................................................................................................................................... 4

Trade-Offs ................................................................................................................................................. 5

Economic ............................................................................................................................................... 5

Components and Price of All Design ..................................................................................................... 5

Chapter 5 Final Design ................................................................................................................................ 12

Conclusion ............................................................................................................................................... 32

List of Figures

Figure 1-1.Flow Chart of Project Development .............................................................................................. 3

Figure 2-1.Actual View of Domus Mariae Condominium ............................................................................... 5

Figure 2-2.Map of Domus Mariea Condominium 3 ........................................................................................ 5

Figure 2-3.Domus Mariae Conduminium 3 Ground Floor Plan ...................................................................... 6

Figure 2-4.Domus Mariae Conduminium 3 2nd -5th Floor Plan ..................................................................... 7

Figure 2-5. Domus Mariae Conduminium 3 Roof Deck Plan ......................................................................... 8

Figure 2-6. Domus Mariae Conduminium 3 Section Elevation Plan .............................................................. 9

Figure 2-7. Domus Mariae Conduminium 3 Gate ........................................................................................ 10

Figure 2-8.Domus Mariae Conduminium 3 Hall Way ................................................................................... 10

Figure 2-9. Domus Mariae Conduminium 3 Ramp ....................................................................................... 11

Figure 2-10. Domus Mariae Conduminium 3 Unit Door ............................................................................... 11

Figure 2-11. Domus Mariae Conduminium 3 Unit Kitchen/Living Room ...................................................... 12

Figure 2-12. Domus Mariae Conduminium 3 Bed Room ............................................................................. 12

Figure 2-13. Magnetic System ..................................................................................................................... 13

Figure 2-14. Microcontroller ......................................................................................................................... 14

Figure 2-15.Sensors .................................................................................................................................... 14

Figure 2-16. MAX 7000E and MAX 7000S Device Block Diagram .............................................................. 15

Figure 2-17. Xilinx CPLD supposed visual look ........................................................................................... 16

Figure 2-18. Eagle CAD ............................................................................................................................... 16

Figure 2-19. Altera Quartus II ...................................................................................................................... 17

Figure 2-20. Xilinx ISE ................................................................................................................................. 18

Figure 3-1.CPLDs ........................................................................................................................................ 21

Figure 3-2. Altera Block Diagram ................................................................................................................. 22

Figure 3-3. Pin-Out Diagram ........................................................................................................................ 23

Figure 3-4. AND Gate Array ........................................................................................................................ 24

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Figure 3-5. Input/Output Block ..................................................................................................................... 25

Figure 3-6.LAB ............................................................................................................................................ 26

Figure 3-7.Macrocell .................................................................................................................................... 27

Figure 3-8.OR Gates ................................................................................................................................... 28

Figure 3-9.Output Gates .............................................................................................................................. 29

Figure 3-10. PAL (Prorammabble Array Logic) ............................................................................................ 30

Figure 3-11. PIA ( Programmabble Interconnection Array) .......................................................................... 31

Figure 3-12.XOR Gates ............................................................................................................................... 32

Figure 3-13.Verilog Program ....................................................................................................................... 33

Figure 3-14. Simulation of Verilog Program ................................................................................................. 34

Figure 3-15.Altera Schematic Diagram ........................................................................................................ 35

Figure 3-16. Architechture Altera PCB Layout ............................................................................................. 36

Figure 3-17. XC9500XL Architechture ......................................................................................................... 37

Figure 3-18 to 33. Simulation of Xilinx ................................................................................................ 38 to 46

Figure 3-34. Schematic of Light Openner .................................................................................................... 47

Figure 3-35. Xilinx Schematic Diagram ........................................................................................................ 48

Figure 3-36. Xilinx PCB Layout .................................................................................................................... 49

Figure 3-37. Pinout of ATmega 2560 ........................................................................................................... 50

Figure 3-38. Arduino Schematic Diagram .................................................................................................... 51

Figure 3-39. Arduino PCB Layout ................................................................................................................ 52

Figure 3-40. Zilog Schematic Diagram ........................................................................................................ 53

Figure 3-41. Zilog PCB Layout .................................................................................................................... 54

Figure 3-42. Zilog PCB Component Location .............................................................................................. 55

Figure 5-1. Altera Schematic ....................................................................................................................... 65

Figure 5-2. Altera PCB Layout ..................................................................................................................... 66

Table 4-1. Xilinx Total Price ......................................................................................................................... 58

Table 4-2. Altera Total Price ........................................................................................................................ 59

Table 4-3. Arduino Total Price ..................................................................................................................... 60

Table 4-4. Zilog Total Price .......................................................................................................................... 61

Table 4-5. CPLD Trade Off .......................................................................................................................... 62

Table 4-6. Microcontroller Tradeoff .............................................................................................................. 63

Table 4-7. Microcontroller vs. CPLD ............................................................................................................ 64

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Table 5-1. .................................................................................................................................................... 65

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Chapter 1. Project Background

The Project

Automation or automatic control is the technique, method, or system of operating or controlling a process by highly automatic means, or by electronic devices such as microcontrollers, reducing human intervention to a minimum. Year after year, brand new technology emerges that generally eases one’s life. It is no wonder that various processes of automating has found itself into the common household. Home Automation can be simply defined as the automatic control of anything electronic within the home. A smart home however, is the integration of the different systems inside the house such as lighting, multimedia, security, and any system which are handled by a control system which is then controlled by the users with the help of a centralized control device. A smart home tends to be quite expensive since some of the required equipment are highly priced in the market. A complex programmable logic device (CPLD) board is specifically used for automation. CPLDs contain numerous logic blocks; each of it includes eight to 16 macrocells. Each logic block executes a particular function; all of the macrocells inside a logic block are fully connected. Depending upon the application, however, logic blocks may execute vice versa. A microcontroller board is a board embedded with the circuitry needed to controller a microchip. It can be altered depending on the function desired to be executed. The microchip mounted on a microcontroller completes the board to act as a microcomputer and performs the command programmed in the programmable integrated circuit it holds. The Domus Mariae Condominium 3 is a project of the Domus Mariae Foundation, a church incorporated group about 11 years old, which provides socialized housing for needy families. It is a non-stock, non-profit organization that was established on February 24, 1983. The foundation’s main objective is to help the urban poor and have suitable inexpensive dwelling either on site or in relocation sites to help them live in dignity. This 84 studio – type unit, five storey medium rise was built just this 2007 on a 580 square meter land owned by the Archdiocese. This project employs the usage of the same Smart home technology to be used for a low-cost condominium. The design project will focus on designing programmable boards that can be use a controller for the automation system.

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Project Objectives:

Design and develop a Complex Programmable Logic Device (CPLD) or a microcontroller board programmed to function for automation and security system.

Specific Objectives:

Program a smart lighting that could turn on and off automatically.

Program a security access in the form of magnetic cards.

Program a burglar alarm system.

Design a layout and schematic diagram of a CPLD board for Xilinx and Altera.

Design a layout and schematic diagram of a microcontroller for Atmel and Zilog. The Client Domus Mariae 5 Storey Low-Cost Condominium at Pandacan, Manila that is a medium rise with an 84 studio type units of 22.5 square meters each on a 580 square meter land supervised by Engr. Hernan of Domus Mariae Foundation.

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Project Development

Figure 1-1. Flow Chart of Project Development

Figure 1-1 shows the project design flow and more likely, a framework of the whole system’s progression, and functions as a guide to be able to distinguish all the important aspects of the design. The first process on this project design is to do a site inspection for placement of equipment to be utilized in this design and determine possible problems that will occur for the design project where there will always be constraints to consider. In line to this, there will be equipment trade-offs until the client’s constraints are met, then the project design will be finalized as stated above.

Yes

Yes

No

Address possible problems and

define solutions

Design Project and Consider the

Constraints

Are all

Constraints

Considered?

Evaluate Alternative Designs

(Trade - Offs)

A

B

Inspect Location

Start

Yes

No

No Are the alternative

designs much better?

A

Apply Trade – Off results in

Project Design

Did the results finalize

the Project Design?

B

End

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Project Scope and Limitations

The scope of this project design will be concentrates on automation system for Domus Mariae Foundation, Inc. at the 2002 Jesus Street Pandacan, Manila. There will be trade-offs for equipment which will have a further discussion about their specification and amount value in the remaining chapters below. The scopes of this project are the following:

Design of a smart lighting to turn on/off automatically.

Design and develop a CPLD board that has specific function for automation.

Design an automated door system that is connected to the CPLD Board through Bluetooth.

The limitations of the design are the following:

The existing room plan will be the basis for the automation, thus the proponents will only focus on that existing floor plan.

The economic factor will be based on the client’s budget, and the location of the proponents will use a design based on the price capacity of the client.

The availability and cost of the equipment to be used or installed in the project will stay nominal.

The design of the CPLD board to be used in this project is specific only to its components.

The number of inputs of the development boards is limited to the presented design.

Sensitivity of the devices or equipment to be interfaced in CPLD Board will be based on the program and the specifications according to the equipment’s manufacturer themselves.

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Chapter 2. Design Inputs

The Existing Site

Figure 2-1. actual view of Domus Mariae Condominium Figure 2 – 1 shows the actual view of Domus Mariae Condominium, a 5 – storey medium rise, low – cost residential consisting of 84 studio – type units in a 580 square meter of land nestled in the busy streets of Paco, Manila.

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Project Site

Figure 2-2. Map of Domus Mariea Condominium III

Figure 2-2 shows the actual location of Domus Mariae Low-Cost Condominium which is located at Lot 10 & 11, BLK 6, Ducepec St., Paco Manila City near Unilever as a landmark. The Domus Mariae has studio type units that feature 1 bedroom, 1 living room, 1 dining room, and 1 bathroom.

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Figure 2-3. Domus Mariae Conduminium 3 Ground Floor Plan Figure 2-3.shows the ground floor of the Domus Mariae Conduminium 3 which consists of 16 units with an area of 22.5 square meters per unit. The area doesn’t have existing monitoring system.

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Figure 2-4. Domus Mariae Conduminium 3 2nd -5th Floor Plan

Figure 2-4 shows the 2nd-5th floor of the Domus Mariae Conduminium 3 which consists of 17 units with an area of 22.5 square meters per unit.

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Figure 2-5. Domus Mariae Conduminium 3 Roof Deck Plan Figure 2-5 shows the roof deck of the Domus Mariae Conduminium 3 which is an open space. The site also doesn’t have existing monitoring system.

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Figure 2-6. Domus Mariae Conduminium 3 Section Elevation Plan Figure 2.6 shows the section elevation plan that explains the height of the building and the multipurpose area which is a ramp and the stairs and gates of each floor.

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Figure 2-7. Domus Mariae Conduminium 3 Gate Figure 2-7 shows the actual gate of Domus Mariae Conduminium 3 this is locked and opened manually by a person who manages the gate. The proponents suggested putting a magnetic lock on the gate.

Figure 2-8. Domus Mariae Conduminium 3 Hall Way Figure 2-8. Show the existing hall way of Domus Mariae Conduminium 3 where there are no guards roaming to secure the area. The residences of Domus Mariae Conduminium 3 hold the monitoring of their unit.

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Figure 2-9. Domus Mariae Conduminium 3 Ramp Figure 2-9. Shows the existing ramp of Domus Mariae Conduminium 3 which is same as the hallway but with security for bikes and motorbikes.

Figure 2-10. Domus Mariae Conduminium 3 Unit Door Figure 2-10 shows the unit door of Domus Mariae Conduminium 3 with a manual lock where there will be an installation of sensors for every door wherein the time doors open and close will be registered to the data base of the monitoring system.

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Figure 2-11. Domus Mariae Conduminium 3 Unit Kitchen/Living Room Figure 2-11 shows the kitchen of Domus Mariae Conduminium 3 wherein the utilities of the unit are manually operated.

Figure 2-12. Domus Mariae Conduminium 3 Bed Room

Figure 2-12 shows the bed room of Domus Mariae Conduminium 3 which is the same as the kitchen where there will be automated system.

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WIFI WIFI is a wireless technology standard popular nowadays as a wireless networking technology that uses radio waves with a low-power, high-range, radio technology and known for its capability to send signals with high speed and more than two networking devices. WIFI device is designed to replace an interconnection means for devices and peripherals but has evolved into having a more sophisticated usage. WIFI has said to evolve each generation expanding the generic use in terms of a wireless network technology however, WIFI functions different from Bluetooth and other wireless technology in terms of its capacity, security, speed and distance. WIFI technology has been part of IEEE’s 802.11 standards which use 2.4 Ghz and 5.2 Ghz frequency band. The frequency used by 802.11 falls in the unlicensed band and specifically, exact frequency used and how they used depends on whether the system follows 802.11b, 802.11a, 802.11g or 802.11n.

Figure 2-13. Magnetic System

Figure 2-13: Shows the magnetic system used in the gate or door of the Domus Mariae Condominium 3 with an electric locking device that will meet the demand for monitoring system of most rigorous building and safety codes for remote controlling or access control, with a typical holding capacity of 600lbs to 1200lbs that requires power to remain locked for high monitoring application.

Figure 2-14. Microcontroller Figure 2-14 shows a microcontroller, a programmable device which allows reading the inputs from the external devices. This can range for both analog and digital devices serving a wide variety of purpose like

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security system for sending and receiving data to execute the application significantly faster that will offer more flexible for advance use a wide variety of interfaces, standard serial line and wireless.

Figure 2-15. Sensors

Figure 2-15 shows a variety of sensors. These are impressive devices with a compact dimensions that can be used in some large application like in automation system.

Figure 2-16. ALTERA EPM7064 or MAX 7000 Device

Figure 2-17 shows the CPLD and actual image considered for the project, Altera’s MAX 7000. It is a high-density, high-performance PLD. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 is said to provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.

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Figure 2-17. Xilinx CPLD supposed visual look

Figure 2-18 shows the other CPLD and actual image included for this project. The XC9572XL is described as a 3.3V CPLD intended for high-performance, low-voltage applications in leading-edge communications and computing systems as per Xilinx datasheet. Its four 54V18 Function Blocks aims to provide 1,600 usable gates with propagation delays of 5 ns.

Figure 2-18. Eagle CAD The image shown in Figure 2-18 is the software to be used in designing any development board, CPLD or microcontroller. Eagle is an abbreviation for Easily Applicable Graphical Layout Editor or in its developer’s naïve language, German: Einfach Anzuwendender Grafischer Layout-Editor. This software is from CadSoft Computer that is describe as a flexible, expandable and scriptable EDA application with schematic capture editor, PCB layout editor, auto-router and CAM and BOM tools. The software has downloadable freeware license giving a wide range of component availability.

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Figure 2-19. Altera Quartus II

The image above, labeled as Figure 2-19, is the program from the CPLD manufacturer that is Altera. Altera Quartus II is a PLD specific design software able of analysis and synthesis of HDL designs, which developer can compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus includes an implementation of VHDL and Verilog for hardware description, visual editing of logic circuits, and vector waveform simulation.

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Figure 2-20. Xilinx ISE

Figure 2-20 shows the image of a Xilinx ISE, the counterpart of Altera Quartus II. Xilinx ISE or Integrated Synthesis Environment is a software tool for synthesis and analysis of HDL designs, enabling the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

Figure 2-21. JTAG USB Blaster

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The image shown is of a JTAG connector in a form of USB. This standard and technology is used to

program and debug the CPLDS in the designs presented in this project. JTAG which stands for Joint Test

Action Group implements standards for verifying designs and testing of printed circuit boards. It can be a

tool for digital simulation of on- chip instrumentation in electronic design automation.

Figure 2-22. CoolRunner CLPD

Above is an image of CoolRunner circuit used to program CPLDs. This is interfaced in the development

board to be able to program the chip mounted in the board. It can access and manipulate the capabilities of

the CPLD used the designed board.

Design Considerations The performance of home automation system is checked according to different parameters. The following considerations where accounted in each design.

Current Consumption/ Operating Current The current consumption or operating current is a direct proportional factor to be computed in obtaining the power consumption. Below are the formulas used for the said parameter:

Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode

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MC = Total number of macrocells used f = Clock frequency (MHz)

Where: MCTON = Number of macrocells with the Turbo Bit option turned on,

as reported in the MAX+PLUS II Report File (.rpt) MCDEV = Number of macrocells in the device MCUSED = Total number of macrocells in the design, as reported in the MAX+PLUS II Report File (.rpt) fMAX = Highest clock frequency to the device togLC = Average ratio of logic cells toggling at each clock (typically 0.125) A, B, C = Constants

Power Dissipation Wasted power is often in the form of too much heat radiated from the device. Aside from the fact these are considered losses; integrated circuits (ICs) have the tendency to get damaged by thermal causes.

Where: P = Power Dissipated, in mW Vcc = Voltage Source

Speed This parameter is specified in the datasheet of the device. It defines how fast the device can respond, usually in Mhz units. Memory This describes the information capacity of a device, how many functions it can perform, and how much program it can handle. Data Retention Another specification that can be found in the datasheet, it informs how long the program embedded in the device will be retained.

Slew Rate The unit of this parameter is in seconds. It defines how long it takes, often in nanoseconds, for a certain value in voltage to change to another voltage level.

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Chapter 3. Project Design

Figure 3-1. Design Tree Diagram

The diagram above represents the structure of this project design. There are two major categories,

microcontroller and CPLD. The bottom level shows the four manufacturers of chips that were taken into

consideration for the development board design, two marquees for each category and one layout for each

manufacturing label. All programmable devices having their respective advantages were methodically

assessed by the proponents.

CPLD Board

Microcontroller

Based

ATMEL ZILOG

CPLD Based

XILINX ALTERA

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Design 1. CPLDs

Figure 3-2. CPLD The figure shows the CPLD Block Structure, it is a combination of a fully programmable AND/OR array and a bank of macrocells. The AND/OR array is reprogrammable and can perform a multitude of logic functions. Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths. Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. This performance boost came at the cost of very high current requirements. An innovative all-digital core makes it possible to achieve the same levels of performance at ultra-low power requirements. This allows designers to use the same CPLD architecture for both high-performance and low-power designs.

The removal of analog sense amplifiers also makes the architecture scalable, allowing for aggressive cost reduction and feature enhancement with each successive process generation

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Option 1. Altera

Design 1

Figure 3-3. Altera Block Diagram

Figure 3-3 shows the typical block diagram of a EPM7064-J84 CPLD. The diagram shows that the chip

consists of four Logic array block, and each LAB consist of 16 macrocells that corresponds to the specific

I/O control blocks. Each macrocells is connected to each other using the Programmable Interconnection

array. The clock or oscillation is connected to the GLCK1 or Global Clock.

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Figure 3-4. Pin-Out Diagram

Figure 3-4 shows the pin diagram of the EPM7064 CPLD. It has 84 I/O ports not including the GND, VDD

and VCCID pin outs.

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Figure 3-5. Altera Schematic Altera Components List

Resistors

64 pcs. – 330 ohm

1 pc. – 1 M ohm

1 pc. – 1 K ohm

1 pc. – 390 ohm

6 pcs. – 220 ohm

5 pcs. – 470 ohm

2 pcs. – 100 ohm Semiconductors

1 pc. – EPM7064-J84

1 pc. – NE555

1 pc. – PIC182550_28W

1 pc. – LM317TS

1 pc. – HC49UP(Crystal)

1 pc. – LED Capacitor

1 pc. – 47 nF (Ceramic)

2 pcs. – 100 uF (Ceramic)

2 pcs. – 100 uF (Electrolytic)

1 pc. – 0.1 uF (Electrolytic)

1 pc. – 0.33 uF (Electrolytic)

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Figure 3-6. Power Supply Schematic

Power Supply (LM317)

To stabilize the voltage at the adjustment pin

To improve transient response

For reverse bias circuit protection

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Current Consumption

Power Dissipation

Speed

Memory

Data Retention

Slew Rate

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Figure 3-7. Altera PCB Layout

Figure 3-7 shows the pcb layout of the Altera CPLD device. The EPM7064-J84 is in series by 330 resistor

to protect the the I/O pins against accidental short circuit cooperation with desired voltage by limiting the

current of clamp diodes. The board is supplied with a LM317 voltage regulator that has a ranged of 3v-6v.

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Design 2

Figure 3-8. Altera Design 2 Schematic

The second design for Altera shown in the figure above is implemented with RS232, a Universal

Asynchronous Receiver Transmitter (UART), the a widely used serial datacommunication circuit. The

general purpose of this UART are a microprocessor interface, double buffering of tranmitter data, frame

generation, parity generation, parallel to serial conversion, double buffering of receiver data, parity

checking, serial to parallel conversion.

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Figure 3-9. PCB Layout of Altera Design 2

The image above is almostt he same as the first pcb layout of the Altera design 1, the only difference is the

use of RS232 whose function was described in the description of this design’s schematic.

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Figure 3-10. AND Gate Array

This figure shows the combination set of AND gates to construct a programmable array that was connected

to the input with a specific number in the PAL, which are connected to the fixed programmable OR gates.

Pins are configurable in such things that was included in the architectural attributes, interfacing the output

and input in the configuration of programmable array on the size and arrangements of gates. A

programmable logic array composed of many input and one output is shown in the figure. To form

complemented and true in a both array to the routed inputs with combinations possible that provide

programble interconnection points via AND gates are connected to the inputs. The logic function with a

programmed and logical diagram form with one output and many inputs are drawn. The logic diagram

indicated can be inter-connected in a desired function, with a particular logic function to implement in

programmed array.

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Figure 3-11. Input/Output Block

The figure above shows the registered device with a eight dedicated input lines, and each combinational

output is an I/O pin, the figure shows many dedicated input lines and eigth output of the combinational

outputs. Buffers for dedicated vice inputs have complementary ouput to provide user programmable input

signal polarity. Unused input pins should be tied to VCC and GND. The pinout has been designed to

minimize the noise that can be generated in high speed signals, short leads and multiple ground signals

reducing the effective lead inductive, minimizing ground bounce. Placing ground pins between the outputs

optimizes and isolates from each other elimaniting cross talk. This pinout can reduce the propagation delay

as much of 20% as if the device has a standard 20 pin DIP pinout for most design software.

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Figure 3-12. LAB

This figure shows the SPLDs or usually called LAB of the CPLD that includes several gate arrays

connected in a provided PIA. Any input and output of LAB as well any pin of the chip can be connected

one to another thourh the PIA. CPLDs themselves as well as LABs of CPLDs are quite advance device

such as Altera that use a 16 macrocells and have a 36 inputs with a 4 LABs that are all connected to the

PIA. They contain several logic module with a local interconnection array and logic modules are the

fundamental bricks of the CPLDs like the macrocells are the fundamentals blocks. Logic modules are

based on the LAB and less complex than the macrocells. I/O blocks are located around the perimeter of the

gate array and configurable which can operate as input/output or bidirectional buffers. An CPLDs may have

a huge number of logic modules and LABs was configurable memory is also extremely large. Due to this

huge volume CPLDs are either one-time programmable or configured from RAM. The RAM is located with

configuration data right at power-up from a boot flash that may be internal,but usually is external.

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Figure 3-13. Macrocell

This figure shows the Macrocell of CPLDs is more complicated which includes a flip-flop that can be

programmed for D, T, RS and JK operation. They also include hardware dedicated for cascading of

macrocell such as parallel and shared expanders. The parallel expansion assumes that the term allocation

matrix of macrocell has special inputs that can be directly connected to other outputs of the macrocells that

allows their cascaded use. The shared expanders are bases on the PALs, In order to provide that TAM has

special path that connects an AND element to PIA through an inverter. Inverted product then passed

through another AND element thus providing and additional sum of products. Configurations of CPLDs are

directly controlled from their internal flash memory that allows using them with less number of extra

components.

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Figure 3-14. OR Gate

This figure show the OR array for logical function that need only specify the truth table for the set of

function. In CPLDs there is no need for logic minimization since all possible input combinations are

provided in the AND array. As well pointed out, a OR array provides the complete set of input combination

in the AND array bus most logic function however this is completely unnecessary and may result to a

wasted ciruitry on the chip.Particularly when a large number of inputs are required, the OR array structure

become impractical when a logic function of 16 input and 8 output variables are desired. To implement

such function in a CPLDs it would have to use a 64K by 8bit PROM device, regardless of the complexity of

the logic function. A PROM of this size would be a highly ineffecient for most logic functions, it can be

implemented with far less than 2 product terms. To more efficiently map logic functions with a larger

number of inputs, the PLA and PAL device were developed. The PLA structure is the basis for virtually all

PLDs in use today. The complete PLA structure is the basis for a variety of PLDs and provides greatest

flexibility in how product terms are allocated to the OR gates and associated outputs.

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Figure 3-15. Output Gates

This figure show the output gates which the output of the CPLDs has a three state output buffer with three

state control. On combinational outputs, a product term controls the buffer, allowing enable and disable to

be function of any product of device inputs or output feed-back. The combinational output provides a

bidirectional I/O pin and may be configured as a dedicated input if the output buffer is always disabled. On

registered outputs, an inputs pin controls the enabling of the three state outputs. A control device to the I/O

pin to prevent them from floating during device programming,powerup and erased device. It can

deactivated in a normal operation. independent slew rate control with output edge rate may be slow down

to reduce noise thourgh programming.

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Figure 3-16. PAL (Prorammabble Array Logic)

This figure shows the PAL where it implement a boolean logic transfer function, the sum of products. The

PAL device is programmable AND array driving a OR array. The AND array is programmed to create

custom product terms, while the OR array sums selected terms at the outputs. The PAL devices provide

the variable input and output pin ratio where it programmed the three state outputs and register with a

feedback. Product terms with all connections opened assume the logical high state and to both true and

complement of any single input assume the logical low state. Register consist of D-type flip-flop that are

loaded on the low to high transition of the clock. Unused input pins should be tied to VCC or GND. PAL

device programmed with appropiate design and socket adapter modules. Once the PAL device

programmed and verified, an additional connection may be opened to prevent pattern readout. This feature

secures proprietary circuits.

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Figure 3-17. PIA ( Programmabble Interconnection Array)

This figure show the design of PIA in a CPLDs which combine with a locally effcient logic block with a

globally flexible interconnect structure to provide ideal connectability for a very large spectrum of designs.

The key qualities of the logic block which have a 36 input signals presented to logic block. An automatic

allocation of product terms as needed within the function block. The average is 5 product terms per

macrocell, but up to 15 are easily obtained and up to 90 can be used when needed. Formation of efficient

counters, multiplexers, shifters and parity circuits with an efficiency of one macrocell or less per bit. The

remaining logic is available for use by other functions. Any input pin connects to any function block with

constant high speed across the entire device. Macrocell output can connect to its own or any other function

block with no restriction. Macrocell can be internally bused with bit level independent 3 state control,to form

internal data buses with global access to all logic blocks.

39

Figure 3-18. XOR Gate

This figure show the implementation of NOR gates since realization of AND and OR gates in the CPLDs

are difficult and generally use more delays and chip area than NAND or NOR, with complemented outputs

is equivalent to an OR and a NOR gate with complemented inputs is equivalent to an AND gate. NOR

gates use for generating of minterms and circuit outputs. To keep functionality and activity levels of inputs

and outputs intact extra inverters are used on the circuit inputs and outputs. These inverters are highlighted

the outputs, Although NOR gates are used the left plane is still called the AND plane and the right plane is

called the OR plane. Implementation of the logical gates or circuits are difficult in routing wires and building

gates with large number of inputs. This became more complicated when we are using arrays with many

inputs, such as 16 inputs which used for combinational circuits that has a 64k minterms. In the AND plane

wires from circuit inputs must be routed to over 64k NOR gates, while on the OR plane the NOR gates

must be large enough for every minterm of the function to reach their inputs. Such an design is very slow

because of long lines and takes too much space because of the requirments of large gates. The solution to

this problem is to distribute gates along array rows and columns. In the AND plane instead of having a

clustered NOR gates for all inputs to reach, The NOR gate is distributed along the rows of the array. The

NOR gate that implements minterm was distributed transistor level logic of this NOR gate structure.

40

Figure 3-19. Verilog Program

The figure shows the verilog command used in the Altera CPLD board design. In this here command,

simple declaration of inputs and outputs where first thought of, next would be the designation of these

outputs to its corresponding number of inputs. A simple logic design is used in this that uses the three

inputs which then would result in the output which in this case is the light for a particular room opening. The

inputs here represent the number of sensors to be used in the design alongside the light that will open once

the proper conditions are met.

41

Figure 3-20. Simulation of Verilog Program

In this figure, a functional simulation of the program used in the Altera MAX7000s cpld board is shown. It is

the timing analysis between the inputs and the resulting output. Each input has its own variation of timing

range. The square wave represents the whole sample which is seen as high if the logic level is 1 and low if

the logic level is 0. This simulation is made to see the transitioning logic levels of each input as well as see

the resulting output.

42

Interfacing the Devices

Figure 3-21. Zigbee Module

Zigbee is a device based on an IEEE 802.15.4 standard that can create networks between points. It is a

low power consumption ideal low rate data transfer. Because of these properties this devices was chosen

for the interfacing of the designed board to the applications this project is intended for.

Design 1

Figure 3-22. Block Diagram of the System (Computer)

In this design the, sensors used was a motion sensor that transmits wirelessly to the Zigbee Transceiver

Module and relays the data gathered from the sensor over a modem to the other part of the data transfer

pair. When received, this data is then sent to a computer where it will be processed and then forwarded into

the CPLD where the information will be analyzed. After this step, it is sent back through the computer and

then again to the Zigbee Module Transceiver which will relay the data to the devices to trigger it either ON

or OFF.

Zigbee Module

Transceiver Computer

Device 1 Device 2 Device 3

Sensors Zigbee Module

Transceiver Modem

CPLD

Zigbee Module



43

Design 2

Figure 3-23. Block Diagram of the System (UART)

This design shows the process of ZigBee technology that can be used in automation. The setup makes use

of the technology’s low cost implementation and low speed to control the homes’ systems wirelessly.

The motion sensor or PIR, in this case, sends the information to the ZigBee Transceiver Module. This then

sends it through a modem onto the receiving part of the module.

Figure 3-24. UART Data Flow Diagram

This figure shows the UARTs data flow which, for this application, connects the ZigBee module to the

CPLD which analyzes and processes the data from the sensors. It then sends this processed information to

another receiver that relays the received data into triggering signals that switches these devices into

operation.


Transceiver Modem Zigbee Module

Transceiver UART

CPLD Zigbee Module

Transceiver

Device Device Device

44

Option 2. Xilinx

Figure 3-25. XC9500XL Architechture This figure shows the architechture for a typical CPLD of Xilinx. It is a subsystem consisting of Function Blocks and I/O Blocks Fully interconnected by the FASTCONNECT II switch matrix. Each Function Blocks provides programmable logic capabiity with 54 inputs and 18 outputs. The inputs and outputs are designated by the macrocells which may be configured for a combinational or registered function.

45

Figure 3-26. Xilinx Schematic Xilinx Components List

Resistors

34 pcs. – 330 ohm

1 pc. – 240 ohm

1 pc. – 390 ohm

1 pc. – 1 M ohm

7 pcs. – 100 ohm

1 pc. – 1 k ohm

1 pc. – 5 k ohm


1 pc. – XC9536

1 pc. – LM317TS

1 pc. – TLC555

2 pcs. – 74HC125

1 pc. – 1N4001 diode

2 pcs. – Bat41 Capacitors

1 pc. – 47 nF

1 pc. – 10 nF

2 pcs. – 100 uF

6 pcs. – 100 uF

4 pcs. – 100 pF

46






47

Current Consumption

Power Dissipation

Speed

Memory

Data Retention

Slew Rate

48

Figure 3-28. Xilinx PCB Layout

This figure shows the PCB layout for Xilinx CPLD Board. The board can work with both XC9536 which is a

version of circuit powered from 5V. The circuit is powered by a selectable output voltage power supply

LM317TS from 3.3 up to 5.5v. Each pin is in two versions, the standard which is not secured and the

secured which is in series with the 330 ohm resistor to protect the I/O pins against accidental short-circuit.

Without the resistor inputs would be burned in a short time.

49

Design 2

Figure 3-29. Xilinx Design 2 Scematic

The second design for Xilinx shown in the figure above is implemented with RS232, a Universal





50

Figure 3-30. Xilinx Design 2 PCB Layout

The figure showing a pcb layout showcases the Xilinx design with the RS232 implemented. The same

alteration done in the design 2 of the Altera is applied here.

51

Figure 3-31. Simulation Output

The figure above shows the graphical representation of the simulation output. The pulses indicate whether

the output is low or high or whether it is in the on or off condition.

Figure 3-32. Program Code

52

For figure 3-26 designated the wire of AO2-AO6 as output and for line 46 – line 64 of the program shows

the instantiate of the UTT which the process before initialization.

Figure 3-33. Program Code (cont.)

Figure 3-27 shows the program line 65-79 is the end of instantiate of the UTT. And for line 81 stated to

initial begin for inputs for line 81 to 84, line 87-90 and line 92-95 run the condition of inputs then show the

output in AO1 pin port in ISIM. The value 0 means that the sensor detected no movement, the value 1

means that the sensor detected a movement.

53


Figure 3-28 shows the continuation of the conditions for IA1, IA2, IA3 inputs which are in program line 97-

100, 102-105, 107-110, 112-115, 117-120. And for 122-125 is another set of inputs for the output AO2.

54


For Figure 3-29 shows the continuation of the conditions for inputs IA5, IA6 and IA4.


Figure 3-30, the continuation for conditioning of inputs.

55


Figure 3-31, continuation for conditioning of inputs.



56




Figure 3-34 continuation for conditioning of inputs.

57





58





59


The figure above shows in line 3 the timescale for simulation and for line 8-31 register IA1 – IA 24 as

inputs.


Figure 3-40 show the CPLD reports for the program simulated.

60

Figure 3-47. Schematic of Light Openner

Figure 3-41 shows the schematic diagram which will be converted to VHDL code. Inverter is the sensor

which will be placed at the door either is open or closed means if it is close the value is 1 and vise versa

then connected to 1 input of the 2 AND gate as the sensor placed within the range.

Interfacing the Devices


61




Design 1







or OFF.

Design 2




Transceiver UART

CPLD Zigbee Module

Transceiver


Zigbee Module




Transceiver Modem

CPLD

Zigbee Module



62









operation.

63

Design 2: Microcontroller

Option 1 ATMEL

Figure 3-52. Pinout of ATmega 2560

Figure 3-37 shows the pinout of ATmega168 which is a low – power CMOS 8 bit microcontroller based on

AVR enhanced RISC architechture. It has 23 pinouts with 16KB ISP flash memory, 1KB SRAM, 512B

EEPROM, an 8-channel/10-bit A/D converter (TQFP and QFN/MLF), and debugWIRE for on-chip

debugging. The device supports a throughput of 20 MIPS at 20 MHz and operates between 2.7-5.5 volts. It

uses C++ language to code its information and has a capacity of 20 years data retention.

64

Figure 3-53. Atmel Microcontroller Schematic

Atmel Microcontroller Component Lists

7805 Voltage Regulator

2 LED

2 220Ω Resistor

1 10KΩ Resistor

2 10µF Capacitor

16MHz Clock Crystal

2 22pF Capacitor

ATMEGA 168

Momentary Tact Switch

65

Figure 3-54. Atmel PCB Layout

Figure 3-44 shows the PCB layout for Atmel Microcontroller using the ATmega 168 microchip. The board is

designed with 23 Digital I/O pins, a 16 MHz crystal oscillator, a usb serial converter cable, a power jack, an

ICSP header and a reset button.

Current Consumption

Power Dissipation

Speed Memory Data Retention

Slew Rate

66

Interfacing of Devices

WIFI Based

Figure 3-55. WIFI- based System Block Diagram

This figure shows a WIFI based sensor capable of using secure accounts in standard web protocol to

ensure the program to be sent in a home router making new deployment an easy task.

Motion Sensor

Figure 3-56. PIR Sensor

This figure shows the motion sensor used connected to the WASPMOTE with a pyroeletric sensor mainly

consisting of an infra-red receiver and a focusing lens that can detect the reflection of movement by setting

its output signal high.

Wireless

Sensor Nodes

(WASPMOTE)

Motion Sensor (PIR)

Router

ETHERTEN

Arduino

Relay

Relay

Relay

Device 1

Device 2

Device 3

67

The 10 µm spectrum corresponds to the radiation of heat from the majority of objects as they emit

temperatures around 36ºC. The maximum detection direction goes perpendicular to the sensor board, this

is why it is advised to place WASPMOTE perpendicular to the ground when using the PIR sensor.

The code used for reading the PIR sensor

int value; SensorEventv20.ON(); delay(10); value = SensorEventv20.readValue(SENS_SOCKET7);

Value is an integer variable where the sensor state a high value (1), indicating a presence, or a low value

(0) will be stored. WASPMOTE configurations allow connecting up to six sensor probes at the same time

where the perimeter access control such liquid presence detection and doors or windows openings. The

sensor data gathered by the nodes is sent to the gateway router that is easier to receive which parse it and

store the data into a local or external data base.

Using Ether Ten, the gateway router is connected to the microcontroller board which is the head of the

operation that control the opening of the devices, and these devices are then connected to relay driver.

This can work alongside the exiting remotes to turn on and off the relay and a fly back diode to protect the

transistor and Ether Ten from the voltage spike generated by the device. This process is shows in the

figure below.

Figure 3-57. Connection of Sensors to Router to the Microcontroller

68

This figure shows how the sensors are connected through wifi to the router that is then connected to the

microcontroller, which controls the devices.

Bluetooth Based

Bluetooth technology is the wireless automation used in this process. Standards based and low power

Bluetooth technology enables the development of devices’ application.

Figure 3-58. Bluetooth- based System Block Diagram

This figure shows how blue technologies control a system of lighting, door and windows lock with an

application. It can simplify daily task by setting up alerts about their home.

The PIR is connected to the Bluetooth shield card. The data detected will be sent to the Bluetooth Module

and can be controlled by a microcontroller or an arduino shown below in figure.

Relay

Relay

Relay

Device 1

Device 2

Device 3

Bluetooth

Shield

Motion Sensor (PIR)

Bluetooth Module

Arduino

69

Figure 3-59. PIR connected to Bluetooth Shield

This figure shows the PIR sensor used as a triggering device for the Bluetooth module connected to the

microcontroller for opening the device.

The Bluetooth module is configured or interfaced with the microcontroller while it does the main processing

part for the control, i.e. switching ON and OFF a relay. The relay acts a switch for AC appliances shown in

the figure below.

Figure 3-60. Process of Automation System Using Bluetooth Technology

The figure shows a system able to turn ON/OFF appliances such as fan, lights, and etc. A system that is

wireless yet independent from the internet.

Smart Phone Based

This design is a fine combination of smart phone technology and embedded system. Host can control

appliances using smart phone. An application should be installed on the smart phone to control various

70

appliances to send command using that application wirelessly controlled using Bluetooth technology

connected to the microcontroller circuit board turning the appliance on/off depending on the command

given.

Figure 3-61. Smartphone- based System Block Diagram

Any smart phone with any version of android installed an application called VT- 100 terminal emulator for

communicating with serial device using Bluetooth module will enable smart phones to send a command to

the microcontroller, this purpose needs an ASCI code which the controller receives.

Figure 3-62. The Application installed to Smart Phone

Relay

Relay

Relay

Device 1

Device 2

Device 3

Smart Phone

Bluetooth Module

Arduino

71

This figure shows the application that is installed to the smart phone and connected to the Bluetooth

module. It may require a password to connect and pair with the module to control the module for switching

the relay.

The HC-05 Linvor Bluetooth module is a user- friendly modue with Bluetooth serial port protocol designed

for transparent wireless serial connection set-up. The module has 34 PINS for configuration/interfacing of

Bluetooth module with microcontrollers.

Figure 3-63. Bluetooth Module

The figure shows the Bluetooth module used in this design guaranteeing connection to the microcontroller

and the relay driver controlling the devices connected to it.

This design is used to automate the appliances through smart phone and Bluetooth technology.

72

Program Used

char val;

int device=2, light=4, faucet=7;

void setup()

pinMode(device, OUTPUT);

pinMode(light, OUTPUT);

pinMode(faucet, OUTPUT);

Serial.begin (9600);

void loop()

if(Serial.available())

val=Serial.read();

if(val=='A')

digitalWrite(device, HIGH);

if(val=='a')

digitalWrite(device, LOW);

if(val=='B')

digitalWrite(light, HIGH);

if(val=='b')

digitalWrite(light, LOW);

if (val=='C')

digitalWrite(faucet, HIGH);

if(val=='c')

digitalWrite(faucet, LOW);

if(val=='D')



digitalWrite(faucet,HIGH);

if(val=='d')




delay(100);

73

Simulation Test

Figure 3-64. Arduino Uno Simulation Program

The image above shows the simulation of the program in Arduino Uno. The code is inserted to the program

and was run without error as indicated by the words “Done compiling”. The statement below indicated how

much of the memory of its capacity was used.

74

Option 2. Zilog

Figure 3-65. Pin Configuration of Z8F08XA

The above figure is a Z8 Encore series from Zilog which can operate up to 20Mhz it is marketed as a

microcontroller suitable for a variety of applications including motor control, security systems,

home appliances, personal electronic devices and sensors.

Figure 3-66. Zilog Schematic Diagram

75

Zilog Components List


2 LED

2 220Ω Resistor

1 10KΩ Resistor

2 10µF Capacitor

20MHz Clock Crystal

2 15pF Capacitor

Z8F08XA

Momentary Tact Switc

Figure 3-67. Zilog PCB LAYOUT

The figure shows the pcb layout for the Zilog Z8Encore development board. This microcontroller based

project board is paired with a JTAG programmer built around the MAX232E which is designed alongside

the main control board. This helps with writing programs through the software dedicated for Zilog uses.

76

Current Consumption

Power Dissipation

Speed

Memory

Data Retention

Slew Rate Connection of Devices

WIFI Based

Figure 3-68. WIFI- based System Block Diagram

This figure shows a WIFI based sensor capable of using secure accounts in standard web protocol to

ensure the program to be sent in a home router making new deployment an easy task.

Wireless

Sensor Nodes

(WASPMOTE)

Motion Sensor (PIR)

Router

ETHERTEN

Arduino

Relay

Relay

Relay

Device 1

Device 2

Device 3

77

Motion Sensor

Figure 3-69. PIR Sensor

This figure shows the motion sensor used connected to the WASPMOTE with a pyroeletric sensor mainly

consisting of an infra-red receiver and a focusing lens that can detect the reflection of movement by setting

its output signal high.

The 10 µm spectrum corresponds to the radiation of heat from the majority of objects as they emit

temperatures around 36ºC. The maximum detection direction goes perpendicular to the sensor board, this

is why it is advised to place WASPMOTE perpendicular to the ground when using the PIR sensor.

The code used for reading the PIR sensor

int value; SensorEventv20.ON(); delay(10); value = SensorEventv20.readValue(SENS_SOCKET7);

Value is an integer variable where the sensor state a high value (1), indicating a presence, or a low value

(0) will be stored. WASPMOTE configurations allow connecting up to six sensor probes at the same time

where the perimeter access control such liquid presence detection and doors or windows openings. The

sensor data gathered by the nodes is sent to the gateway router that is easier to receive which parse it and

store the data into a local or external data base.

Using Ether Ten, the gateway router is connected to the microcontroller board which is the head of the

operation that control the opening of the devices, and these devices are then connected to relay driver.

This can work alongside the exiting remotes to turn on and off the relay and a fly back diode to protect the

transistor and Ether Ten from the voltage spike generated by the device. This process is shows in the

figure below.

78

Figure 3-70. Connection of Sensors to Router to the Microcontroller

This figure shows how the sensors are connected through WiFi to the router that is then connected to the

microcontroller, which controls the devices.

Bluetooth Based

Bluetooth technology is the wireless automation used in this process. Standards based and low power

Bluetooth technology enables the development of devices’ application.

Figure 3-71. Bluetooth- based System Block Diagram

Relay

Relay

Relay

Device 1

Device 2

Device 3

Bluetooth

Shield

Motion Sensor (PIR)

Bluetooth Module

Arduino

79

This figure shows how blue technologies control a system of lighting, door and windows lock with an

application. It can simplify daily task by setting up alerts about their home.

The PIR is connected to the Bluetooth shield card. The data detected will be sent to the Bluetooth Module

and can be controlled by a microcontroller or an arduino shown below in figure.

Figure 3-72. PIR connected to Bluetooth Shield

This figure shows the PIR sensor used as a triggering device for the Bluetooth module connected to the

microcontroller for opening the device.

The Bluetooth module is configured or interfaced with the microcontroller while it does the main processing

part for the control, i.e. switching ON and OFF a relay. The relay acts a switch for AC appliances shown in

the figure below.

Figure 3-73. Process of Automation System Using Bluetooth Technology

80

The figure shows a system able to turn ON/OFF appliances such as fan, lights, and etc. A system that is

wireless yet independent from the internet.

Smart Phone Based

This design is a fine combination of smart phone technology and embedded system. Host can control

appliances using smart phone. An application should be installed on the smart phone to control various

appliances to send command using that application wirelessly controlled using Bluetooth technology

connected to the microcontroller circuit board turning the appliance on/off depending on the command

given.

Figure 3-74. Smartphone- based System Block Diagram

Any smart phone with any version of android installed an application called VT- 100 terminal emulator for

communicating with serial device using Bluetooth module will enable smart phones to send a command to

the microcontroller, this purpose needs an ASCI code which the controller receives.

Relay

Relay

Relay

Device 1

Device 2

Device 3

Smart Phone

Bluetooth Module

Arduino

81

Figure 3-75. The Application installed to Smart Phone

This figure shows the application that is installed to the smart phone and connected to the Bluetooth

module. It may require a password to connect and pair with the module to control the module for switching

the relay.

The HC-05 Linvor Bluetooth module is a user- friendly modue with Bluetooth serial port protocol designed

for transparent wireless serial connection set-up. The module has 34 PINS for configuration/interfacing of

Bluetooth module with microcontrollers.

Figure 3-76. Bluetooth Module

The figure shows the Bluetooth module used in this design guaranteeing connection to the microcontroller

and the relay driver controlling the devices connected to it.

This design is used to automate the appliances through smart phone and Bluetooth technology.

82

Program Used

char val;

int device=2, light=4, faucet=7;

void setup()

pinMode(device, OUTPUT);

pinMode(light, OUTPUT);

pinMode(faucet, OUTPUT);

Serial.begin (9600);

void loop()

if(Serial.available())

val=Serial.read();

if(val=='A')


if(val=='a')


if(val=='B')


if(val=='b')


if (val=='C')

digitalWrite(faucet, HIGH);

if(val=='c')


if(val=='D')



digitalWrite(faucet,HIGH);

if(val=='d')




delay(100);

2

Simulation Test

Figure 3-77. Arduino Uno Simulation Program

The image above shows the simulation of the program in Arduino Uno. The code is inserted to the program

and was run without error as indicated by the words “Done compiling”. The statement below indicated how

much of the memory of its capacity was used.

3

Chapter 4. Constraints, Trade – offs, and Standards Design Constraints This chapter explains the different constraints used in this project. The design constraint describes the limitations about how a specific system is made or about the system’s requirements. These constraints are important to consider as it sets up a boundary as well as confirming with the requirements specified when designing the project. The following are the constraints considered during the design procedure: Economic With the design project aimed at a lower-cost perspective it is a must to go to a more practical and economical approach. Having said that, it must be considered whether or not the process involved, be it service or construction, will be profitable or if it will change the way the design is made making it unprofitable. This constraint also includes the estimated total cost over the life span of the location it will be implemented into considerations. Additionally, factors like fabrication and shipping, ease of installation, and maintenance cost are also a part of it. Establishing a balance between required reliability and its subsequent cost is also a must. To total it all, the design must be backed by an economic study to prove that all methods, services, and materials used will be comparable in terms of cost to other designs that has an identical reliability. Manufacturability Since most of the designs presented is of custom construction the design will look for the manufacturability factor for the project’s components such as the core material in essence different CPLD ICs (Altera, Xilinx, and Lattice), and also the availability of these components within the country or shipping locations. The design will also put into consideration the time it takes to construct the whole project along with the time allotted to the miscellaneous task such as ordering, shipment, and also the delivery period of the design project’s components. Sustainability The equipments used as well as the material’s quality and performance under the normal operating conditions should be defined within the design. Proper compatibility between the design project’s parts, materials, and equipment alongside similar characteristic and factors should be considered so that it coincides with the other designs as well.

4

Design Standards This design project conforms to the following codes and standards and references:

IEEE Std. 802.11 Wireless Standards

IEEE Std. 802.15.1 Bluetooth Technology

IEEE Std. 802.3 2012 Ethernet

IEEE Std. 802.15.4 Physical and MAC Layer for Low-Rate Wireless Personal Area Network (LR-WPAN)

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support

IEEE Std. 1532 Boundary-Scan-based In System Configuration of Programmable Devices

Table 4-1. IEEE 802.11 Wireless Standards

IEEE Standard 802.11a 802.11b 802.11g 802.11n

Year Released 1999 1999 2003 2009

Frequency 5 GHz 2.4 GHz 2.4 GHz 2.4/5 GHz

Max. Data Rate 54 Mbps 11 Mbps 54 Mbps 600 Mbps

802.11 is more commonly referred as Wi-Fi. Table 2-1 shows the standard for the Wireless Local Area Network. This standard has been developed throughout the years and became faster and better in terms of range with every alteration. 802.11a - the second extension of the original 802.11 standard which has fast maximum speed which

supports up to 54 Mbps that operates at 5 GHz. 802.11b - the first extension of the original 802.11 standard released at the same time as 802.11a but

gained more popularity than the latter. It supports up to 11 Mbps that operates a 2.4GHz. 802.11g - combines the best of both 802.11a and 802.11b which supports up to 2.4 GHz that operates at

54 Mbps. 802.11n - was designed to improve 802.11g’s amount of bandwidth support up to 600 Mbps that operates

at 2.4/5 GHz which is backwards compatible with 802.11b/g.

Table 4-2. Bluetooth Technology Standard

Bluetooth Technology

Year Released 1999 Frequency 2.4 GHz Range (m) 1 – 10 m

Max. Data Rate 720 Kb/s

5

Trade-Offs

Economic

Components and Price of All Design

Xilinx

Components Value No. of Components Price Amount

330 Ohm 0.25 watts 34 Php 0.5 17

240 Ohm 0.25 watts 1 Php 0.5 0.5

1M Ohm 0.25 watts 1 Php 1 1

390 Ohm 0.25 watts 1 Php 0.5 0.5

100uF (Electrolytic) 10 volts 2 Php 5 10

0.1uF (Ceramic) 10 volts 5 Php 2 10

100uF (Ceramic) 10 volts 3 Php 5 15

XC9536 1 Php 130 130

1N4001 1 Php 8 8

LM317TS 1 Php 40 40

TLC555 1 Php 21 21

PIR 5 Php 525 2625

CNET Wireless- N Broadband Router

1 Php 680 680

XBee XB24 Z7CIT 1 Php 1210.68 1210.68

XBee XB24 Z7WIT 1 Php 1645 1645

Total Php 6413.68

TABLE 4-3 Xilinx Total Price

6

Altera


330 Ohm 0.25 watts 34 Php 0.5 17

240 Ohm 0.25 watts 1 Php 0.5 0.5

1M Ohm 0.25 watts 1 Php 1 1

390 Ohm 0.25 watts 1 Php 0.5 0.5

100uF (Electrolytic) 10 volts 2 Php 5 10

0.1uF (Ceramic) 10 volts 5 Php 2 10

100uF (Ceramic) 10 volts 3 Php 5 15

EPM9572 1 Php 1036.50 1036.50

1N4001 1 Php 8 8

LM317TS 1 Php 40 40

TLC555 1 Php 21 21

PIR 5 Php 525 2625

CNET Wireless- N Broadband Router

1 Php 680 680

XBee XB24 Z7CIT 1 Php 1210.68 1210.68

XBee XB24 Z7WIT 1 Php 1645 1645

Total Php 7320.18

TABLE 4-4 Altera Total Price

7

Atmel



1 Php 15 15

LED 2 Php 3 6

220Ω Resistor 0.25 watts 2 Php 0.5 1

10KΩ Resistor 0.25 watts 1 Php 0.5 0.5

10µF Capacitor 10 volts 2 Php 0.75 1.5

16MHz Clock Crystal 1 Php 20 20

22pF Capacitor 6.3 volts 1 Php 1 1

ATMEGA 168 0.25 watts 1 Php 315.70 315.70


6.3 volts 1 Php 5 5

ETHERTEN 1 Php 3262.5 3262.50

WaspMote 1 Php 6996.08 6996.08

Total Php 10624.28

TABLE 4-5 Atmel Total Price

8

Zilog



1 Php 15 15

LED 2 Php 3 6

220Ω Resistor 0.25 watts 2 Php 0.5 1

10KΩ Resistor 0.25 watts 1 Php 0.5 0.5

10µF Capacitor 10 volts 2 Php 0.75 1.5

16MHz Clock Crystal 1 Php 20 20

22pF Capacitor 6.3 volts 1 Php 1 1

78F0422 0.25 watts 1 Php 256.10 256.10


6.3 volts 1 Php 5 5

ETHERTEN 1 Php 3262.5 3262.50

WaspMote 1 Php 6996.08 6996.08

Total Php 10564.68

TABLE 4-6 Zilog Total Price

9

Raw Designer’s Ranking Formula If the governing value is greater than the value to be ranked use:

If the governing value is less than the value to be ranked use:

10

Computations for Trade Offs Economic *Altera

Sustainability *Altera

Total Ranking Total (Altera):

Total (Xilinx):

Criteria Criterion’s Importance

Altera Xilinx

Economic 5 Php 7320.18 4 Php 6413.68 5

Sustainability 4 175.4 Mhz 2 178 Mhz 4

Manufacturability 3 4 days 3 4 days 3

Total 42 50

Table 4-7 CPLD Trade Offs

11

Economic *Atmel

Sustainability *Zilog

Total Ranking Total (Atmel):

Total (Zilog):


Atmel Zilog

Economic 5 Php 10624.28 4 Php 10564.68 5

Sustainability 4 16 KB 4 8 KB 1

Manufacturability 3 1 day 3 1 day 3

Total 45 38

Table 4-8 Microcontroller Tradeoffs

12

Economic *Atmel

Sustainability *Atmel

Manufacturability *Xilinx

Total Ranking Total (Atmel):

Total (Xilinx):


Atmel Xilinx

Economic 5 Php 10624.28 1 Php 6413.68 5

Sustainability 4 20 MHz 1 178 MHz 4

Manufacturability 3 1 day 3 4 days 1

Total 18 44

Table 4-9 Microcontroller vs CPLD Tradeoffs

13

Chapter 5. Final Design


Xilinx

Economic 5 Php 6413.68 5

Sustainability 4 178 MHz 4

Manufacturability 3 4 days 1

Total 44

Table 5-1 Xilinx Design Constraints Ratings

Xilinx

Figure 5-1. XC9500XL Architechture

This figure shows the architechture for a typical CPLD of Xilinx. It is a subsystem consisting of Function Blocks and I/O Blocks Fully interconnected by the FASTCONNECT II switch matrix. Each Function Blocks provides programmable logic capabiity with 54 inputs and 18 outputs. The inputs and outputs are designated by the macrocells which may be configured for a combinational or registered function.

14

Figure 5-2. Xilinx Schematic Xilinx Components List

Resistors

34 pcs. – 330 ohm

1 pc. – 240 ohm

1 pc. – 390 ohm

1 pc. – 1 M ohm

7 pcs. – 100 ohm

1 pc. – 1 k ohm

1 pc. – 5 k ohm


1 pc. – XC9536

1 pc. – LM317TS

1 pc. – TLC555

2 pcs. – 74HC125

1 pc. – 1N4001 diode

2 pcs. – Bat41

Capacitors

1 pc. – 47 nF

1 pc. – 10 nF

2 pcs. – 100 uF

6 pcs. – 100 uF

4 pcs. – 100 pF

15






16

Current Consumption

Power Dissipation

Speed

Memory

Data Retention

Slew Rate

17

Figure 5-4. Xilinx PCB Layout

This figure shows the PCB layout for Xilinx CPLD Board. The board can work with both XC9536 which is a

version of circuit powered from 5V. The circuit is powered by a selectable output voltage power supply

LM317TS from 3.3 up to 5.5v. Each pin is in two versions, the standard which is not secured and the

secured which is in series with the 330 ohm resistor to protect the I/O pins against accidental short-circuit.

Without the resistor inputs would be burned in a short time.

18

Design 2

Figure 5-5. Xilinx Design 2 Scematic

The second design for Xilinx shown in the figure above is implemented with RS232, a Universal





19

Figure 5-6. Xilinx Design 2 PCB Layout

The figure showing a pcb layout showcases the Xilinx design with the RS232 implemented. The same

alteration done in the design 2 of the Altera is applied here.

20

Figure 5-7. Simulation Output

The figure above shows the graphical representation of the simulation output. The pulses indicate whether

the output is low or high or whether it is in the on or off condition.

Figure 5-8. Program Code

21

For figure 3-26 designated the wire of AO2-AO6 as output and for line 46 – line 64 of the program shows

the instantiate of the UTT which the process before initialization.


Figure 3-27 shows the program line 65-79 is the end of instantiate of the UTT. And for line 81 stated to

initial begin for inputs for line 81 to 84, line 87-90 and line 92-95 run the condition of inputs then show the

output in AO1 pin port in ISIM. The value 0 means that the sensor detected no movement, the value 1

means that the sensor detected a movement.

22


Figure 3-28 shows the continuation of the conditions for IA1, IA2, IA3 inputs which are in program line 97-

100, 102-105, 107-110, 112-115, 117-120. And for 122-125 is another set of inputs for the output AO2.

23


For Figure 3-29 shows the continuation of the conditions for inputs IA5, IA6 and IA4.


Figure 3-30, the continuation for conditioning of inputs.

24





25





26





27





28


The figure above shows in line 3 the timescale for simulation and for line 8-31 register IA1 – IA 24 as

inputs.


Figure 3-40 show the CPLD reports for the program simulated.

29

Figure 5-23. Schematic of Light Openner

Figure 3-41 shows the schematic diagram which will be converted to VHDL code. Inverter is the sensor which will be placed at the door either is open or closed means if it is close the value is 1 and vise versa then connected to 1 input of the 2 AND gate as the sensor placed within the range. Interfacing the Devices


30




Design 1







or OFF.

Design 2




Transceiver UART

CPLD Zigbee Module

Transceiver


Zigbee Module




Transceiver Modem

CPLD

Zigbee Module



31









operation.

32

Conclusion After several researches, analysis of data, and decision making process, the design making for the CPLD

and Microcontroller boards is completed. The impact each constraint have on making this project had been

carefully evaluated and identified. The constraints that the proponents considered in the design are

Economic, Sustainability and Manufacturability. It is also the basis on how the proponents have attained

the layout and designs. For this project design, the proponents showed the advent of a low-power CPLDs

over microcontroller and to have new option for electronic product designer in implementing many functions

traditionally performed by microcontroller. Also, CPLD allows them to use a software program to

reconfigure the operation of the hardware which is alike to a microcontroller but CPLD have a vast array of

features and packages, abundance of software development tools, and huge libraries of application code.

As beginners, the proponents found out that the aspects of CPLD design is similar with traditional

microcontrollers i.e. CPLDs can be made first by schematic diagram then converted in a high-level

language, such as Verilog or VHDL, design can be simulated for functional and timing correctness, design

can be fitted to a particular CPLD providing physical aspects such as resource utilization and timing path,

and design is programmed into the physical device.

For this, section the proponents determined the application where a CPLD can cost-effectively overpass a

microcontroller. Firstly, the I/O management which is the quantity and the type I/O’s needed is two critical

considerations. Microcontroller offer and has a good reputation in small and inexpensive project however if

an application requires a large quantity of general purpose of I/Os. CPLD can be cost-competitive with a

microcontroller which are usually limited to serial ports also the proponents discover that microcontrollers

with dozens of I/Os are no longer small and inexpensive. CPLDs, on the other hand can offer a small form

factor to have well over 50 I/Os which is the maximum I/Os in microcontroller.

Programmable Level Shifting is also the advantage in CPLD over microcontroller many products require the

use of logic devices of varying voltages. This is rarely possible with a microcontroller because they have

limited number of I/O resources and also often operate from one voltage source. In contrast CPLDs have a

larger number of I/Os, which are grouped into multiple banks. Each I/O Banks can assign unique voltage

source.

Pulse Width Modulation (PWM) most microcontrollers have ports that dedicated function as a PWM port.

That can be accomplish also by CPLD’s even though do not have dedicated circuitry, yet it is not difficult to

implement a PWM output for example in MAX 7000 CPLD contains an internal oscillator that can be used

as a source for the frequency.

Power sequencing Altera Max7000 devices are optimized for many system management functions such as

power sequencing, which includes multi-voltage system power up and system reset, as well as a chip

select generation. Multi-voltage power sequencing requires a device to be instantly on and ready to

manage the power-up sequencing of other devices on the PCB. Therefore a CPLD, which power up within

microseconds, is a better choice for power sequencing than microcontroller, which often needs milliseconds

to power up.

33

Recommendation: The proponents would like to recommend the following according to the project’s result:

Relying only on one (1) reference standard book is unadvisable since there are different books to choose from. It should also be made a point that all the standards and rules to be used must be followed.

It is best to find a better way to meet the requirements needed whilst also complying with the constraints set upon by the group so that the result would be efficiently done that it would reflect upon the paper.

In making a CPLD development board, be sure to check on local availability of the components to be use and make note of shipping times if localized stock(s) are not available. It would not just save time but also make you prepared in terms of knowledge about the component’s availability.

DON’T EVER TRY IT.

design and development of a cpld board revised v2.0 1 new version

Documents

project design

project development

project objectives

project site

project scope

project background

design inputs

design considerations